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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.7k 256

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 857 183

  3. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 484 99

  4. riscv-rvv-intrinsic-doc riscv-rvv-intrinsic-doc Public

    C 381 112

  5. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 225 57

  6. riscv-iommu riscv-iommu Public

    RISC-V IOMMU Specification

    C 172 35

Repositories

Showing 10 of 36 repositories
  • riscv-semihosting Public
    riscv-non-isa/riscv-semihosting's past year of commit activity
    Makefile 32 CC-BY-SA-4.0 10 2 2 Updated Nov 2, 2026
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu's past year of commit activity
    C 172 CC-BY-4.0 35 1 3 Updated Nov 1, 2026
  • riscv-ras-eri Public

    The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors, and configuration.

    riscv-non-isa/riscv-ras-eri's past year of commit activity
    TeX 12 CC-BY-4.0 7 0 1 Updated Nov 1, 2026
  • riscv-cbqri Public

    This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

    riscv-non-isa/riscv-cbqri's past year of commit activity
    Makefile 7 CC-BY-4.0 8 0 1 Updated Nov 1, 2026
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security's past year of commit activity
    Makefile 20 CC-BY-4.0 6 2 1 Updated Oct 30, 2026
  • riscv-rpmi Public

    RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

    riscv-non-isa/riscv-rpmi's past year of commit activity
    Makefile 25 CC-BY-4.0 17 4 1 Updated Oct 29, 2026
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs's past year of commit activity
    Shell 59 CC-BY-4.0 24 17 3 Updated Oct 28, 2026
  • riscv-iopmp Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/riscv-iopmp's past year of commit activity
    C 42 CC-BY-4.0 11 6 6 Updated Oct 27, 2026
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc's past year of commit activity
    Python 857 CC-BY-4.0 183 66 26 Updated Oct 27, 2026
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec's past year of commit activity
    C 225 CC-BY-4.0 57 4 0 Updated Oct 23, 2026
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