Minira

A minimal communication protocol for communication between 2 FPGAs over LVDS PHY.

Purpose:

To be used when one FPGA is used as a debugger of another FPGA.

Guide:

• The main branch has 3 directories:
  • loopback_minira: Used loopback PCB for initial prototyping of the design code. It will be dumped on single Vaaman, to check functionality of LVDS pins and the design code.
  • simplex_minira: Used LVDS cables, with cables for both LVDS Rx and Tx, we can have send 64 bits from sender to receiver. Read only.
  • duplex_minira: Used LVDS cables, it is used for both read and write operations with 32 bits data width for each.
• First you should go through the loopback_minira branch. The issues mentioned there are solved in other 2 branches.
• If you want to use any one of these functionalities, you can checkout to its respective branch.
• 55 MHz used because RAH works on 54 MHz.
• *.peri.xml is available for all the functioanlites, but always cross check the interface designer.