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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 117 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 25 Apache-2.0 54 147 (6 issues need help) 36 Updated Apr 6, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 146 Apache-2.0 95 225 (10 issues need help) 72 Updated Apr 6, 2026
  • firtool-resolver Public
    chipsalliance/firtool-resolver’s past year of commit activity
    Shell 5 2 0 3 Updated Apr 6, 2026
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    391 Apache-2.0 63 74 12 Updated Apr 6, 2026
  • rocket-pcb Public

    PCB libraries and templates for rocket-chip based FPGA/ASIC designs

    chipsalliance/rocket-pcb’s past year of commit activity
    Verilog 16 Apache-2.0 4 0 1 Updated Apr 6, 2026
  • rocket-pcblib Public
    chipsalliance/rocket-pcblib’s past year of commit activity
    2 Apache-2.0 1 0 0 Updated Apr 6, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 46 Apache-2.0 24 10 1 Updated Apr 6, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 9 6 0 0 Updated Apr 6, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 43 796 0 1 Updated Apr 5, 2026
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 455 Apache-2.0 79 47 (2 issues need help) 0 Updated Apr 5, 2026
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