🌍 SUSTech CS202 2025 Spring course project, a single-cycle CPU and a 5-stage pipeline CPU based on Verilog, supporting RISC-V assembly language.
Single-cycle CPU | Pipeline CPU
中文文档见：README-cn
| Name | Name | Last commit date | ||
|---|---|---|---|---|
🌍 SUSTech CS202 2025 Spring course project, a single-cycle CPU and a 5-stage pipeline CPU based on Verilog, supporting RISC-V assembly language.
Single-cycle CPU | Pipeline CPU
中文文档见：README-cn