fix(IMSIC): declare AXI slave interleaved ID - #46
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AXIRegIMSIC_WRAP is consumed by RocketChip AXI4 diplomacy. TLToAXI4 requires every reachable AXI4 slave to define the same interleavedId, so mark the REE and TEE IMSIC slave ports as non-interleaving. This only describes the AXI response ordering guarantee and does not change the IMSIC register FSM or AXI write handshake behavior.
zhaohong1988
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Jun 18, 2026
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yes, to match with the use from top
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AXIRegIMSIC_WRAP is consumed by RocketChip AXI4 diplomacy. TLToAXI4 requires every reachable AXI4 slave to define the same interleavedId, so mark the REE and TEE IMSIC slave ports as non-interleaving.
This only describes the AXI response ordering guarantee and does not change the IMSIC register FSM or AXI write handshake behavior.