Archdetect riscv update#243
Conversation
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I think this update makes sense as it certainly gives more flexibility and would allow working with subsets of extensions instead of matching the whole ISA string. I suggest to change the comment in as it explains better why the replacement is done. The tokens here are just features/extensions and do not translate to compilation flags (in contrast with x86). At the end, when building we will need the ISA string (with underscores) anyway to pass it to the Which makes me think... if we do: where/how is the ISA string to pass to |
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New job on instance
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This update will treat the isa line from a riscv cpu (e.g. rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt) and sed it into seperate flags which can be matched as relevant (!) features, the same way we do for x86_64. This should allow cpu's with the same relevant features, but from different vendors to be matched to the same cpu paths.