An 8-bit CPU built entirely from scratch in Logisim. Every component was constructed using only basic AND, OR, XOR, and NOT gates, which were combined and reused to build the CPU's registers, ALU, memory, control unit, and other components.
The CPU is fully programmable through its custom instruction set and is capable of running programs stored in its RAM. As a demonstration, the included program calculates the Fibonacci sequence up to 233 and then repeats.
The CPU was built using Logisim 2.7.1.
- Download logisim-generic-2.7.1.jar.
- Open
logisim-generic-2.7.1.jar. - Open 8-Bit CPU.circ.
When opening the project, the program has to be manually transferred from ROM to RAM before the CPU can execute it.
- Enable manual control of the instruction bus.
- Set EN (ROM) to
1. - Set WR (RAM) to
1. - Let the clock tick until the program has been transferred to RAM.
- Set EN (ROM) back to
0. - Disable manual control of the instruction bus.
The control unit can now control the instruction bus and the CPU will begin executing the program.
Every component of the CPU was built from scratch using simple logic gates.
- 8-bit address bus
- 8-bit data bus
- Instruction bus, which can be controlled either manually or by the control unit
The Arithmetic Logic Unit contains:
- AU — Arithmetic Unit for addition and subtraction
- AND
- OR
- XOR
- NOT
- LLS — logical left shift
- LRS — logical right shift
- RLC — rotate left through carry
- RRC — rotate right through carry
The ALU provides four flags:
- ZF — Zero Flag
- SF — Sign Flag
- CF — Carry Flag
- P/VF — Parity/Overflow Flag
The CPU contains 256 bytes of RAM with:
- Self-built address encoder
- Self-built address decoder
- Self-built 8-bit registers
- 8 general-purpose registers
- Program Counter
- Instruction Register
- Output Register
- Control Unit
The control unit translates the 8-bit instruction stored in the Instruction Register, together with the four ALU flags, into the corresponding control signals on the instruction bus.
The CPU has a 3-digit decimal display consisting of:
- 3 × 7-segment displays
- 3 × BCD-to-7-segment decoders
- A self-built dual-BCD decoder
The output register provides an 8-bit value which is converted into a three-digit decimal representation and displayed on the 7-segment displays.
The CPU uses a custom 8-bit instruction set. The complete instruction set and instruction encoding are documented in:
The instruction set makes the CPU programmable, allowing programs to be written and executed by the processor.
The included program calculates the Fibonacci sequence up to 233, the largest Fibonacci number that can be represented using an unsigned 8-bit value, and then repeats the calculation.
The program instructions are:
MVI001 1 MVI000 1 OUT000 ANI 0 ADD000 ADD001
STA 3 MOV001000 JNC 2 LDA 6 STA 3 JMP 0
Encoded in hexadecimal:
69 01 68 01 98 82 00 00 01 89 03 C8 92 02 88 06 89 03 8A 00
The resulting Fibonacci values are displayed on the three 7-segment displays.