VHDL-Programming

VHDL program which runs in Xilinx ISE.

Name		Name	Last commit message	Last commit date
Latest commit History 29 Commits
1 BIT COMPARATOR		1 BIT COMPARATOR
10 to 4 bit priority encoder		10 to 4 bit priority encoder
1:8 DEMUX		1:8 DEMUX
4 BIT COMPARATOR _EQUAL OUT		4 BIT COMPARATOR _EQUAL OUT
4 is to 1 MUX		4 is to 1 MUX
8 : 1 MUX		8 : 1 MUX
AND Gate		AND Gate
DFLIPFLOP		DFLIPFLOP
Delay		Delay
FULL ADDER		FULL ADDER
FULL SUBTRACTOR		FULL SUBTRACTOR
HALF SUBTRACTOR		HALF SUBTRACTOR
Half Adder		Half Adder
JK FLIPFLOP		JK FLIPFLOP
NAND Gate		NAND Gate
NOR Gate		NOR Gate
NOT Gate		NOT Gate
OR Gate		OR Gate
README.md		README.md
SR FLIPFLOP		SR FLIPFLOP
T FLIPFLOP		T FLIPFLOP
XNOR Gate		XNOR Gate
XOR Gate		XOR Gate
comparator.vhdl		comparator.vhdl
dflipflop in structural model		dflipflop in structural model

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