SAFARI Research Group at ETH Zurich and Carnegie Mellon University
- 889 followers
- ETH Zurich and Carnegie Mellon University
- https://safari.ethz.ch/
- omutlu@gmail.com
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Repositories
- DPC4 Public
The GitHub repository containing all resources used in the 4th Data Prefetching Championship (DPC4), co-located with HPCA 2026.
CMU-SAFARI/DPC4’s past year of commit activity - prim-benchmarks Public
PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (https://arxiv.org/abs/2105.03814).
CMU-SAFARI/prim-benchmarks’s past year of commit activity - DRAM-Bender Public
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
CMU-SAFARI/DRAM-Bender’s past year of commit activity - Athena Public
A reinforcement learning based policy to dynamically coordinate off-chip predictor with multiple data prefetchers, as described in the HPCA2026 paper by Bera and Lang et al.: https://arxiv.org/abs/2601.17615
CMU-SAFARI/Athena’s past year of commit activity - Pythia Public
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
CMU-SAFARI/Pythia’s past year of commit activity - Hermes Public
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
CMU-SAFARI/Hermes’s past year of commit activity - ramulator2 Public
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
CMU-SAFARI/ramulator2’s past year of commit activity - Cleaning-up-the-Mess Public
Source code for the Ramulator 2.0, DAMOV and Standalone Ramulator used in our ISPASS 2026 paper "Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0". Paper: https://arxiv.org/abs/2510.15744
CMU-SAFARI/Cleaning-up-the-Mess’s past year of commit activity - RawBench Public
A comprehensive benchmarking framework for raw nanopore signal analysis, as described by Eris et al. (https://arxiv.org/pdf/2510.03629)
CMU-SAFARI/RawBench’s past year of commit activity - Proteus Public
Source code for the architectural simulator used for modeling the PUD system proposed in our ICS 2025 paper `Proteus: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic''. Paper is at: https://arxiv.org/pdf/2501.17466
CMU-SAFARI/Proteus’s past year of commit activity
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