From b14b1d262e9bd39d542f8d9c6b78e58bbfe45f5d Mon Sep 17 00:00:00 2001 From: Stephen Tridgell Date: Mon, 10 Aug 2015 13:41:22 +1000 Subject: [PATCH 1/3] Move emitDef from Verilog to backend; Removed seemily redundant nameAll as called further down; Not passing tests as emitRef is called twice in some situations; Valid code is generated but does not start at T0 --- src/main/scala/Backend.scala | 8 ++++++-- src/main/scala/Verilog.scala | 4 +--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/Backend.scala b/src/main/scala/Backend.scala index e13ebfb0..09d9abbc 100644 --- a/src/main/scala/Backend.scala +++ b/src/main/scala/Backend.scala @@ -192,6 +192,8 @@ abstract class Backend extends FileSystemUtilities{ comp dfs { case reg: Reg if reg.name == "" => reg setName "R" + reg.component.nextIndex + case clk: Clock if clk.name == "" => + clk setName "C" + clk.component.nextIndex case node: Node if !node.isTypeNode && node.name == "" && node.compOpt != None => node.name = "T" + node.component.nextIndex case _ => @@ -207,6 +209,8 @@ abstract class Backend extends FileSystemUtilities{ comp dfs { case reg: Reg => reg setName namespace.getUniqueName(reg.name) + case clk: Clock => + clk setName namespace.getUniqueName(clk.name) case node: Node if !node.isTypeNode && !node.isLit && !node.isIo => { // the isLit check should not be necessary // the isIo check is also strange and happens because parents see child io in the DFS @@ -250,6 +254,8 @@ abstract class Backend extends FileSystemUtilities{ node.name case _: Reg => if (node.named) node.name else "R" + node.emitIndex + case _: Clock => + if (node.named) node.name else "C" + node.emitIndex case _ => if (node.named) node.name else "T" + node.emitIndex } @@ -814,8 +820,6 @@ abstract class Backend extends FileSystemUtilities{ verifyComponents - ChiselError.info("giving names") - nameAll ChiselError.checkpoint() ChiselError.info("executing custom transforms") diff --git a/src/main/scala/Verilog.scala b/src/main/scala/Verilog.scala index 05af1bb0..7294e12a 100644 --- a/src/main/scala/Verilog.scala +++ b/src/main/scala/Verilog.scala @@ -101,10 +101,8 @@ class VerilogBackend extends Backend { override def emitRef(node: Node): String = { node match { case x: Literal => emitLit(x.value, x.needWidth()) - case _: Reg => - if (node.name != "") node.name else "R" + node.emitIndex case _ => - if (node.name != "") node.name else "T" + node.emitIndex + super.emitRef(node) } } From cdec7a07cf1add7f8d1c06f7c5810b5bbe5b6bbe Mon Sep 17 00:00:00 2001 From: Stephen Tridgell Date: Tue, 11 Aug 2015 12:17:18 +1000 Subject: [PATCH 2/3] Put the first nameAll back in --- src/main/scala/Backend.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/Backend.scala b/src/main/scala/Backend.scala index 09d9abbc..555b493f 100644 --- a/src/main/scala/Backend.scala +++ b/src/main/scala/Backend.scala @@ -820,6 +820,8 @@ abstract class Backend extends FileSystemUtilities{ verifyComponents + ChiselError.info("giving names") + nameAll ChiselError.checkpoint() ChiselError.info("executing custom transforms") From ad9ea28a6737bff99ea95e7eaf55fc9e6a984b3f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 13 Aug 2015 14:52:53 -0700 Subject: [PATCH 3/3] Update MultiClockSuite_Comp_1.v success code. Don't use T0 for both clock and wire. --- src/test/resources/MultiClockSuite_Comp_1.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/test/resources/MultiClockSuite_Comp_1.v b/src/test/resources/MultiClockSuite_Comp_1.v index 9de9480c..870d022b 100644 --- a/src/test/resources/MultiClockSuite_Comp_1.v +++ b/src/test/resources/MultiClockSuite_Comp_1.v @@ -1,4 +1,4 @@ -module MultiClockSuite_ClockedSubComp_1(input T0, +module MultiClockSuite_ClockedSubComp_1(input C0, input io_ready, output io_valid ); @@ -17,12 +17,12 @@ module MultiClockSuite_ClockedSubComp_1(input T0, assign io_valid = stored; - always @(posedge T0) begin + always @(posedge C0) begin stored <= io_ready; end endmodule -module MultiClockSuite_Comp_1(input T0, +module MultiClockSuite_Comp_1(input C0, input io_data0, input io_data1, output io_result @@ -34,7 +34,7 @@ module MultiClockSuite_Comp_1(input T0, assign T0 = io_data0 & io_data1; assign io_result = sub_io_valid; - MultiClockSuite_ClockedSubComp_1 sub(.T0(T0), + MultiClockSuite_ClockedSubComp_1 sub(.C0(C0), .io_ready( T0 ), .io_valid( sub_io_valid ) );