From 45641c82e16b90df3fe1ac41bb63fa659b6d3637 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 21 Apr 2026 18:13:01 +0800 Subject: [PATCH 1/2] [bsp] update nuvoton board porting. - Support M3331 series. - Align nuvoton-series package only. --- .github/ALL_BSP_COMPILE.json | 3 +- bsp/nuvoton/docs/LVGL_Notes.md | 40 - bsp/nuvoton/libraries/m3331/README.md | 36 + bsp/nuvoton/libraries/m3331/SConscript | 15 + bsp/nuvoton/libraries/m3331/rtt_port/Kconfig | 550 ++++++ .../libraries/m3331/rtt_port/SConscript | 32 + .../m3331/rtt_port/cherryusb/SConscript | 10 + .../m3331/rtt_port/cherryusb/msh_cmd.c | 77 + .../m3331/rtt_port/cherryusb/usb_config.h | 264 +++ .../m3331/rtt_port/cherryusb/usb_hs_dc.c | 987 +++++++++++ .../m3331/rtt_port/cherryusb/usb_hs_otg.c | 107 ++ .../m3331/rtt_port/cherryusb/usb_sw_otg.c | 193 +++ .../m3331/rtt_port/cherryusb/usbd_hs_glue.c | 60 + .../cherryusb/usbh_ehci_custom_glue.c | 83 + .../libraries/m3331/rtt_port/drv_bpwm.c | 221 +++ .../m3331/rtt_port/drv_bpwm_capture.c | 385 +++++ .../libraries/m3331/rtt_port/drv_canfd.c | 691 ++++++++ .../libraries/m3331/rtt_port/drv_clk.c | 356 ++++ .../libraries/m3331/rtt_port/drv_common.c | 271 +++ .../libraries/m3331/rtt_port/drv_common.h | 36 + .../libraries/m3331/rtt_port/drv_crc.c | 231 +++ .../libraries/m3331/rtt_port/drv_crc.h | 19 + .../libraries/m3331/rtt_port/drv_crypto.c | 147 ++ .../libraries/m3331/rtt_port/drv_eadc.c | 303 ++++ .../libraries/m3331/rtt_port/drv_ebi.c | 50 + .../libraries/m3331/rtt_port/drv_ebi.h | 41 + .../libraries/m3331/rtt_port/drv_ecap.c | 277 +++ .../libraries/m3331/rtt_port/drv_epwm.c | 209 +++ .../m3331/rtt_port/drv_epwm_capture.c | 296 ++++ .../libraries/m3331/rtt_port/drv_eqei.c | 286 ++++ .../libraries/m3331/rtt_port/drv_eqei.h | 18 + .../libraries/m3331/rtt_port/drv_fmc.c | 391 +++++ .../libraries/m3331/rtt_port/drv_fmc.h | 22 + .../libraries/m3331/rtt_port/drv_gpio.c | 348 ++++ .../libraries/m3331/rtt_port/drv_gpio.h | 26 + .../libraries/m3331/rtt_port/drv_i2c.c | 373 ++++ .../libraries/m3331/rtt_port/drv_i2c.h | 40 + .../libraries/m3331/rtt_port/drv_i2s.c | 607 +++++++ .../libraries/m3331/rtt_port/drv_i2s.h | 84 + .../libraries/m3331/rtt_port/drv_llsi.c | 434 +++++ .../libraries/m3331/rtt_port/drv_llsi.h | 44 + .../libraries/m3331/rtt_port/drv_log.h | 23 + .../libraries/m3331/rtt_port/drv_pdma.c | 1261 ++++++++++++++ .../libraries/m3331/rtt_port/drv_pdma.h | 109 ++ .../libraries/m3331/rtt_port/drv_qspi.c | 417 +++++ .../libraries/m3331/rtt_port/drv_qspi.h | 12 + .../libraries/m3331/rtt_port/drv_rtc.c | 242 +++ .../libraries/m3331/rtt_port/drv_sdio.c | 762 +++++++++ .../libraries/m3331/rtt_port/drv_softi2c.c | 219 +++ .../libraries/m3331/rtt_port/drv_spi.c | 705 ++++++++ .../libraries/m3331/rtt_port/drv_spi.h | 48 + .../libraries/m3331/rtt_port/drv_spii2s.c | 609 +++++++ .../libraries/m3331/rtt_port/drv_sys.h | 20 + .../libraries/m3331/rtt_port/drv_timer.c | 283 +++ .../libraries/m3331/rtt_port/drv_tpwm.c | 232 +++ .../libraries/m3331/rtt_port/drv_uart.c | 882 ++++++++++ .../libraries/m3331/rtt_port/drv_uart.h | 15 + .../libraries/m3331/rtt_port/drv_ui2c.c | 387 +++++ .../libraries/m3331/rtt_port/drv_uspi.c | 672 ++++++++ .../libraries/m3331/rtt_port/drv_uuart.c | 639 +++++++ .../libraries/m3331/rtt_port/drv_wdt.c | 421 +++++ bsp/nuvoton/libraries/m460/rtt_port/Kconfig | 820 +++------ bsp/nuvoton/libraries/m480/rtt_port/Kconfig | 670 +++----- bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig | 2 +- bsp/nuvoton/libraries/nu_packages/Kconfig | 55 +- bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig | 2 +- bsp/nuvoton/ma35-rtp/.config | 2 +- bsp/nuvoton/ma35-rtp/rtconfig.h | 2 +- bsp/nuvoton/nk-980iot/.config | 75 +- bsp/nuvoton/nk-980iot/SConstruct | 2 +- bsp/nuvoton/nk-980iot/config_lvgl | 1317 -------------- bsp/nuvoton/nk-980iot/rtconfig.h | 25 +- bsp/nuvoton/nk-n9h30/.config | 79 +- bsp/nuvoton/nk-n9h30/SConstruct | 2 +- bsp/nuvoton/nk-n9h30/rtconfig.h | 26 +- bsp/nuvoton/nk-rtu980/.config | 73 +- bsp/nuvoton/nk-rtu980/SConstruct | 2 +- bsp/nuvoton/nk-rtu980/rtconfig.h | 25 +- bsp/nuvoton/numaker-hmi-ma35d1/.config | 2 +- bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.h | 2 +- bsp/nuvoton/numaker-iot-m467/.config | 2 +- bsp/nuvoton/numaker-iot-m467/config_lvgl | 1204 ------------- bsp/nuvoton/numaker-iot-m467/rtconfig.h | 2 +- bsp/nuvoton/numaker-iot-m487/.config | 2 +- bsp/nuvoton/numaker-iot-m487/config_lvgl | 924 ---------- bsp/nuvoton/numaker-iot-m487/rtconfig.h | 2 +- bsp/nuvoton/numaker-iot-ma35d1/.config | 2 +- bsp/nuvoton/numaker-iot-ma35d1/rtconfig.h | 2 +- bsp/nuvoton/numaker-m032ki/.config | 2 +- bsp/nuvoton/numaker-m032ki/config_lvgl | 844 --------- bsp/nuvoton/numaker-m032ki/rtconfig.h | 2 +- bsp/nuvoton/numaker-m2354/.config | 2 +- bsp/nuvoton/numaker-m2354/rtconfig.h | 2 +- .../config_lvgl => numaker-m3334ki/.config} | 999 +++++++---- bsp/nuvoton/numaker-m3334ki/Kconfig | 14 + bsp/nuvoton/numaker-m3334ki/README.md | 61 + bsp/nuvoton/numaker-m3334ki/SConscript | 14 + bsp/nuvoton/numaker-m3334ki/SConstruct | 59 + bsp/nuvoton/numaker-m3334ki/Template.uvprojx | 392 +++++ .../numaker-m3334ki/applications/SConscript | 15 + .../numaker-m3334ki/applications/lv_conf.h | 104 ++ .../numaker-m3334ki/applications/main.c | 32 + .../numaker-m3334ki/applications/mnt.c | 70 + .../numaker-m3334ki/applications/pm_test.c | 251 +++ bsp/nuvoton/numaker-m3334ki/board/Kconfig | 82 + .../numaker-m3334ki/board/Kconfig_Board_NUFUN | 143 ++ .../numaker-m3334ki/board/Kconfig_Board_NUTFT | 49 + .../numaker-m3334ki/board/NTFUN_board_dev.c | 187 ++ .../numaker-m3334ki/board/NUTFT_board_dev.c | 117 ++ .../NuPinConfig/M3334KIGAE(LQFP128).ncfg | 188 ++ .../board/NuPinConfig/V1.0/nutool_pincfg.c | 150 ++ .../board/NuPinConfig/V1.0/nutool_pincfg.h | 23 + .../board/NuPinConfig/nutool_pincfg.c | 556 ++++++ .../board/NuPinConfig/nutool_pincfg.h | 64 + .../board/NuPinConfig/nutool_pincfg.ncfg | 188 ++ bsp/nuvoton/numaker-m3334ki/board/SConscript | 19 + bsp/nuvoton/numaker-m3334ki/board/board.h | 37 + .../numaker-m3334ki/board/custom_loader.c | 80 + bsp/nuvoton/numaker-m3334ki/board/fal_cfg.h | 75 + .../numaker-m3334ki/board/nutool_clkcfg.h | 27 + .../numaker-m3334ki/board/nutool_modclkcfg.c | 1521 +++++++++++++++++ .../numaker-m3334ki/board/nutool_modclkcfg.h | 26 + .../numaker-m3334ki/linking_scripts/M3331.ld | 247 +++ .../numaker-m3334ki/linking_scripts/M3331.sct | 89 + bsp/nuvoton/numaker-m3334ki/rtconfig.h | 606 +++++++ bsp/nuvoton/numaker-m3334ki/rtconfig.py | 100 ++ bsp/nuvoton/numaker-m467hj/.config | 2 +- bsp/nuvoton/numaker-m467hj/config_lvgl | 1177 ------------- bsp/nuvoton/numaker-m467hj/rtconfig.h | 2 +- bsp/nuvoton/numaker-pfm-m487/.config | 2 +- bsp/nuvoton/numaker-pfm-m487/config_lvgl | 892 ---------- bsp/nuvoton/numaker-pfm-m487/rtconfig.h | 2 +- 132 files changed, 23612 insertions(+), 7846 deletions(-) delete mode 100644 bsp/nuvoton/docs/LVGL_Notes.md create mode 100644 bsp/nuvoton/libraries/m3331/README.md create mode 100644 bsp/nuvoton/libraries/m3331/SConscript create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/Kconfig create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/SConscript create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/SConscript create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_otg.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbd_hs_glue.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbh_ehci_custom_glue.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm_capture.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_common.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_crypto.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_eadc.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_ecap.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm_capture.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_softi2c.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_spii2s.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_sys.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_tpwm.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.h create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c create mode 100644 bsp/nuvoton/libraries/m3331/rtt_port/drv_wdt.c delete mode 100644 bsp/nuvoton/nk-980iot/config_lvgl delete mode 100644 bsp/nuvoton/numaker-iot-m467/config_lvgl delete mode 100644 bsp/nuvoton/numaker-iot-m487/config_lvgl delete mode 100644 bsp/nuvoton/numaker-m032ki/config_lvgl rename bsp/nuvoton/{numaker-m2354/config_lvgl => numaker-m3334ki/.config} (63%) create mode 100644 bsp/nuvoton/numaker-m3334ki/Kconfig create mode 100644 bsp/nuvoton/numaker-m3334ki/README.md create mode 100644 bsp/nuvoton/numaker-m3334ki/SConscript create mode 100644 bsp/nuvoton/numaker-m3334ki/SConstruct create mode 100644 bsp/nuvoton/numaker-m3334ki/Template.uvprojx create mode 100644 bsp/nuvoton/numaker-m3334ki/applications/SConscript create mode 100644 bsp/nuvoton/numaker-m3334ki/applications/lv_conf.h create mode 100644 bsp/nuvoton/numaker-m3334ki/applications/main.c create mode 100644 bsp/nuvoton/numaker-m3334ki/applications/mnt.c create mode 100644 bsp/nuvoton/numaker-m3334ki/applications/pm_test.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/Kconfig create mode 100644 bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUFUN create mode 100644 bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUTFT create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NTFUN_board_dev.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NUTFT_board_dev.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/M3334KIGAE(LQFP128).ncfg create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.h create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.h create mode 100644 bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.ncfg create mode 100644 bsp/nuvoton/numaker-m3334ki/board/SConscript create mode 100644 bsp/nuvoton/numaker-m3334ki/board/board.h create mode 100644 bsp/nuvoton/numaker-m3334ki/board/custom_loader.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/fal_cfg.h create mode 100644 bsp/nuvoton/numaker-m3334ki/board/nutool_clkcfg.h create mode 100644 bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.c create mode 100644 bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.h create mode 100644 bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.ld create mode 100644 bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.sct create mode 100644 bsp/nuvoton/numaker-m3334ki/rtconfig.h create mode 100644 bsp/nuvoton/numaker-m3334ki/rtconfig.py delete mode 100644 bsp/nuvoton/numaker-m467hj/config_lvgl delete mode 100644 bsp/nuvoton/numaker-pfm-m487/config_lvgl diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 9977e293f41..ebceb176337 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -291,7 +291,8 @@ "nuvoton/ma35-rtp", "nuvoton/nk-980iot", "nuvoton/numaker-iot-ma35d1", - "nuvoton/numaker-m2354" + "nuvoton/numaker-m2354", + "nuvoton/numaker-m3334ki" ] }, { diff --git a/bsp/nuvoton/docs/LVGL_Notes.md b/bsp/nuvoton/docs/LVGL_Notes.md deleted file mode 100644 index 1ccadd838ce..00000000000 --- a/bsp/nuvoton/docs/LVGL_Notes.md +++ /dev/null @@ -1,40 +0,0 @@ -# Bring up LVGL demo on Nuvoton platforms - -Current supported LVGL running environment on Nuvoton's boards shown in below table: - -| **Board Name** | **Default demo** | **Need Expansion** | **Used Configuration filename** | -| -------------- | ------------------------------- | ---------------- | ----------- | -| numaker-iot-m487 | Widgets | Nu-TFT v1.3 | config_lvgl | -| numaker-pfm-m487 | Widgets | Advance v4 | config_lvgl | -| nk-980iot | Music | Nu-TFT v1.3 | config_lvgl | -| numaker-m2354 | Music | Nu-TFT v1.3 | config_lvgl | -| nk-n9h30 | Music | No | .config | -| numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl | -| numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl | -| numaker-iot-m467 | Widgets | Nu-TFT v1.3 | config_lvgl | -| numaker-hmi-ma35d1 | Widgets | No | .config | - -## Download related packages - -To execute below commands in env command-line window to download related packages for building. - -```bash -# cd bsp/nuvoton/ -# menuconfig --config config_lvgl -# pkgs --update -# scons -``` - -## Firmware programming - -To program built rt-thread.bin into flash. You can refer steps in README.md in corresponding supported board folder or CN quick-start guide in rt-thread documents site. - -``` -/bsp/nuvoton//README.md -``` - - or - -``` -https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/quick-start/more -``` diff --git a/bsp/nuvoton/libraries/m3331/README.md b/bsp/nuvoton/libraries/m3331/README.md new file mode 100644 index 00000000000..52379ad8b53 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/README.md @@ -0,0 +1,36 @@ +# M3331 Series + +## Supported drivers + +| Peripheral | rt_device_class_type | Device name | +| ------ | ---- | :------: | +| CANFD | RT_Device_Class_CAN | ***canfd[0-1]*** | +| CRC | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| DAC | RT_Device_Class_Miscellaneous (DAC) | ***dac[0-1]*** | +| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc0*** | +| EBI | N/A | ***N/A*** | +| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** | +| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** | +| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** | +| EQEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***eqei[0-3]*** | +| RMC | FAL | ***N/A*** | +| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** | +| GPIO (Software I2C) | RT_Device_Class_I2CBUS | ***softi2c[0-1]*** | +| I2C | RT_Device_Class_I2CBUS | ***i2c[0-3]*** | +| PDMA | N/A | ***N/A*** | +| PWM | RT_Device_Class_Miscellaneous (PWM) | ***pwm[0-1]*** | +| QSPI | RT_Device_Class_SPIBUS | ***qspi0*** | +| RTC | RT_Device_Class_RTC | ***rtc*** | +| SPI | RT_Device_Class_SPIBUS | ***spi[0-3]*** | +| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-3]*** | +| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** | +| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** | +| TRNG | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** | +| UART | RT_Device_Class_Char | ***uart[0-7]*** | +| USBD | RT_Device_Class_USBDevice | ***usbd*** | +| USBH | RT_Device_Class_USBHost | ***usbh*** | +| USCI (I2C function) | RT_Device_Class_I2CBUS | ***ui2c[0-1]*** | +| USCI (SPI function) | RT_Device_Class_SPIBUS | ***uspi[0-1]*** | +| USCI (UART function) | RT_Device_Class_Char | ***uuart[0-1]*** | +| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** | diff --git a/bsp/nuvoton/libraries/m3331/SConscript b/bsp/nuvoton/libraries/m3331/SConscript new file mode 100644 index 00000000000..4c815c49b83 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/Kconfig b/bsp/nuvoton/libraries/m3331/rtt_port/Kconfig new file mode 100644 index 00000000000..5c8b2f77cb5 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/Kconfig @@ -0,0 +1,550 @@ +config SOC_FAMILY_NUMICRO + bool + +config SOC_SERIES_M3331 + bool + select ARCH_ARM + select ARCH_ARM_CORTEX_M + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + select SOC_FAMILY_NUMICRO + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select PKG_USING_NUVOTON_SERIES_DRIVER + default y + +menuconfig BSP_USING_BPWM + bool "Enable Basic PWM Generator and Capture Timer(BPWM)" + select RT_USING_PWM + + if BSP_USING_BPWM + config BSP_USING_BPWM_CAPTURE + bool + + config BSP_USING_BPWM0 + bool "Enable BPWM0" + select RT_USING_PWM + depends on !BSP_USING_BPWM0_CAPTURE + + config BSP_USING_BPWM0_CAPTURE + bool "Enable BPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + + config BSP_USING_BPWM1 + bool "Enable BPWM1" + select RT_USING_PWM + depends on !BSP_USING_BPWM1_CAPTURE + + config BSP_USING_BPWM1_CAPTURE + bool "Enable BPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + + config BSP_USING_BPWM2 + bool "Enable BPWM2" + select RT_USING_PWM + depends on !BSP_USING_BPWM2_CAPTURE + + config BSP_USING_BPWM2_CAPTURE + bool "Enable BPWM2_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + + config BSP_USING_BPWM3 + bool "Enable BPWM3" + select RT_USING_PWM + depends on !BSP_USING_BPWM3_CAPTURE + + config BSP_USING_BPWM3_CAPTURE + bool "Enable BPWM3_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + + config BSP_USING_BPWM4 + bool "Enable BPWM4" + select RT_USING_PWM + depends on !BSP_USING_BPWM4_CAPTURE + + config BSP_USING_BPWM4_CAPTURE + bool "Enable BPWM4_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + + config BSP_USING_BPWM5 + bool "Enable BPWM5" + select RT_USING_PWM + depends on !BSP_USING_BPWM5_CAPTURE + + config BSP_USING_BPWM5_CAPTURE + bool "Enable BPWM5_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE + endif + +menuconfig BSP_USING_CANFD + bool "Enable Controller Area Network Flexible Data-Rate Controller(CANFD)" + select RT_USING_CAN + + if BSP_USING_CANFD + config BSP_USING_CANFD0 + bool "Enable CANFD0" + + config BSP_USING_CANFD1 + bool "Enable CANFD1" + endif + +menuconfig BSP_USING_CLK + bool "Enable Clock Controller(CLK)" + select RT_USING_PM + select BSP_USING_TMR + default y + help + Choose this option if you need CLK function. + +menuconfig BSP_USING_CRC + bool "Enable Cyclic Redundancy Check Generator(CRC)" + + if BSP_USING_CRC + config BSP_USING_CRC0 + bool "Enable CRC0" + endif + +menuconfig BSP_USING_CRYPTO + bool "Enable Cryptographic Accelerator(CRYPTO)" + + if BSP_USING_CRYPTO + config BSP_USING_CRYPTO0 + bool "Enable CRYPTO0" + endif + +menuconfig BSP_USING_EADC + bool "Enable Enhanced Analog-to-Digital Converter(EADC)" + select RT_USING_ADC + + if BSP_USING_EADC + config BSP_USING_EADC0 + bool "Enable EADC0" + endif + +menuconfig BSP_USING_EBI + bool "Enable External Bus Interface(EBI)" + +menuconfig BSP_USING_EPWM + bool "Enable Enhanced PWM Generator and Capture Timer(EPWM)" + select RT_USING_PWM + + if BSP_USING_EPWM + config BSP_USING_EPWM_CAPTURE + bool + + config BSP_USING_EPWM0 + bool "Enable EPWM0" + select RT_USING_PWM + depends on !BSP_USING_EPWM0_CAPTURE + + config BSP_USING_EPWM0_CAPTURE + bool "Enable EPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + + config BSP_USING_EPWM1 + bool "Enable EPWM1" + select RT_USING_PWM + depends on !BSP_USING_EPWM1_CAPTURE + + config BSP_USING_EPWM1_CAPTURE + bool "Enable EPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + endif + +menuconfig BSP_USING_EQEI + bool "Enable Enhanced Quadrature Encoder Interface(EQEI)" + + if BSP_USING_EQEI + config BSP_USING_EQEI0 + bool "Enable EQEI0" + + config BSP_USING_EQEI1 + bool "Enable EQEI1" + + config BSP_USING_EQEI2 + bool "Enable EQEI2" + + config BSP_USING_EQEI3 + bool "Enable EQEI3" + endif + +menuconfig BSP_USING_FMC + bool "Enable Flash Memory Controller(FMC)" + select RT_USING_FAL + +menuconfig BSP_USING_GPIO + bool "Enable General Purpose I/O(GPIO)" + select RT_USING_PIN + default y + +menuconfig BSP_USING_I2C + bool "Enable Inter-Integrated Circuit(I2C)" + select RT_USING_I2C + select RT_USING_BITOPS + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + + config BSP_USING_I2C1 + bool "Enable I2C1" + + config BSP_USING_I2C2 + bool "Enable I2C2" + + config BSP_USING_I2C3 + bool "Enable I2C3" + endif + +menuconfig BSP_USING_LPADC + bool "Enable Low Power Analog-to-Digital Converter(LPADC)" + select RT_USING_ADC + + if BSP_USING_LPADC + config BSP_USING_LPADC0 + bool "Enable LPADC0" + endif + +menuconfig BSP_USING_LPTMR + bool "Enable Low Power Timer(LPTMR)" + + if BSP_USING_LPTMR + config BSP_USING_LPTMR0 + bool "Enable LPTMR0" + + config BSP_USING_LPTMR1 + bool "Enable LPTMR1" + endif + +menuconfig BSP_USING_PDMA + bool "Enable Peripheral Direct Memory Access(PDMA)" + + if BSP_USING_PDMA + config BSP_USING_PDMA0 + bool "Enable PDMA0" + + config NU_PDMA_SGTBL_POOL_SIZE + int "The size of PDMA scatter-gather tables pool." + default 16 + + config NU_PDMA_MEMFUN_ACTOR_MAX + int "The maximal actor number of PDMA memory function." + range 0 2 + default 2 + endif + +menuconfig BSP_USING_QSPI + bool "Enable Quad Serial Peripheral Interface(QSPI)" + select RT_USING_QSPI + + if BSP_USING_QSPI + config BSP_USING_QSPI0 + bool "Enable QSPI0" + + if BSP_USING_QSPI0 + config BSP_USING_QSPI0_PDMA + bool "Enable PDMA for QSPI0" + select BSP_USING_SPI_PDMA + endif + endif + +menuconfig BSP_USING_RTC + bool "Enable Real Time Clock(RTC)" + select RT_USING_RTC + + if BSP_USING_RTC + config BSP_USING_RTC_INTERNAL + bool "Enable Internal RTC" + endif + +menuconfig BSP_USING_SC + bool "Enable Smart Card Interface(SC)" + + if BSP_USING_SC + config BSP_USING_SC0 + bool "Enable SC0" + + config BSP_USING_SC1 + bool "Enable SC1" + + config BSP_USING_SC2 + bool "Enable SC2" + endif + +menuconfig BSP_USING_SPI + bool "Enable Serial Peripheral Interface(SPI)" + select RT_USING_SPI + + if BSP_USING_SPI + config BSP_USING_SPI_PDMA + bool + + config BSP_USING_SPII2S + bool + + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + select RT_USING_SPI + depends on !BSP_USING_SPII2S0 + + config BSP_USING_SPII2S0 + bool "Enable SPII2S0" + select RT_USING_AUDIO + select BSP_USING_SPII2S + + if BSP_USING_SPI0 + config BSP_USING_SPI0_PDMA + bool "Enable PDMA for SPI0" + select BSP_USING_SPI_PDMA + endif + + config BSP_USING_SPI1 + bool "Enable SPI1" + select RT_USING_SPI + depends on !BSP_USING_SPII2S1 + + config BSP_USING_SPII2S1 + bool "Enable SPII2S1" + select RT_USING_AUDIO + select BSP_USING_SPII2S + + if BSP_USING_SPI1 + config BSP_USING_SPI1_PDMA + bool "Enable PDMA for SPI1" + select BSP_USING_SPI_PDMA + endif + + config BSP_USING_SPI2 + bool "Enable SPI2" + select RT_USING_SPI + depends on !BSP_USING_SPII2S2 + + config BSP_USING_SPII2S2 + bool "Enable SPII2S2" + select RT_USING_AUDIO + select BSP_USING_SPII2S + + if BSP_USING_SPI2 + config BSP_USING_SPI2_PDMA + bool "Enable PDMA for SPI2" + select BSP_USING_SPI_PDMA + endif + endif + endif + +menuconfig BSP_USING_TMR + bool "Enable Timer(TMR)" + + if BSP_USING_TMR + config BSP_USING_TIMER + bool + + config BSP_USING_TPWM + bool + + config BSP_USING_TMR0 + bool "Enable TIMER0" + depends on BSP_USING_TMR + + if BSP_USING_TMR0 + config BSP_USING_TIMER0 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_HWTIMER + depends on !BSP_USING_TPWM0 + + config BSP_USING_TPWM0 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + endif + + config BSP_USING_TMR1 + bool "Enable TIMER1" + depends on BSP_USING_TMR + + if BSP_USING_TMR1 + config BSP_USING_TIMER1 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_HWTIMER + depends on !BSP_USING_TPWM1 + + config BSP_USING_TPWM1 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + endif + + config BSP_USING_TMR2 + bool "Enable TIMER2" + depends on BSP_USING_TMR + + if BSP_USING_TMR2 + config BSP_USING_TIMER2 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_HWTIMER + depends on !BSP_USING_TPWM2 + + config BSP_USING_TPWM2 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + endif + + config BSP_USING_TMR3 + bool "Enable TIMER3" + depends on BSP_USING_TMR + + if BSP_USING_TMR3 + config BSP_USING_TIMER3 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_HWTIMER + depends on !BSP_USING_TPWM3 + + config BSP_USING_TPWM3 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + endif + endif + +menuconfig BSP_USING_UART + bool "Enable Universal Asynchronous Receiver/Transmitter(UART)" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + + config BSP_USING_UART1 + bool "Enable UART1" + + config BSP_USING_UART2 + bool "Enable UART2" + + config BSP_USING_UART3 + bool "Enable UART3" + + config BSP_USING_UART4 + bool "Enable UART4" + + config BSP_USING_UART5 + bool "Enable UART5" + endif + +menuconfig BSP_USING_USCI + bool "Enable Universal Serial Control Interface(USCI)" + + if BSP_USING_USCI + config BSP_USING_UUART + bool + + config BSP_USING_USPI + bool + + config BSP_USING_USPI_PDMA + bool + default n + + config BSP_USING_UI2C + bool + + config BSP_USING_USCI0 + bool "Enable USCI0" + + config BSP_USING_USCI1 + bool "Enable USCI1" + + if BSP_USING_USCI0 + config BSP_USING_UUART0 + bool "UUART0" + select RT_USING_SERIAL + select BSP_USING_UUART + + config BSP_USING_UI2C0 + bool "UI2C0" + select RT_USING_I2C + select BSP_USING_UI2C + depends on !BSP_USING_UUART0 + + config BSP_USING_USPI0 + bool "USPI0" + select RT_USING_SPI + select BSP_USING_USPI + depends on !BSP_USING_UUART0 && !BSP_USING_UI2C0 + + config BSP_USING_UUART0_TX_DMA + bool "Enable UUART0 TX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UUART0_RX_DMA + bool "Enable UUART0 RX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_USPI0_PDMA + bool "Use PDMA for data transferring" + select BSP_USING_USPI_PDMA + depends on BSP_USING_USPI0 + endif + + if BSP_USING_USCI1 + config BSP_USING_UUART1 + bool "UUART1" + select RT_USING_SERIAL + select BSP_USING_UUART + + config BSP_USING_UI2C1 + bool "UI2C1" + select RT_USING_I2C + select BSP_USING_UI2C + depends on !BSP_USING_UUART1 + + config BSP_USING_USPI1 + bool "USPI1" + select RT_USING_SPI + select BSP_USING_USPI + depends on !BSP_USING_UUART1 && !BSP_USING_UI2C1 + + config BSP_USING_UUART1_TX_DMA + bool "Enable UUART1 TX DMA" + depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UUART1_RX_DMA + bool "Enable UUART1 RX DMA" + depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA + + config BSP_USING_USPI1_PDMA + bool "Use PDMA for data transferring" + select BSP_USING_USPI_PDMA + depends on BSP_USING_USPI1 + endif + endif + +config BSP_USING_HSUSBD + bool "Enable High-Speed USB Device Controller(HSUSBD)" + +config BSP_USING_HSUSBH + bool "Enable High-Speed USB Host Controller(HSUSBH)" + +config BSP_USING_HSOTG + bool "Enable High-Speed USB On-The-Go(HSOTG)" + select BSP_USING_HSUSBH + select BSP_USING_HSUSBD + +config BSP_USING_WDT + bool "Enable Watchdog Timer(WDT)" + select RT_USING_WDT diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/SConscript b/bsp/nuvoton/libraries/m3331/rtt_port/SConscript new file mode 100644 index 00000000000..8768cc4a132 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/SConscript @@ -0,0 +1,32 @@ +# RT-Thread building script for component + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +group = [] + +# USB driver constrain +if GetDepend('BOARD_USING_USBD') and ( GetDepend('BSP_USING_OTG') or GetDepend('BSP_USING_USBH') ): + print ('Sorry, wrong selection.') + print ('[Hint] You already select BOARD_USING_USBD. Please de-select BSP_USING_OTG and BSP_USING_USBH.') + sys.exit(1) +elif GetDepend('BOARD_USING_USBH') and ( GetDepend('BSP_USING_OTG') or GetDepend('BSP_USING_USBD') ): + print ('Sorry, wrong selection.') + print ('[Hint] You already select BOARD_USING_USBH. Please de-select BSP_USING_OTG and BSP_USING_USBD options.') + sys.exit(1) +else: + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +objs += group + +Return('objs') diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/SConscript b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/SConscript new file mode 100644 index 00000000000..cf721b49d8a --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('CherryUSB-port', src, depend = ['PKG_USING_CHERRYUSB'], CPPPATH = CPPPATH) + +Return('group') + diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c new file mode 100644 index 00000000000..c1957aaafa3 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c @@ -0,0 +1,77 @@ +/* Includes ------------------------------------------------------------------*/ +#include "rtthread.h" +#include "NuMicro.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.unknown" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#if defined(PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) +void cdc_acm_init(uint8_t busid, uint32_t reg_base); + +int rt_cdc_acm_init(void) +{ + cdc_acm_init(0, USBD_BASE); + return 0; +} + +INIT_APP_EXPORT(rt_cdc_acm_init); +MSH_CMD_EXPORT(rt_cdc_acm_init, start rt_cdc_acm_init); +#endif + +#if defined(PKG_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE) +void hid_mouse_init(uint8_t busid, uint32_t reg_base); +void hid_mouse_test(uint8_t busid); + +int rt_hid_mouse_init(void) +{ + hid_mouse_init(0, HSUSBD_BASE); + return 0; +} + +int rt_hid_mouse_test(void) +{ + hid_mouse_test(0); + return 0; +} + +MSH_CMD_EXPORT(rt_hid_mouse_init, start hid_mouse_test); +MSH_CMD_EXPORT(rt_hid_mouse_test, start hid_mouse_test); +#endif + +#if defined(PKG_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD) +void hid_keyboard_init(uint8_t busid, uint32_t reg_base); +void hid_keyboard_test(uint8_t busid); + +int rt_hid_keyboard_test(void) +{ + hid_keyboard_init(0, HSUSBD_BASE); + hid_keyboard_test(0); + return 0; +} + +MSH_CMD_EXPORT(rt_hid_keyboard_test, start hid_keyboard_test); +#endif + +#if defined(PKG_CHERRYUSB_DEVICE_TEMPLATE_MSC) +void msc_ram_init(uint8_t busid, uint32_t reg_base); + +int rt_msc_ram_test(void) +{ + msc_ram_init(0, HSUSBD_BASE); + return 0; +} + +INIT_APP_EXPORT(rt_msc_ram_test); +MSH_CMD_EXPORT(rt_msc_ram_test, start msc_ram_init); +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h new file mode 100644 index 00000000000..c1dd12aae19 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h @@ -0,0 +1,264 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __USB_CONFIG_H__ +#define __USB_CONFIG_H__ + +#include "rtthread.h" +#include "NuMicro.h" + + + +#define CONFIG_USB_PRINTF rt_kprintf + +#define usb_malloc(size) rt_malloc(size) +#define usb_free(ptr) rt_free(ptr) + + +//#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG +#if !defined(CONFIG_USB_DBG_LEVEL) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#if !defined(CONFIG_USB_ALIGN_SIZE) + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + + + +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip + +/* Ep0 max transfer buffer, specially for receiving data from ep0 out */ +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256 + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#if !defined(CONFIG_USBDEV_MSC_MAX_LUN) + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#define CONFIG_USBDEV_TX_THREAD +#define CONFIG_USBDEV_RX_THREAD + +#if defined(CONFIG_USBDEV_TX_THREAD) + #if !defined(CONFIG_USBDEV_TX_PRIO) + #define CONFIG_USBDEV_TX_PRIO 4 + #endif + #if !defined(CONFIG_USBDEV_TX_STACKSIZE) + #define CONFIG_USBDEV_TX_STACKSIZE 2048 + #endif +#endif + +#if defined(CONFIG_USBDEV_RX_THREAD) + #if !defined(CONFIG_USBDEV_RX_PRIO) + #define CONFIG_USBDEV_RX_PRIO 4 + #endif + #if !defined(CONFIG_USBDEV_RX_STACKSIZE) + #define CONFIG_USBDEV_RX_STACKSIZE 2048 + #endif +#endif + +#if !defined(CONFIG_USBDEV_MSC_MAX_LUN) +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#if !defined(CONFIG_USBDEV_MSC_MAX_BUFSIZE) +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#if !defined(CONFIG_USBDEV_MSC_MANUFACTURER_STRING) +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif +#if !defined(CONFIG_USBDEV_MSC_PRODUCT_STRING) +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif +#if !defined(CONFIG_USBDEV_MSC_VERSION_STRING) +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +#define CONFIG_USBDEV_MSC_THREAD + +#if !defined(CONFIG_USBDEV_MSC_PRIO) +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif +#if !defined(CONFIG_USBDEV_MSC_STACKSIZE) +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#if !defined(CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE) +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#if !defined(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE) +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#if !defined(CONFIG_USBDEV_RNDIS_VENDOR_ID) +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#if !defined(CONFIG_USBDEV_RNDIS_VENDOR_DESC) +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + + + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 4 +#define CONFIG_USBHOST_MAX_EHPORTS 8 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 +#define CONFIG_USBHOST_MAX_RNDIS_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#if !defined(CONFIG_USBHOST_PSC_PRIO) +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#if !defined(CONFIG_USBHOST_PSC_STACKSIZE) +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#if !defined(CONFIG_USBHOST_MSOS_VENDOR_CODE) +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#if !defined(CONFIG_USBHOST_REQUEST_BUFFER_LEN) +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#if !defined(CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT) +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#if !defined(CONFIG_USBHOST_MSC_TIMEOUT) +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE) +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#if !defined(CONFIG_USBHOST_BLUETOOTH_TX_SIZE) +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#if !defined(CONFIG_USBHOST_BLUETOOTH_RX_SIZE) +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + + +#if !defined(CONFIG_USB_HS) +#define CONFIG_USB_HS +#endif + +#if !defined(CONFIG_USBDEV_EP_NUM) + #define CONFIG_USBDEV_EP_NUM 8 +#endif +#if !defined(CONFIG_USBHOST_MAX_BUS) +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#if !defined(CONFIG_USBHOST_PIPE_NUM) +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ +#define CONFIG_USB_EHCI_HCCR_OFFSET (0) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +#define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +//#define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +#if !defined(usb_phyaddr2ramaddr) +#define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#if !defined(usb_ramaddr2phyaddr) +#define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c new file mode 100644 index 00000000000..6de0b43a7e4 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c @@ -0,0 +1,987 @@ +/* Includes ------------------------------------------------------------------*/ +#include +#include "NuMicro.h" +#include "usbd_core.h" +#include "nu_bitutil.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.usb.hs.dc" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define EPADR_SW2HW(address) ((address == 0) ? (CEP) : (USB_EP_GET_IDX(address) - 1)) +#define EPADR_HW2SW(address) (address + 1) +#define CEP_BUF_ADR 0 +#define CEP_BUF_SIZE 64 + +/* Endpoint state */ +struct usb_dc_ep_state +{ + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t ep_addr; /* Endpoint address */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; + uint32_t mps_xfer_len; +}; + +/* Driver state */ +struct usb_dc_config_priv +{ + struct usb_setup_packet setup_pkt; + uint32_t epUsedBufSize; + struct usb_dc_ep_state ep[HSUSBD_MAX_EP]; /*!< IN/OUT endpoint parameters*/ +} ; + +static volatile struct usb_dc_config_priv s_sUDC; + +static const char *szGLOBAL[] = +{ + "USBIF", + "CEPIF" +}; + +static const char *szUSBIF[] = +{ + "SOFIF", + "RSTIF", + "RESUMEIF", + "SUSPENDIF", + "HISPDIF", + "DMADONEIF", + "PHYCLKVLDIF", + "BIT7-RESERVED", + "VBUSDETIF", + "BIT9-RESERVED" +}; + +static const char *szCEPIF[] = +{ + "SETUPTKIF", + "SETUPPKIF", + "OUTTKIF", + "INTKIF", + "PINGIF", + "TXPKIF", + "RXPKIF", + "NAKIF", + "STALLIF", + "ERRIF", + "STSDONEIF", + "BUFFULLIF", + "BUFEMPTYIF", + "BIT9-RESERVED" +}; + +__STATIC_INLINE uint32_t HSUSBD_GetEpBufAddr(uint32_t u32HWEP) +{ + if (u32HWEP == CEP) + { + return HSUSBD->CEPBUFSTART; + } + + return HSUSBD->EP[u32HWEP].EPBUFSTART; +} + +__STATIC_INLINE uint32_t HSUSBD_GetEpBufAddrEnd(uint32_t u32HWEP) +{ + if (u32HWEP == CEP) + { + return HSUSBD->CEPBUFEND; + } + + return HSUSBD->EP[u32HWEP].EPBUFEND; +} + +__STATIC_INLINE uint32_t HSUSBD_GetEpDir(uint32_t u32HWEP) +{ + return HSUSBD->EP[u32HWEP].EPCFG & HSUSBD_EPCFG_EPDIR_Msk; +} + +static void HSUSBD_DumpEpBufAddr(void) +{ + int i; + + USB_LOG_INFO("CEP@[%08X-%08X]\n", HSUSBD_GetEpBufAddr(CEP), HSUSBD_GetEpBufAddrEnd(CEP)); + for (i = 0; i < HSUSBD_MAX_EP; i++) + { + USB_LOG_INFO("EP%c@[%08X-%08X]\n", 'A' + i, HSUSBD_GetEpBufAddr(EPA + i), HSUSBD_GetEpBufAddrEnd(EPA + i)); + } +} + +static uint32_t HSUSBD_NewEpBuf(int n) +{ +#define DEF_HSUSBD_RAM_SIZE HSUSBD_RAM_SIZE +#define DEF_HSUSBD_MAX_EP_BUF_SIZE HSUSBD_MAX_EP_RAM_SIZE + + uint32_t u32Addr; + + if (((s_sUDC.epUsedBufSize + n) > DEF_HSUSBD_RAM_SIZE) || (n > DEF_HSUSBD_MAX_EP_BUF_SIZE)) + return 0; + + u32Addr = s_sUDC.epUsedBufSize; + s_sUDC.epUsedBufSize += n; + + return u32Addr; +} + +static const char *HSUSBD_PrintEpType(uint32_t u32HWType) +{ + switch (u32HWType) + { + case HSUSBD_EP_CFG_TYPE_BULK: + return "BULK"; + case HSUSBD_EP_CFG_TYPE_INT: + return "INT"; + case HSUSBD_EP_CFG_TYPE_ISO: + return "ISO"; + default: + return "UNK"; + } +} + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usbd_set_remote_wakeup(uint8_t busid) +{ + return -1; +} + +int usb_dc_init(uint8_t busid) +{ + int i; + int32_t i32TimeOutCnt = HSUSBD_TIMEOUT / 1000; + + memset((void *)&s_sUDC, 0, sizeof(s_sUDC)); + + usb_dc_low_level_init(); + + /*****************************************************/ + /* Initial USB engine */ + HSUSBD_ENABLE_PHY(); + /* wait PHY clock ready */ + while (!(HSUSBD->PHYCTL & HSUSBD_PHYCTL_PHYCLKSTB_Msk)) + { + if (i32TimeOutCnt-- < 0) + { + break; + } + } + + HSUSBD->OPER &= ~HSUSBD_OPER_HISPDEN_Msk; /* full-speed */ + + /* Force SE0 */ + HSUSBD_SET_SE0(); + + /* Configure USB controller */ + /* Enable USB BUS, CEP global interrupt */ + HSUSBD_ENABLE_USB_INT(HSUSBD_GINTEN_USBIEN_Msk + | HSUSBD_GINTEN_CEPIEN_Msk); + + /* Enable BUS interrupt */ + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RESUMEIEN_Msk + | HSUSBD_BUSINTEN_RSTIEN_Msk + | HSUSBD_BUSINTEN_VBUSDETIEN_Msk); + + /* USB start */ + HSUSBD_CLR_SE0(); + + /* Enable interrupt */ + NVIC_EnableIRQ(HSUSBD_IRQn); + + HSUSBD_ENABLE_USB(); + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + HSUSBD_SET_ADDR(0); + + /* Force SE0 */ + HSUSBD_SET_SE0(); + + HSUSBD_DISABLE_USB(); + + /* Enable interrupt */ + NVIC_DisableIRQ(HSUSBD_IRQn); + + usb_dc_low_level_deinit(); + + return 0; +} + +static uint8_t g_address = 0; +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + USB_LOG_DBG("[%s]%d\n", __func__, addr); + g_address = addr; + //HSUSBD_SET_ADDR(addr); + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + if (HSUSBD->OPER & HSUSBD_OPER_CURSPD_Msk) + { + USB_LOG_DBG("[%s] HIGH\r\n", __func__); + return USB_SPEED_HIGH; + } + + USB_LOG_DBG("[%s] FULL\r\n", __func__); + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep->bEndpointAddress); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + uint32_t u32MPS = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + + if (SWEP) // IN/OUT EPs + { + uint32_t u32EPType = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + uint32_t u32HWEPType; + + switch (u32EPType) + { + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + u32HWEPType = HSUSBD_EP_CFG_TYPE_ISO; + break; + case USB_ENDPOINT_TYPE_BULK: + u32HWEPType = HSUSBD_EP_CFG_TYPE_BULK; + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + u32HWEPType = HSUSBD_EP_CFG_TYPE_INT; + break; + default: + return -1; + } + + s_sUDC.ep[HWEP].ep_addr = ep->bEndpointAddress; + s_sUDC.ep[HWEP].ep_mps = u32MPS; + s_sUDC.ep[HWEP].ep_type = u32EPType; + s_sUDC.ep[HWEP].ep_enable = true; + + HSUSBD_SetEpBufAddr(HWEP, HSUSBD_NewEpBuf(u32MPS), u32MPS); + HSUSBD_SET_MAX_PAYLOAD(HWEP, u32MPS); + + if (USB_EP_DIR_IS_IN(ep->bEndpointAddress)) // IN + { + HSUSBD_ENABLE_EP_INT(HWEP, HSUSBD_EPINTEN_TXPKIEN_Msk); + HSUSBD_ConfigEp(HWEP, SWEP, u32HWEPType, HSUSBD_EP_CFG_DIR_IN); + } + else //OUT + { + HSUSBD_ENABLE_EP_INT(HWEP, HSUSBD_EPINTEN_RXPKIEN_Msk | HSUSBD_EPINTEN_SHORTRXIEN_Msk | HSUSBD_EPINTEN_BUFFULLIEN_Msk); + HSUSBD_ConfigEp(HWEP, SWEP, u32HWEPType, HSUSBD_EP_CFG_DIR_OUT); + } + + HSUSBD->EP[HWEP].EPRSPCTL = (HSUSBD->EP[HWEP].EPRSPCTL & HSUSBD_EP_RSPCTL_MODE_MASK) | HSUSBD_EPRSPCTL_FLUSH_Msk; + + HSUSBD->GINTEN |= (0x1UL << (HSUSBD_GINTEN_EPAIEN_Pos + (HWEP - EPA))); + + USB_LOG_INFO("[%s]EpAddr:%02x-> SWEP:%d -> EP%c_Buf@[%08x - %08X], HWEPType:%s\n", + __func__, + s_sUDC.ep[HWEP].ep_addr, + SWEP, + 'A' + HWEP, + HSUSBD_GetEpBufAddr(HWEP), HSUSBD_GetEpBufAddrEnd(HWEP), + HSUSBD_PrintEpType(u32HWEPType)); + + //HSUSBD_DumpEpBufAddr(); + + } + else if (ep->bEndpointAddress == USB_CONTROL_IN_EP0) + { + USB_LOG_INFO("[%s]EP:%02x, SWEP:%d, CEP, MaxPktSize: %d\n", __func__, ep->bEndpointAddress, SWEP, u32MPS); + + /* Control endpoint */ + HSUSBD_SetEpBufAddr(CEP, HSUSBD_NewEpBuf(CEP_BUF_SIZE), CEP_BUF_SIZE); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk + | HSUSBD_CEPINTEN_STSDONEIEN_Msk + | HSUSBD_CEPINTEN_TXPKIEN_Msk + | HSUSBD_CEPINTEN_RXPKIEN_Msk); + HSUSBD_SET_ADDR(0); + + /* Clear all CEP-BUFEMPTYIF, BUFFULLIF, STSDONEIF, ERRIF, STALLIF, NAKIF, RXPKIF, TXPKIF, + PINGIF, INTKIF, OUTTKIF flags, unless SETUPPKIF and SETUPTKIF flags. */ + HSUSBD_CLR_CEP_INT_FLAG(0x1ffc); + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + if (USB_EP_GET_IDX(ep)) // IN/OUT EPs + { + USB_LOG_DBG("[%s]EP:%02x-> SWEP:%d -> EP%c\n", __func__, ep, SWEP, 'A' + HWEP); + HSUSBD->EP[HWEP].EPCFG &= ~HSUSBD_EP_CFG_VALID; + } + else //CEP + { + USB_LOG_DBG("[%s]EP:%02x-> SWEP:%d -> CEP\n", __func__, ep, SWEP); + } + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + HSUSBD_SetEpStall(HWEP); + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + HSUSBD_ClearEpStall(HWEP); + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + *stalled = HSUSBD_GetEpStall(HWEP) > 0 ? 1 : 0; + + return 0; +} + +static uint32_t usbd_ep_xfer(const uint8_t ep_addr, uint8_t *buffer, uint32_t size) +{ + uint32_t i, cnt; + uint32_t *_buf_word; + uint8_t *_buf_byte; + uint8_t SWEP = USB_EP_GET_IDX(ep_addr); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + _buf_word = (uint32_t *)buffer; + cnt = size >> 2; + _buf_byte = (uint8_t *)((uint8_t *)buffer + (cnt * 4)); + + if (SWEP) //EPs + { + if (USB_EP_DIR_IS_IN(ep_addr)) //IN + { + for (i = 0; i < cnt; i++) + { + HSUSBD->EP[HWEP].EPDAT = _buf_word[i]; + } + for (i = 0; i < (size & 0x3); i++) + { + HSUSBD->EP[HWEP].EPDAT_BYTE = _buf_byte[i]; + } + + HSUSBD->EP[HWEP].EPRSPCTL = HSUSBD_EP_RSPCTL_SHORTTXEN; // packet end + HSUSBD->EP[HWEP].EPTXCNT = size; + } + else //OUT + { + for (i = 0; i < cnt; i++) + { + _buf_word[i] = HSUSBD->EP[HWEP].EPDAT; + } + for (i = 0; i < (size & 0x3); i++) + { + _buf_byte[i] = HSUSBD->EP[HWEP].EPDAT_BYTE; + } + } + } + else //CEP + { + if (USB_EP_DIR_IS_IN(ep_addr)) //IN + { + for (i = 0; i < cnt; i++) + { + HSUSBD->CEPDAT = _buf_word[i]; + } + for (i = 0; i < (size & 0x3); i++) + { + HSUSBD->CEPDAT_BYTE = _buf_byte[i]; + } + } + else //OUT + { + for (i = 0; i < cnt; i++) + { + _buf_word[i] = HSUSBD->CEPDAT; + } + for (i = 0; i < (size & 0x3); i++) + { + _buf_byte[i] = HSUSBD->CEPDAT_BYTE; + } + } + } + + return size; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + USB_LOG_DBG("[W] ep:%02x, %p, len: %d\n", ep, data, data_len); + + if (SWEP) // IN EPs + { + if (!data && data_len) + { + return -1; + } + + if (!s_sUDC.ep[HWEP].ep_enable) + { + return -2; + } + + s_sUDC.ep[HWEP].xfer_buf = (uint8_t *)data; + s_sUDC.ep[HWEP].xfer_len = data_len; + s_sUDC.ep[HWEP].actual_xfer_len = 0; + + if (data_len > s_sUDC.ep[HWEP].ep_mps) + { + data_len = s_sUDC.ep[HWEP].ep_mps; + } + + usbd_ep_xfer(ep, s_sUDC.ep[HWEP].xfer_buf, data_len); + } + else //CEP + { + if (data) + { + if (data_len > 0) + { + usbd_ep_xfer(ep, (uint8_t *)data, data_len); + HSUSBD_START_CEP_IN(data_len); + } + else + { + /* Zero length */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_ZEROLEN); + } + } + else if (data_len == 0) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + } + } + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t SWEP = USB_EP_GET_IDX(ep); + uint8_t HWEP = EPADR_SW2HW(SWEP); + + USB_LOG_DBG("[R] ep:%02x, %p, len: %d\n", ep, data, data_len); + + if (SWEP) // OUT EPs + { + if (!s_sUDC.ep[HWEP].ep_enable) + { + return -2; + } + + s_sUDC.ep[HWEP].xfer_buf = (uint8_t *)data; + s_sUDC.ep[HWEP].xfer_len = data_len; + s_sUDC.ep[HWEP].actual_xfer_len = 0; + + if (s_sUDC.ep[HWEP].xfer_len < s_sUDC.ep[HWEP].ep_mps) + { + s_sUDC.ep[HWEP].mps_xfer_len = s_sUDC.ep[HWEP].xfer_len; + } + else + { + s_sUDC.ep[HWEP].mps_xfer_len = s_sUDC.ep[HWEP].ep_mps; + } + } + else //CEP + { + if (data_len) + { + usbd_ep_xfer(ep, data, data_len); + } + else + { + } + } + + return 0; +} + +static void dump_isr_event(uint32_t idx, const char *Str[], uint32_t u32PoolSize) +{ + if (idx < u32PoolSize) + { + if ((szGLOBAL == Str) && (idx >= 2)) + { + USB_LOG_DBG("[%d]GLOBAL-EP%cIF\r\n", rt_tick_get(), 'A' + idx - 2); + } + else + { + USB_LOG_DBG("[%d]%s-%s(#%d)\r\n", + rt_tick_get(), + (Str == szGLOBAL) ? "GLOBAL" : \ + ((Str == szUSBIF) ? " USBIF" : " CEPIF"), \ + Str[idx], + idx); + } + } +} + +typedef void (*usbif_isr_func)(uint8_t busid); + +static void BUS_ISR_SOFIF(uint8_t busid) +{ + /* This bit indicates when a start-of-frame packet has been received */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SOFIF_Msk); +} + +static void BUS_ISR_RSTIF(uint8_t busid) +{ + /* When set, this bit indicates that either the USB root port reset is end. */ + + /* Reset DMA engine */ + HSUSBD_ResetDMA(); + s_sUDC.epUsedBufSize = 0; + /* Set DMA engine, Flush All EPs Buffer. */ + //int i; + //for (i = 0; i < HSUSBD_MAX_EP; i++) + //{ + // HSUSBD->EP[i].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; + //} + usbd_event_reset_handler(busid); + HSUSBD_ENABLE_USB(); + + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RSTIF_Msk); +} + +static void BUS_ISR_RESUMEIF(uint8_t busid) +{ + /* Resume Interrupt */ + /* When set, this bit indicates that a device resume has occurred. */ + + /* Enable USBIF - RST, SUSPEND interrupts. */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RESUMEIF_Msk); + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk); + + /* Call CherryUSB resume callback. */ + usbd_event_resume_handler(busid); +} + +static void BUS_ISR_SUSPENDIF(uint8_t busid) +{ + /* Suspend Request Interrupt */ + /* This bit is set as default and it has to be cleared by writing ????before the USB reset. + This bit is also set when a USB Suspend request is detected from the host. */ + + /* Enable USBIF - RST, RESUME, SUSPEND interrupts. */ + HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | + HSUSBD_BUSINTEN_RESUMEIEN_Msk); + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SUSPENDIF_Msk); + + /* Call CherryUSB suspend callback. */ + usbd_event_suspend_handler(busid); +} + +static void BUS_ISR_HISPDIF(uint8_t busid) +{ + /* High-speed Settle Interrupt */ + /* + 0 = No valid high-speed reset protocol is detected. + 1 = Valid high-speed reset protocol is over and the device has settled in high-speed. + */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_HISPDIF_Msk); +} + +static void BUS_ISR_DMADONEIF(uint8_t busid) +{ + /* DMA Completion Interrupt */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_DMADONEIF_Msk); +} + +static void BUS_ISR_PHYCLKVLDIF(uint8_t busid) +{ + /* Usable Clock Interrupt */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk); +} + +static void BUS_ISR_VBUSDETIF(uint8_t busid) +{ + /* VBUS Detection Interrupt */ + /* 0 = No VBUS is plug-in. + 1 = VBUS is plug-in. */ + HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_VBUSDETIF_Msk); + + /* Check cable connect status. */ + if (HSUSBD_IS_ATTACHED()) + { + /* USB Plug In */ + USB_LOG_INFO("USB Plug In!!\r\n"); + + HSUSBD->OPER = HSUSBD_OPER_HISPDEN_Msk; /* high-speed */ + HSUSBD_CLR_SE0(); + HSUSBD->OPER |= HSUSBD_OPER_HISHSEN_Msk; /* Start high speed handshake*/ + + usbd_event_connect_handler(busid); + } + else + { + /* USB Un-plug */ + USB_LOG_INFO("USB Un-plug!!\r\n"); + + HSUSBD_DISABLE_USB(); + usbd_event_disconnect_handler(busid); + } +} + +static void CEP_ISR_SETUPTKIF(uint8_t busid) +{ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPTKIF_Msk); + + /* + Setup Token Interrupt + 0 = Not a Setup token is received. + 1 = A Setup token is received. Writing 1 clears this status bit + */ +} + +static void CEP_ISR_SETUPPKIF(uint8_t busid) +{ + /* + This bit must be cleared (by writing 1) before the next setup packet can be received. If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. + 0 = Not a Setup packet has been received from the host. + 1 = A Setup packet has been received from the host. + */ + s_sUDC.setup_pkt.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0); + s_sUDC.setup_pkt.bRequest = (uint8_t)(HSUSBD->SETUP1_0 >> 8); + s_sUDC.setup_pkt.wValue = (uint16_t)(HSUSBD->SETUP3_2); + s_sUDC.setup_pkt.wIndex = (uint16_t)(HSUSBD->SETUP5_4); + s_sUDC.setup_pkt.wLength = (uint16_t)(HSUSBD->SETUP7_6); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk); + + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&s_sUDC.setup_pkt); +} + +static void CEP_ISR_OUTTKIF(uint8_t busid) +{ + /* + 0 = The control-endpoint does not receive an OUT token from the host. + 1 = The control-endpoint receives an OUT token from the host. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_OUTTKIF_Msk); +} + +static void CEP_ISR_INTKIF(uint8_t busid) +{ + /* + 0 = The control-endpoint does not receive an IN token from the host. + 1 = The control-endpoint receives an IN token from the host. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); +} + +static void CEP_ISR_PINGIF(uint8_t busid) +{ + /* + 0 = The control-endpoint does not receive a ping token from the host. + 1 = The control-endpoint receives a ping token from the host. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_PINGIF_Msk); +} + +static void CEP_ISR_TXPKIF(uint8_t busid) +{ + /* + Data Packet Transmitted Interrupt + 0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + 1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + + usbd_event_ep_in_complete_handler(busid, USB_CONTROL_IN_EP0, HSUSBD->CEPTXCNT); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk); +} + +static void CEP_ISR_RXPKIF(uint8_t busid) +{ + /* + Data Packet Received Interrupt + 0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + 1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + */ + //HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + + usbd_event_ep_out_complete_handler(busid, USB_CONTROL_OUT_EP0, HSUSBD->CEPRXCNT); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_RXPKIF_Msk); +} + +static void CEP_ISR_NAKIF(uint8_t busid) +{ + /* + NAK Sent Interrupt + 0 = Not a NAK-token is sent in response to an IN/OUT token. + 1 = A NAK-token is sent in response to an IN/OUT token. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_NAKIF_Msk); +} + +static void CEP_ISR_STALLIF(uint8_t busid) +{ + /* + Stall Sent Interrupt + 0 = Not a stall-token is sent in response to an IN/OUT token. + 1 = A stall-token is sent in response to an IN/OUT token. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STALLIF_Msk); +} + +static void CEP_ISR_ERRIF(uint8_t busid) +{ + /* + USB Error Interrupt + 0 = No error had occurred during the transaction. + 1 = An error had occurred during the transaction. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_ERRIF_Msk); +} + +static void CEP_ISR_STSDONEIF(uint8_t busid) +{ + if ((g_address > 0) && (HSUSBD_GET_ADDR() == 0)) + { + HSUSBD_SET_ADDR(g_address); + } + + /* + Status Completion Interrupt + 0 = Not a USB transaction has completed successfully. + 1 = The status stage of a USB transaction has completed successfully. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); +} + +static void CEP_ISR_BUFFULLIF(uint8_t busid) +{ + /* + Buffer Full Interrupt + 0 = The control-endpoint buffer is not full. + 1 = The control-endpoint buffer is full. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFFULLIF_Msk); +} + +static void CEP_ISR_BUFEMPTYIF(uint8_t busid) +{ + /* + Buffer Empty Interrupt + 0 = The control-endpoint buffer is not empty. + 1 = The control-endpoint buffer is empty. + */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk); +} + +static void process_busif(uint8_t busid) +{ + static const usbif_isr_func isr_cb[] = + { + BUS_ISR_SOFIF, + BUS_ISR_RSTIF, + BUS_ISR_RESUMEIF, + BUS_ISR_SUSPENDIF, + BUS_ISR_HISPDIF, + BUS_ISR_DMADONEIF, + BUS_ISR_PHYCLKVLDIF, + NULL, + BUS_ISR_VBUSDETIF + }; + __IO rt_uint32_t IrqSt = HSUSBD->BUSINTSTS & HSUSBD->BUSINTEN; + int i; + + // Find first set. + while ((i = nu_ctz(IrqSt)) < (sizeof(isr_cb) / sizeof(usbif_isr_func))) + { + uint32_t u32BitMask = (1 << i); + + dump_isr_event(i, szUSBIF, sizeof(szUSBIF) / sizeof(char *)); + + if (isr_cb[i] != NULL) + isr_cb[i](busid); + + IrqSt &= ~u32BitMask; + } +} + +static void process_cepif(uint8_t busid) +{ + static const usbif_isr_func isr_cb[] = + { + CEP_ISR_SETUPTKIF, + CEP_ISR_SETUPPKIF, + CEP_ISR_OUTTKIF, + CEP_ISR_INTKIF, + CEP_ISR_PINGIF, + CEP_ISR_TXPKIF, + CEP_ISR_RXPKIF, + CEP_ISR_NAKIF, + CEP_ISR_STALLIF, + CEP_ISR_ERRIF, + CEP_ISR_STSDONEIF, + CEP_ISR_BUFFULLIF, + CEP_ISR_BUFEMPTYIF + }; + __IO rt_uint32_t IrqSt = HSUSBD->CEPINTSTS & HSUSBD->CEPINTEN; + int i; + + // Find first set. + while ((i = nu_ctz(IrqSt)) < (sizeof(isr_cb) / sizeof(usbif_isr_func))) + { + uint32_t u32BitMask = (1 << i); + + dump_isr_event(i, szCEPIF, sizeof(szCEPIF) / sizeof(char *)); + + if (isr_cb[i] != NULL) + isr_cb[i](busid); + + IrqSt &= ~u32BitMask; + } +} + +static void process_epxif(uint8_t busid) +{ + /* Service EP events */ + uint32_t HWEP, u32EpIntSts; + + u32EpIntSts = ((HSUSBD->GINTSTS & HSUSBD->GINTEN) >> HSUSBD_GINTSTS_EPAIF_Pos) & ((1 << HSUSBD_MAX_EP) - 1); + while ((HWEP = nu_ctz(u32EpIntSts)) < HSUSBD_MAX_EP) + { + uint32_t u32BitMask = (1 << HWEP); + uint8_t SWEP = EPADR_HW2SW(HWEP); + + uint32_t IrqSt = HSUSBD->EP[HWEP].EPINTSTS & HSUSBD->EP[HWEP].EPINTEN; + HSUSBD_CLR_EP_INT_FLAG(HWEP, IrqSt); + + if (HSUSBD_GetEpDir(HWEP) == HSUSBD_EP_CFG_DIR_IN) // IN ep + { + if (s_sUDC.ep[HWEP].xfer_len > s_sUDC.ep[HWEP].ep_mps) + { + s_sUDC.ep[HWEP].xfer_buf += s_sUDC.ep[HWEP].ep_mps; + s_sUDC.ep[HWEP].xfer_len -= s_sUDC.ep[HWEP].ep_mps; + s_sUDC.ep[HWEP].actual_xfer_len += s_sUDC.ep[HWEP].ep_mps; + + uint16_t min_len = MIN(s_sUDC.ep[HWEP].xfer_len, s_sUDC.ep[HWEP].ep_mps); + + usbd_ep_xfer(s_sUDC.ep[HWEP].ep_addr, s_sUDC.ep[HWEP].xfer_buf, min_len); + + } + else + { + s_sUDC.ep[HWEP].actual_xfer_len += s_sUDC.ep[HWEP].xfer_len; + s_sUDC.ep[HWEP].xfer_len = 0; + + usbd_event_ep_in_complete_handler(busid, SWEP | 0x80, s_sUDC.ep[HWEP].actual_xfer_len); + } + } + else // OUT + { + uint32_t u32Len = HSUSBD->EP[HWEP].EPDATCNT & 0xFFFFUL; + + usbd_ep_xfer(s_sUDC.ep[HWEP].ep_addr, s_sUDC.ep[HWEP].xfer_buf, u32Len); + + s_sUDC.ep[HWEP].xfer_buf += u32Len; + s_sUDC.ep[HWEP].xfer_len -= u32Len; + s_sUDC.ep[HWEP].actual_xfer_len += u32Len; + + if ((u32Len < s_sUDC.ep[HWEP].ep_mps) || + (s_sUDC.ep[HWEP].xfer_len == 0)) + { + usbd_event_ep_out_complete_handler(busid, SWEP, s_sUDC.ep[HWEP].actual_xfer_len); + } + else + { + if (s_sUDC.ep[HWEP].xfer_len < s_sUDC.ep[HWEP].ep_mps) + { + s_sUDC.ep[HWEP].mps_xfer_len = s_sUDC.ep[HWEP].xfer_len; + } + else + { + s_sUDC.ep[HWEP].mps_xfer_len = s_sUDC.ep[HWEP].ep_mps; + } + } + } + + u32EpIntSts &= ~u32BitMask; + } + +} + +void CherryUSB_USBD_IRQHandler(uint8_t busid) +{ + __IO rt_uint32_t IrqSt = HSUSBD->GINTSTS & HSUSBD->GINTEN; + if (IrqSt) + { + int i; + + // Find first set. + while ((i = nu_ctz(IrqSt)) != 32) + { + uint32_t u32BitMask = (1 << i); + + dump_isr_event(i, szGLOBAL, 2 + HSUSBD_MAX_EP); + + switch (u32BitMask) + { + case HSUSBD_GINTSTS_USBIF_Msk: + process_busif(busid); + break; + + case HSUSBD_GINTSTS_CEPIF_Msk: + process_cepif(busid); + break; + + default: /* EP interrups */ + process_epxif(busid); + break; + } + + IrqSt &= ~u32BitMask; + } + } +} diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_otg.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_otg.c new file mode 100644 index 00000000000..c731af9a33a --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_otg.c @@ -0,0 +1,107 @@ +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#include "rtdevice.h" +#include "NuMicro.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.usb.hs.otg" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(BSP_USING_HSOTG) + +/* Check current usb role */ +static void usb_role(void) +{ + uint32_t status = (HSOTG->STATUS) & (HSOTG_STATUS_ASHOST_Msk | HSOTG_STATUS_ASPERI_Msk | HSOTG_STATUS_IDSTS_Msk); + + if (status == (HSOTG_STATUS_IDSTS_Msk | HSOTG_STATUS_ASPERI_Msk)) + { + LOG_I("usb frame acts as peripheral\n"); + } + else if (status == HSOTG_STATUS_ASHOST_Msk) + { + LOG_I("usb frame acts as host\n"); + } + else + { + LOG_I("usb frame is unknown state: 0x%x\n", status); + } + + return; +} +MSH_CMD_EXPORT_ALIAS(usb_role, usb_role, check usb role); + +static int hsotg_init(void) +{ + void nutool_modclkcfg_init_hsusbd(void); + nutool_modclkcfg_init_hsusbd(); + + void nutool_modclkcfg_init_usbh(void); + nutool_modclkcfg_init_usbh(); + + SYS->USBPHY = (SYS_USBPHY_HSUSBEN_Msk) | + (0x2ul << SYS_USBPHY_HSUSBROLE_Pos) | + (SYS_USBPHY_SBO_Msk); + + void rt_hw_us_delay(rt_uint32_t us); + rt_hw_us_delay(40); + + /* user should keep HSUSB PHY at reset mode at lease 10 us before changing to active mode */ + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;//Set HSUSB PHY Active. + + /* Enable OTG and ID detection function */ + HSOTG_ENABLE_PHY(); + HSOTG_ENABLE_ID_DETECT(); + NVIC_EnableIRQ(HSOTG_IRQn); + + /* clear interrupt and enable relative interrupts */ + HSOTG_ENABLE_INT(HSOTG_INTEN_IDCHGIEN_Msk | HSOTG_INTEN_HOSTIEN_Msk | HSOTG_INTEN_PDEVIEN_Msk | + HSOTG_INTEN_BVLDCHGIEN_Msk | HSOTG_INTEN_AVLDCHGIEN_Msk); + + return (int)RT_EOK; +} +INIT_PREV_EXPORT(hsotg_init); + +/* HSOTG interrupt entry */ +void HSOTG_IRQHandler(void) +{ + __IO uint32_t reg = HSOTG->INTSTS; + + /* usb id pin status change */ + if (reg & HSOTG_INTSTS_IDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_IDCHGIF_Msk); + //LOG_D("usb id change"); + } + if (reg & HSOTG_INTSTS_HOSTIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_HOSTIF_Msk); + //LOG_D("usb acts as host"); + } + if (reg & HSOTG_INTSTS_PDEVIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_PDEVIF_Msk); + //LOG_D("usb acts as peripheral"); + } + if (reg & HSOTG_INTSTS_AVLDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_AVLDCHGIF_Msk); + //LOG_D("usb a-device session valid state change"); + } + if (reg & HSOTG_INTSTS_BVLDCHGIF_Msk) + { + HSOTG_CLR_INT_FLAG(HSOTG_INTSTS_BVLDCHGIF_Msk); + //LOG_D("usb b-device session valid state change"); + } +} + +#endif /* defined(BSP_USING_HSOTG) */ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c new file mode 100644 index 00000000000..0d7fa12a607 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c @@ -0,0 +1,193 @@ +/* Includes ------------------------------------------------------------------*/ +#include "rtthread.h" +#include "rtdevice.h" +#include "NuMicro.h" +#include "drv_gpio.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.usb.sw.otg" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(BOARD_USING_USB_SWOTG) && defined(RT_USING_ADC) && defined(RT_USING_PIN) + +#define DEF_ADC_DEV_NAME ("eadc0") // EADC device name +#define DEF_ADC_CC1_CHANNEL (6) // CC1 +#define DEF_ADC_CC2_CHANNEL (7) // CC2 +#define DEF_ADC_SAMPLING_DURATION (1000) // in ticks + +/* defined the PA7 PIN */ +#define DEF_MOS_G_S_PIN NU_GET_PININDEX(NU_PA, 7) + +#define THREAD_PRIORITY 5 +#define THREAD_STACK_SIZE 2048 +#define THREAD_TIMESLICE 5 + +typedef enum +{ + evUSB_ROLE_DEVICE = 0, + evUSB_ROLE_HOST, + evUSB_ROLE_NONE +} E_USB_ROLE; + +static const uint16_t s_swotg_ccx_threshold[evUSB_ROLE_NONE][2] = +{ + /* Min / Max CC1+CC2 */ + {3200, 3800}, /* evUSB_ROLE_DEVICE */ + {400, 600}, /* evUSB_ROLE_HOST */ +}; + +static int isConnectedUSBRole(const rt_int16_t *cc_sum) +{ + /* Determine the USB role based on CC1+CC2 voltage. */ + for (E_USB_ROLE role = evUSB_ROLE_DEVICE; role < evUSB_ROLE_NONE; role++) + { + /* Check if CC1+CC2 voltage is within the threshold range. */ + if ((cc_sum[role] >= s_swotg_ccx_threshold[role][0]) && + (cc_sum[role] <= s_swotg_ccx_threshold[role][1])) + { + /* Found the connected USB role */ + return role; + } + } + return evUSB_ROLE_NONE; +} + +static void swotg_worker(void *parameter) +{ + static E_USB_ROLE last_role = evUSB_ROLE_NONE; + static rt_adc_device_t s_swotg_adc_dev = RT_NULL; + + rt_err_t err = 0; + + /* Find EADC device */ + s_swotg_adc_dev = (rt_adc_device_t)rt_device_find(DEF_ADC_DEV_NAME); + if (s_swotg_adc_dev == RT_NULL) + { + rt_kprintf("Failed to find EADC device for USB OTG Type-C detection!\n"); + return; + } + err = rt_adc_enable(s_swotg_adc_dev, DEF_ADC_CC1_CHANNEL); + err |= rt_adc_enable(s_swotg_adc_dev, DEF_ADC_CC2_CHANNEL); + if (err != RT_EOK) + { + rt_kprintf("Failed to enable EADC channel for USB OTG Type-C detection!\n"); + goto fail_init; + } + +#if defined(RT_USING_PIN) + /* set LEDR pin mode to output. */ + rt_pin_mode(DEF_MOS_G_S_PIN, PIN_MODE_OUTPUT); +#endif + + /* Sample CC1 and CC2 voltages periodically. */ + while (1) + { + rt_int16_t cc_sum[2] = {0}; + + /* Sample CC1 and CC2 voltages under both USB roles. */ + for (E_USB_ROLE role = evUSB_ROLE_DEVICE; role < evUSB_ROLE_NONE; role++) + { + rt_int16_t cc1_mv, cc2_mv; + + /* Set MOS_G_S pin to select USB role */ + rt_pin_write(DEF_MOS_G_S_PIN, role); + rt_thread_mdelay(100); + + /* Read CC1 and CC2 voltages */ + cc1_mv = rt_adc_voltage((rt_adc_device_t)s_swotg_adc_dev, DEF_ADC_CC1_CHANNEL); // CC1 + cc2_mv = rt_adc_voltage((rt_adc_device_t)s_swotg_adc_dev, DEF_ADC_CC2_CHANNEL); // CC2 + + /* Sum CC1 and CC2 voltages */ + cc_sum[role] = cc1_mv + cc2_mv; + + //rt_kprintf("%d: cc1:%04d + cc2:%04d = %04d(mv)\n", role, cc1_mv, cc2_mv, cc_sum[role]); + } + E_USB_ROLE role = isConnectedUSBRole(cc_sum); + if (role != last_role) + { + //rt_kprintf("L: %d(mv), H:%d(mv)\n", cc_sum[evUSB_ROLE_DEVICE], cc_sum[evUSB_ROLE_HOST]); + + switch (role) + { + case evUSB_ROLE_DEVICE: + rt_kprintf("=> Connected to Device. (Will switch USBPHY role to Host.)\n"); + + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); // Select HSUSBH + SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; + rt_thread_mdelay(1); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + + break; + + case evUSB_ROLE_HOST: + rt_kprintf("=> Connected to Host. (Will switch USBPHY role to Device.)\n"); + + SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk)) | (0x0u << SYS_USBPHY_HSUSBROLE_Pos); // Select HSUSBD + SYS->USBPHY &= ~SYS_USBPHY_HSUSBACT_Msk; + SYS->USBPHY |= (SYS_USBPHY_HSUSBEN_Msk); + rt_thread_mdelay(1); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + + break; + + case evUSB_ROLE_NONE: + default: + /* TODO: Add USB OTG de-initialization code here. */ + rt_kprintf("=> No connected.\n"); + + SYS->USBPHY &= (~SYS_USBPHY_HSUSBEN_Msk); + + break; + } + + last_role = role; + } + + rt_thread_mdelay(DEF_ADC_SAMPLING_DURATION); + } + +fail_init: + + /* Disable EADC channels */ + if (s_swotg_adc_dev) + { + rt_adc_disable(s_swotg_adc_dev, DEF_ADC_CC1_CHANNEL); + rt_adc_disable(s_swotg_adc_dev, DEF_ADC_CC2_CHANNEL); + } + +} + +static int swotg_init(void) +{ +#define DEF_THREAD_NAME "SWOTG" + + rt_thread_t swotg_thread = rt_thread_find(DEF_THREAD_NAME); + if (swotg_thread == RT_NULL) + { + swotg_thread = rt_thread_create(DEF_THREAD_NAME, + swotg_worker, + RT_NULL, + THREAD_STACK_SIZE, + THREAD_PRIORITY, + THREAD_TIMESLICE); + + if (swotg_thread != RT_NULL) + rt_thread_startup(swotg_thread); + } + + return 0; +} + +MSH_CMD_EXPORT(swotg_init, enable ccx polling); +INIT_APP_EXPORT(swotg_init); + +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbd_hs_glue.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbd_hs_glue.c new file mode 100644 index 00000000000..8b5150277d2 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbd_hs_glue.c @@ -0,0 +1,60 @@ +/* Includes ------------------------------------------------------------------*/ +#include "rtthread.h" +#include "NuMicro.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.usbd.hs.glue" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(PKG_CHERRYUSB_DEVICE_HS) && defined(BSP_USING_HSUSBD) + +void HSUSBD_IRQHandler(void) +{ + rt_interrupt_enter(); + + void CherryUSB_USBD_IRQHandler(uint8_t busid); + CherryUSB_USBD_IRQHandler(0); + + rt_interrupt_leave(); +} + +void usb_dc_low_level_init(void) +{ +#if !defined(BSP_USING_HSOTG) + void nutool_modclkcfg_init_hsusbd(void); + nutool_modclkcfg_init_hsusbd(); + + { + /* Set PHY*/ + SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk)); // Select HSUSBD + SYS->USBPHY &= ~SYS_USBPHY_HSUSBACT_Msk; + SYS->USBPHY |= (SYS_USBPHY_HSUSBEN_Msk); + rt_thread_delay(20); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + } +#endif + + SYS_ResetModule(HSUSBD_RST); +} + +void usb_dc_low_level_deinit(void) +{ +#if !defined(BSP_USING_HSOTG) + + SYS->USBPHY &= ~(SYS_USBPHY_HSUSBACT_Msk | SYS_USBPHY_HSUSBEN_Msk); + + void nutool_modclkcfg_deinit_hsusbd(void); + nutool_modclkcfg_deinit_hsusbd(); + +#endif +} +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbh_ehci_custom_glue.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbh_ehci_custom_glue.c new file mode 100644 index 00000000000..dfe0d9d7d4e --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usbh_ehci_custom_glue.c @@ -0,0 +1,83 @@ +/* Includes ------------------------------------------------------------------*/ +#include "rtthread.h" +#include "NuMicro.h" +#include "usb_config.h" +#include "usbh_core.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.usbh.ehci.custom.glue" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(PKG_CHERRYUSB_HOST) && defined(PKG_CHERRYUSB_HOST_EHCI_CUSTOM) && defined(BSP_USING_HSUSBH) + +void HSUSBH_EHCI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + if (bus->hcd.reg_base == HSUSBH_BASE) + { +#if !defined(BSP_USING_HSOTG) + /* Enable USBH clock */ + void nutool_modclkcfg_init_usbh(void); + nutool_modclkcfg_init_usbh(); + + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; + rt_thread_mdelay(1); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + + HSUSBH->USBPCR0 = 0x160; /* EHCI: CLKSEL=10b, refclk=1b, SUSPEND=1b */ + //HSUSBH->USBPCR1 = 0x520; /* OHCI: CLKSEL=10b, NEGTX=1b, SUSPEND=1b */ +#endif + } +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + if (bus->hcd.reg_base == HSUSBH_BASE) + { + HSUSBH->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */ + + USBH->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */ + //USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */ + + /* Enable interrupt */ + NVIC_EnableIRQ(HSUSBH_EHCI_IRQn); + } +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} + +int rt_usbh_initialize(void) +{ + int bus_id = 0; + + usbh_initialize(bus_id, HSUSBH_BASE); + + return 0; +} +INIT_ENV_EXPORT(rt_usbh_initialize); +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm.c new file mode 100644 index 00000000000..4063c1b49b4 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm.c @@ -0,0 +1,221 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_BPWM) + +#include "NuMicro.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.bpwm" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define MAKE_BPWM_NAME(x) #x +#define MAKE_BPWM_INSTANCE(x) \ + { \ + .name = MAKE_BPWM_NAME(bpwm##x), \ + .base = BPWM##x, \ + .rstidx = BPWM##x##_RST, \ + .modid = BPWM##x##_MODULE, \ + }, + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + BPWM_START = -1, +#if defined(BSP_USING_BPWM0) + BPWM0_IDX, +#endif +#if defined(BSP_USING_BPWM1) + BPWM1_IDX, +#endif +#if defined(BSP_USING_BPWM2) + BPWM2_IDX, +#endif +#if defined(BSP_USING_BPWM3) + BPWM3_IDX, +#endif +#if defined(BSP_USING_BPWM4) + BPWM4_IDX, +#endif +#if defined(BSP_USING_BPWM5) + BPWM5_IDX, +#endif + + BPWM_CNT +}; + +struct nu_bpwm +{ + struct rt_device_pwm dev; + char *name; + BPWM_T *base; + uint32_t rstidx; + uint32_t modid; + rt_int32_t pwm_period_time; +}; +typedef struct nu_bpwm *nu_bpwm_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_pwm_ops nu_bpwm_ops = +{ + .control = nu_bpwm_control +}; + +static struct nu_bpwm nu_bpwm_arr [] = +{ +#if defined(BSP_USING_BPWM0) + MAKE_BPWM_INSTANCE(0) +#endif +#if defined(BSP_USING_BPWM1) + MAKE_BPWM_INSTANCE(1) +#endif +#if defined(BSP_USING_BPWM2) + MAKE_BPWM_INSTANCE(2) +#endif +#if defined(BSP_USING_BPWM3) + MAKE_BPWM_INSTANCE(3) +#endif +#if defined(BSP_USING_BPWM4) + MAKE_BPWM_INSTANCE(4) +#endif +#if defined(BSP_USING_BPWM5) + MAKE_BPWM_INSTANCE(5) +#endif +}; /* bpwm nu_bpwm */ + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_bpwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + + BPWM_T *pwm_base = ((nu_bpwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + + if (enable == RT_TRUE) + { + BPWM_EnableOutput(pwm_base, 1 << pwm_channel); + BPWM_Start(pwm_base, 1 << pwm_channel); + } + else + { + BPWM_DisableOutput(pwm_base, 1 << pwm_channel); + //BPWM_ForceStop(pwm_base, 1 << pwm_channel); + } + + return result; +} + +static rt_err_t nu_bpwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + if ((((struct rt_pwm_configuration *)configuration)->period) <= 0) + return -(RT_ERROR); + + rt_uint32_t pwm_freq, pwm_dutycycle; + BPWM_T *pwm_base = ((nu_bpwm_t)device)->base; + rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period; + rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse; + + pwm_dutycycle = (pwm_pulse * 100) / pwm_period; + + if (BPWM_GET_CNR(pwm_base, pwm_channel) != 0) + { + pwm_period = ((nu_bpwm_t)device)->pwm_period_time; + LOG_I("%s output frequency is determined, user can only change the duty\n", ((nu_bpwm_t)device)->name); + } + else + { + ((nu_bpwm_t)device)->pwm_period_time = pwm_period; + } + + pwm_freq = 1000000000 / pwm_period; + + BPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ; + + return RT_EOK; +} + +static rt_uint32_t nu_bpwm_clksr(struct rt_device_pwm *device) +{ + return CLK_GetPCLK0Freq(); //Both PCLK0 && PCLK1 are the same. +} + +static rt_err_t nu_bpwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32BPWMClockSrc ; + + BPWM_T *pwm_base = ((nu_bpwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_prescale = pwm_base->CLKPSC; + rt_uint32_t pwm_period = BPWM_GET_CNR(pwm_base, pwm_channel); + rt_uint32_t pwm_pulse = BPWM_GET_CMR(pwm_base, pwm_channel); + + u32BPWMClockSrc = nu_bpwm_clksr(device); + time_tick = (uint64_t)1000000000000 / u32BPWMClockSrc; + + pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000; + pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000; + ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period; + ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty; + + LOG_I("%s %d %d %d\n", ((nu_bpwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(device); + RT_ASSERT(configuration); + + if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > BPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_bpwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_bpwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return nu_bpwm_set(device, configuration); + case PWM_CMD_GET: + return nu_bpwm_get(device, configuration); + } + return -(RT_EINVAL); +} + +static int rt_hw_bpwm_init(void) +{ + rt_err_t ret; + int i; + + for (i = (BPWM_START + 1); i < BPWM_CNT; i++) + { + CLK_EnableModuleClock(nu_bpwm_arr[i].modid); + + SYS_ResetModule(nu_bpwm_arr[i].rstidx); + ret = rt_device_pwm_register(&nu_bpwm_arr[i].dev, nu_bpwm_arr[i].name, &nu_bpwm_ops, RT_NULL); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_bpwm_init); + +#endif //#if defined(BSP_USING_BPWM) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm_capture.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm_capture.c new file mode 100644 index 00000000000..2fc015cf885 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_bpwm_capture.c @@ -0,0 +1,385 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_BPWM_CAPTURE) + +#include "NuMicro.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.bpwmcap" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* First rising and falling edge should be ignore */ +#define NU_DUMMY_DATA 2 + +#define NU_NO_EDGE 0 +#define NU_RISING_EDGE 1 +#define NU_FALLING_EDGE 2 +#define NU_BOTH_EDGE 3 + +#define STR(x) #x +#define XSTR(x) STR(x) +#define CONCAT3(a, b, c) a##b##c +#define XCONCAT3(a, b, c) CONCAT3(a, b, c) +#define MAKE_BPWM_CAPTURE_NAME(x, y) XSTR(XCONCAT3(bpwm, x, y)) + +#define MAKE_BPWM_CAPTURE_INSTANCE(x, y) \ + { \ + .name = MAKE_BPWM_CAPTURE_NAME(x, y), \ + .base = BPWM##x, \ + .irqn = BPWM##x##_IRQn, \ + .rstidx = BPWM##x##_RST, \ + .modid = BPWM##x##_MODULE, \ + }, + +#define FOR_EACH_BPWM_CHANNEL(x) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i0) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i1) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i2) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i3) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i4) \ + MAKE_BPWM_CAPTURE_INSTANCE(x, i5) + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + BPWM_IDX_START = -1, +#if defined(BSP_USING_BPWM0_CAPTURE) + BPWM0I0_IDX, + BPWM0I1_IDX, + BPWM0I2_IDX, + BPWM0I3_IDX, + BPWM0I4_IDX, + BPWM0I5_IDX, +#endif +#if defined(BSP_USING_BPWM1_CAPTURE) + BPWM1I0_IDX, + BPWM1I1_IDX, + BPWM1I2_IDX, + BPWM1I3_IDX, + BPWM1I4_IDX, + BPWM1I5_IDX, +#endif +#if defined(BSP_USING_BPWM2_CAPTURE) + BPWM2I0_IDX, + BPWM2I1_IDX, + BPWM2I2_IDX, + BPWM2I3_IDX, + BPWM2I4_IDX, + BPWM2I5_IDX, +#endif +#if defined(BSP_USING_BPWM3_CAPTURE) + BPWM3I0_IDX, + BPWM3I1_IDX, + BPWM3I2_IDX, + BPWM3I3_IDX, + BPWM3I4_IDX, + BPWM3I5_IDX, +#endif +#if defined(BSP_USING_BPWM4_CAPTURE) + BPWM4I0_IDX, + BPWM4I1_IDX, + BPWM4I2_IDX, + BPWM4I3_IDX, + BPWM4I4_IDX, + BPWM4I5_IDX, +#endif +#if defined(BSP_USING_BPWM5_CAPTURE) + BPWM5I0_IDX, + BPWM5I1_IDX, + BPWM5I2_IDX, + BPWM5I3_IDX, + BPWM5I4_IDX, + BPWM5I5_IDX, +#endif + BPWM_IDX_CNT +}; + +struct nu_bpwmcap +{ + struct rt_inputcapture_device parent; + BPWM_T *base; + char *name; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + float fUsPerTick; + uint8_t u8Channel; + uint8_t u8DummyData; + uint32_t u32CurrentRisingCnt; + uint32_t u32CurrentFallingCnt; + uint32_t u32LastRisingCnt; + uint32_t u32LastFallingCnt; + rt_bool_t input_data_level; +}; +typedef struct nu_bpwmcap *nu_bpwmcap_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_bpwmcap_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_bpwmcap_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_bpwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); +static void nu_bpwmcap_isr(nu_bpwmcap_t psNuBpwmCapBase); +static void nu_bpwmcap_reset(nu_bpwmcap_t psNuBpwmCap); +static int rt_hw_bpwmcap_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_bpwmcap nu_bpwmcap_arr [] = +{ +#if defined(BSP_USING_BPWM0_CAPTURE) + FOR_EACH_BPWM_CHANNEL(0) +#endif +#if defined(BSP_USING_BPWM1_CAPTURE) + FOR_EACH_BPWM_CHANNEL(1) +#endif +#if defined(BSP_USING_BPWM2_CAPTURE) + FOR_EACH_BPWM_CHANNEL(2) +#endif +#if defined(BSP_USING_BPWM3_CAPTURE) + FOR_EACH_BPWM_CHANNEL(3) +#endif +#if defined(BSP_USING_BPWM4_CAPTURE) + FOR_EACH_BPWM_CHANNEL(4) +#endif +#if defined(BSP_USING_BPWM5_CAPTURE) + FOR_EACH_BPWM_CHANNEL(5) +#endif +}; + +static struct rt_inputcapture_ops nu_bpwmcap_ops = +{ + .init = NULL, + .open = nu_bpwmcap_open, + .close = nu_bpwmcap_close, + .get_pulsewidth = nu_bpwmcap_get_pulsewidth, +}; + +/* Functions Implementation --------------------------------------------------*/ +static void nu_bpwmcap_isr(nu_bpwmcap_t psNuBpwmCapBase) +{ + int i; + uint32_t u32Status; + + for (i = 0; i < BPWM_CHANNEL_NUM; i++) + { + nu_bpwmcap_t psNuBpwmCap = psNuBpwmCapBase + i; + + if ((psNuBpwmCap->base->CAPCTL & (0x1 << i)) == 0) + continue; + + u32Status = BPWM_GetCaptureIntFlag(psNuBpwmCap->base, psNuBpwmCap->u8Channel); + switch (u32Status) + { + case NU_NO_EDGE: + break; + + case NU_RISING_EDGE: + BPWM_ClearCaptureIntFlag(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_RISING_LATCH); + psNuBpwmCap->u32CurrentRisingCnt = BPWM_GET_CAPTURE_RISING_DATA(psNuBpwmCap->base, psNuBpwmCap->u8Channel); + + rt_hw_inputcapture_isr(&psNuBpwmCap->parent, psNuBpwmCap->input_data_level); + + break; + + case NU_FALLING_EDGE: + BPWM_ClearCaptureIntFlag(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_FALLING_LATCH); + psNuBpwmCap->u32CurrentFallingCnt = BPWM_GET_CAPTURE_FALLING_DATA(psNuBpwmCap->base, psNuBpwmCap->u8Channel); + + rt_hw_inputcapture_isr(&psNuBpwmCap->parent, psNuBpwmCap->input_data_level); + + break; + + case NU_BOTH_EDGE: + BPWM_ClearCaptureIntFlag(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_RISING_LATCH | BPWM_CAPTURE_INT_FALLING_LATCH); + BPWM_GET_CAPTURE_FALLING_DATA(psNuBpwmCap->base, psNuBpwmCap->u8Channel); + BPWM_GET_CAPTURE_RISING_DATA(psNuBpwmCap->base, psNuBpwmCap->u8Channel); + break; + + default: + break; + + } + + } +} + +#define MAKE_BPWM_CAPTURE_ISR(x) \ + void BPWM##x##_IRQHandler(void) \ + { \ + rt_interrupt_enter(); \ + nu_bpwmcap_isr(&nu_bpwmcap_arr[BPWM##x##I0_IDX]); \ + rt_interrupt_leave(); \ + } + +#if defined(BSP_USING_BPWM0_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(0); +#endif +#if defined(BSP_USING_BPWM1_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(1); +#endif +#if defined(BSP_USING_BPWM2_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(2); +#endif +#if defined(BSP_USING_BPWM3_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(3); +#endif +#if defined(BSP_USING_BPWM4_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(4); +#endif +#if defined(BSP_USING_BPWM5_CAPTURE) + MAKE_BPWM_CAPTURE_ISR(5); +#endif + +static rt_err_t nu_bpwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + float fTempCnt; + nu_bpwmcap_t psNuBpwmCap = (nu_bpwmcap_t)inputcapture; + + RT_ASSERT(inputcapture); + + if (psNuBpwmCap->u32CurrentFallingCnt) + { + if (psNuBpwmCap->u32CurrentFallingCnt > psNuBpwmCap->u32LastRisingCnt) + fTempCnt = psNuBpwmCap->u32CurrentFallingCnt - psNuBpwmCap->u32LastRisingCnt; + else /* Overrun case */ + fTempCnt = psNuBpwmCap->u32CurrentFallingCnt + (0x10000 - psNuBpwmCap->u32LastRisingCnt); + + *pulsewidth_us = fTempCnt * psNuBpwmCap->fUsPerTick; + psNuBpwmCap->input_data_level = RT_FALSE; + psNuBpwmCap->u32LastFallingCnt = psNuBpwmCap->u32CurrentFallingCnt; + psNuBpwmCap->u32CurrentFallingCnt = 0; + } + else if (psNuBpwmCap->u32CurrentRisingCnt) + { + if (psNuBpwmCap->u32CurrentRisingCnt > psNuBpwmCap->u32LastFallingCnt) + fTempCnt = psNuBpwmCap->u32CurrentRisingCnt - psNuBpwmCap->u32LastFallingCnt; + else /* Overrun case */ + fTempCnt = psNuBpwmCap->u32CurrentRisingCnt + (0x10000 - psNuBpwmCap->u32LastFallingCnt); + + *pulsewidth_us = fTempCnt * psNuBpwmCap->fUsPerTick; + psNuBpwmCap->input_data_level = RT_TRUE; + psNuBpwmCap->u32LastRisingCnt = psNuBpwmCap->u32CurrentRisingCnt; + psNuBpwmCap->u32CurrentRisingCnt = 0; + } + else + { + ret = RT_ERROR; + } + return -(ret); +} + +static void nu_bpwmcap_reset(nu_bpwmcap_t psNuBpwmCap) +{ + psNuBpwmCap->u8DummyData = 0; + psNuBpwmCap->u32CurrentFallingCnt = 0; + psNuBpwmCap->u32CurrentRisingCnt = 0; + psNuBpwmCap->u32LastRisingCnt = 0; + psNuBpwmCap->u32LastFallingCnt = 0; +} + +static rt_err_t nu_bpwmcap_open(struct rt_inputcapture_device *inputcapture) +{ + nu_bpwmcap_t psNuBpwmCap = (nu_bpwmcap_t) inputcapture; + + RT_ASSERT(inputcapture); + + nu_bpwmcap_reset(psNuBpwmCap); + + /* Set capture time as 500 nano second */ + psNuBpwmCap->fUsPerTick = (float)BPWM_ConfigCaptureChannel(psNuBpwmCap->base, psNuBpwmCap->u8Channel, 500, 0) / 1000; + + /* Set counter type as up count */ + BPWM_SET_ALIGNED_TYPE(psNuBpwmCap->base, (0x1 << psNuBpwmCap->u8Channel), BPWM_UP_COUNTER); + + /* Enable BPWM Timer */ + BPWM_Start(psNuBpwmCap->base, (0x1 << psNuBpwmCap->u8Channel)); + + /* Enable capture rising/falling edge interrupt */ + BPWM_EnableCaptureInt(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable Capture Function for BPWM */ + BPWM_EnableCapture(psNuBpwmCap->base, 0x1 << psNuBpwmCap->u8Channel); + + /* Enable BPWM NVIC interrupt */ + if ((psNuBpwmCap->base->CAPCTL & ((0x1 << BPWM_CHANNEL_NUM) - 1)) != 0u) + NVIC_EnableIRQ(psNuBpwmCap->irqn); + + return RT_EOK; +} + +static rt_err_t nu_bpwmcap_close(struct rt_inputcapture_device *inputcapture) +{ + nu_bpwmcap_t psNuBpwmCap = (nu_bpwmcap_t) inputcapture; + + RT_ASSERT(inputcapture); + + /* Disable capture rising/falling edge interrupt */ + BPWM_DisableCaptureInt(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable Capture Function for BPWM */ + BPWM_DisableCapture(psNuBpwmCap->base, 0x1 << psNuBpwmCap->u8Channel); + + /* Clear Capture Interrupt flag for BPWM */ + BPWM_ClearCaptureIntFlag(psNuBpwmCap->base, + psNuBpwmCap->u8Channel, + BPWM_CAPTURE_INT_RISING_LATCH | BPWM_CAPTURE_INT_FALLING_LATCH); + + /* Disable BPWM Timer */ + BPWM_Stop(psNuBpwmCap->base, (0x1 << psNuBpwmCap->u8Channel)); + + /* Disable BPWM NVIC interrupt */ + if ((psNuBpwmCap->base->CAPCTL & ((0x1 << BPWM_CHANNEL_NUM) - 1)) == 0u) + NVIC_DisableIRQ(psNuBpwmCap->irqn); + + nu_bpwmcap_reset(psNuBpwmCap); + + return RT_EOK; +} + +static int rt_hw_bpwmcap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (BPWM_IDX_START + 1); i < BPWM_IDX_CNT; i++) + { + nu_bpwmcap_t psNuBpwmCap = &nu_bpwmcap_arr[i]; + + psNuBpwmCap->u8Channel = i % BPWM_CHANNEL_NUM; + psNuBpwmCap->parent.ops = &nu_bpwmcap_ops; + nu_bpwmcap_reset(psNuBpwmCap); + + if ((psNuBpwmCap->u8Channel % BPWM_CHANNEL_NUM) == 0) + { + /* Enable bpwm module */ + CLK_EnableModuleClock(psNuBpwmCap->modid); + SYS_ResetModule(psNuBpwmCap->rstidx); + } + ret = rt_device_inputcapture_register(&psNuBpwmCap->parent, psNuBpwmCap->name, psNuBpwmCap); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_bpwmcap_init); + +#endif //#if defined(BSP_USING_BPWM_CAPTURE) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c new file mode 100644 index 00000000000..22c61b919d2 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c @@ -0,0 +1,691 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_CANFD) + +#include "NuMicro.h" +#include "nu_bitutil.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.canfd" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DEFINE_NU_CANFD(_idx, _rstidx, _irqn0, _irqn1) \ + { \ + .name = "canfd" #_idx, \ + .base = CANFD##_idx, \ + .rstidx = _rstidx, \ + .irqn0 = _irqn0, \ + .irqn1 = _irqn1, \ + } + +#define DEFINE_CANFD_IRQ_HANDLER(_irq, _idx) \ +void CANFD##_irq##_IRQHandler(void) \ +{ \ + rt_interrupt_enter(); \ + \ + nu_canfd_isr(&nu_canfd_arr[CANFD##_idx##_IDX]); \ + \ + rt_interrupt_leave(); \ +} +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) + +/* Default config for serial_configure structure */ +#define NU_CANFD_CONFIG_DEFAULT \ +{ \ + CAN1MBaud, /* 1M bits/s */ \ + RT_CANMSG_BOX_SZ, /* message box max size */ \ + RT_CANSND_BOX_NUM, /* message box number */ \ + RT_CAN_MODE_NORMAL, /* Normal mode */ \ + 0, /* privmode */ \ + 0, /* reserved */ \ + 100, /* Timeout Tick */ \ +} + +/* Types / Structures ---------------------------------------------------------*/ + +enum +{ + CANFD_START = -1, +#if defined(BSP_USING_CANFD0) + CANFD0_IDX, +#endif +#if defined(BSP_USING_CANFD1) + CANFD1_IDX, +#endif + CANFD_CNT +}; + +struct nu_canfd +{ + struct rt_can_device dev; + char *name; + CANFD_T *base; + uint32_t rstidx; + IRQn_Type irqn0; + IRQn_Type irqn1; + uint32_t int_flag; + CANFD_FD_T sCANFD_Config; +}; +typedef struct nu_canfd *nu_canfd_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_canfd_configure(struct rt_can_device *can, struct can_configure *cfg); +static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg); +static int nu_canfd_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); +static int nu_canfd_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); +static void nu_canfd_isr(nu_canfd_t can); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_canfd nu_canfd_arr[] = +{ +#if defined(BSP_USING_CANFD0) + DEFINE_NU_CANFD(0, CANFD0_RST, CANFD00_IRQn, CANFD01_IRQn), +#endif +#if defined(BSP_USING_CANFD1) + DEFINE_NU_CANFD(1, CANFD1_RST, CANFD10_IRQn, CANFD11_IRQn), +#endif +}; /* struct nu_can */ + +static const struct rt_can_ops nu_canfd_ops = +{ + .configure = nu_canfd_configure, + .control = nu_canfd_control, + .sendmsg = nu_canfd_sendmsg, + .recvmsg = nu_canfd_recvmsg, +}; + +static const struct can_configure nu_canfd_default_config = NU_CANFD_CONFIG_DEFAULT; + +static const char *szIR[] = +{ + "CANFD_IR_RF0N - Rx FIFO 0 New Message", + "CANFD_IR_RF0W - Rx FIFO 0 Watermark Reached", + "CANFD_IR_RF0F - Rx FIFO 0 Full", + "CANFD_IR_RF0L - Rx FIFO 0 Message Lost", + "CANFD_IR_RF1N - Rx FIFO 1 New Message", + "CANFD_IR_RF1W - Rx FIFO 1 Watermark Reached", + "CANFD_IR_RF1F - Rx FIFO 1 Full", + "CANFD_IR_RF1L - Rx FIFO 1 Message Lost", + "CANFD_IR_HPM - High Priority Message", + "CANFD_IR_TC - Transmission Completed", + "CANFD_IR_TCF - Transmission Cancellation Finished", + "CANFD_IR_TFE - Tx FIFO Empty", + "CANFD_IR_TEFN - Tx Event FIFO New Entry", + "CANFD_IR_TEFW - Tx Event FIFO Watermark Reached", + "CANFD_IR_TEFF - Tx Event FIFO Full", + "CANFD_IR_TEFL - Tx Event FIFO Event Lost", + "CANFD_IR_TSW - Timestamp Wraparound", + "CANFD_IR_MRAF - Message RAM Access Failure", + "CANFD_IR_TOO - Timeout Occurred", + "CANFD_IR_DRX - Message stored to Dedicated Rx Buffer", + "BIT20", + "BIT21", + "CANFD_IR_ELO - Error Logging Overflow", + "CANFD_IR_EP - Error Passive", + "CANFD_IR_EW - Warning Status", + "CANFD_IR_BO - Bus_Off Status", + "CANFD_IR_WDI - Watchdog", + "CANFD_IR_PEA - Protocol Error in Arbitration Phase", + "CANFD_IR_PED - Protocol Error in Data Phase", + "CANFD_IR_ARA - Access to Reserved Address", + "BIT30", + "BIT31" +}; + +/* Functions Implementation --------------------------------------------------*/ +#if defined(BSP_USING_CANFD0) +/* CAN0 interrupt entry */ +DEFINE_CANFD_IRQ_HANDLER(00, 0) +DEFINE_CANFD_IRQ_HANDLER(01, 0) +#endif + +#if defined(BSP_USING_CANFD1) +DEFINE_CANFD_IRQ_HANDLER(10, 1) +DEFINE_CANFD_IRQ_HANDLER(11, 1) +#endif + +static void dump_interrupt_event(uint32_t u32Status) +{ + uint32_t idx; + while ((idx = nu_ctz(u32Status)) < 32) // Count Trailing Zeros == > Find First One + { + LOG_D("[%s]", szIR[idx]); + u32Status &= ~(1 << idx); + } +} + +static void nu_canfd_isr(nu_canfd_t psNuCANFD) +{ + /* Get base address of CAN register */ + CANFD_T *base = psNuCANFD->base; + + /* Get interrupt status */ + uint32_t u32Status = base->IR; + CANFD_ClearStatusFlag(base, u32Status); + + /* Dump IR event */ + dump_interrupt_event(u32Status); + + /* Check Status Interrupt Flag (Error status Int and Status change Int) */ + /**************************/ + /* Status Change interrupt*/ + /**************************/ + + if (u32Status & CANFD_IR_TC_Msk) + { + if (psNuCANFD->int_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_TX_DONE); + } + } + + if (u32Status & (CANFD_IR_RF0N_Msk | CANFD_IR_RF1N_Msk)) + { + if (psNuCANFD->int_flag & RT_DEVICE_FLAG_INT_RX) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_RX_IND); + } + } + + if (u32Status & (CANFD_IR_RF0L_Msk | CANFD_IR_RF1L_Msk)) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_RXOF_IND); + } + + if (u32Status & (CANFD_IR_TEFF_Msk | CANFD_IR_TOO_Msk)) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_TX_FAIL); + } + if (u32Status & CANFD_IR_EW_Msk) + { + LOG_E("[%s]EWARN", psNuCANFD->name) ; + } + + if (u32Status & CANFD_IR_BO_Msk) + { + LOG_E("[%s]BUSOFF", psNuCANFD->name) ; + + /* To release busoff pin */ + } + + if (u32Status & CANFD_IR_PED_Msk) + { + LOG_E("[%s] LEC: %03x\n", psNuCANFD->name, base->PSR & CANFD_PSR_LEC_Msk) ; + } +} + +static void nu_canfd_ie(nu_canfd_t psNuCANFD) +{ + uint32_t u32CanFDIE = CANFD_IE_BOE_Msk; + + if (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_RX)) + { + /* Rx FIFO 0 New Message Interrupt */ + u32CanFDIE |= (CANFD_IE_RF0NE_Msk | CANFD_IE_RF1NE_Msk); + } + + if (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) + { + /* Transmission Completed Interrupt */ + /* Timeout Occurred Interrupt */ + u32CanFDIE |= (CANFD_IE_TCE_Msk | CANFD_IE_TEFNE_Msk); + } + + if (psNuCANFD->int_flag & RT_DEVICE_CAN_INT_ERR) + { + /* Bus_Off Status Interrupt */ + /* Warning Status Interrupt */ + /* Error Passive Interrupt */ + /* Error Logging Overflow Interrupt */ + /* Protocol Error in Data Phase interrupt Indicator */ + u32CanFDIE |= (CANFD_IE_EPE_Msk | CANFD_IE_EWE_Msk | CANFD_IE_ELOE_Msk | CANFD_IE_TOOE_Msk | CANFD_IR_PED_Msk); + } + + CANFD_EnableInt(psNuCANFD->base, u32CanFDIE, 0, + (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) ? CANFD_TXBTIE_TIEn_Msk : 0, + (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) ? CANFD_TXBCIE_CFIEn_Msk : 0); +} + +static rt_err_t nu_canfd_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + CANFD_FD_T *psCANFDConf; + CANFD_ELEM_SIZE_T *psCANFDElemSize; + uint32_t u32UsedRamSize; + + RT_ASSERT(can); + RT_ASSERT(cfg); + + /* Get base address of CAN register */ + CANFD_T *base = psNuCANFD->base; + + psCANFDConf = &psNuCANFD->sCANFD_Config; + + psCANFDElemSize = &psCANFDConf->sElemSize; + + /* CAN FD Standard message ID elements as 8 elements */ + psCANFDElemSize->u32SIDFC = 8; + /* CAN FD Extended message ID elements as 8 elements */ + psCANFDElemSize->u32XIDFC = 8; + /* CAN FD TX Buffer elements as 4 elements */ + psCANFDElemSize->u32TxBuf = 4; + /* CAN FD Tx FIFO/Queue elements as 4 elements */ + //psCANFDElemSize->u32TxFifoQueue = 4; + /* CAN FD RX Buffer elements as 3 elements */ + psCANFDElemSize->u32RxBuf = 4; + /* CAN FD RX FIFO0 elements as 3 elements */ + psCANFDElemSize->u32RxFifo0 = 4; + /* CAN FD RX FIFO1 elements as 3 elements */ + psCANFDElemSize->u32RxFifo1 = 0; + /* CAN FD TX Event FIFO elements as 3 elements */ + psCANFDElemSize->u32TxEventFifo = 4; + /* User-defined element size. */ + psCANFDElemSize->u32UserDef = 1; + + /*Calculates the CAN FD RAM buffer address*/ + u32UsedRamSize = CANFD_GetDefaultConfig(psCANFDConf, CANFD_OP_CAN_MODE); + + LOG_I("Message Ram Size: %d @%08x ~ %08x, Used: %d Bytes", + psCANFDConf->u32MRamSize, + CANFD_SRAM_BASE_ADDR(base), + psCANFDConf->u32MRamSize + CANFD_SRAM_BASE_ADDR(base), + u32UsedRamSize); + + LOG_I("SIDFC(%d): %d @%08x Size: %dB", + sizeof(CANFD_SID_FILTER_T), + psCANFDConf->sElemSize.u32SIDFC, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32SIDFC_FLSSA, + psCANFDConf->sElemSize.u32SIDFC * sizeof(CANFD_SID_FILTER_T)); + + LOG_I("XIDFC(%d): %d @%08x Size: %dB", + sizeof(CANFD_XID_FILTER_T), + psCANFDConf->sElemSize.u32XIDFC, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32XIDFC_FLESA, + psCANFDConf->sElemSize.u32XIDFC * sizeof(CANFD_XID_FILTER_T)); + + LOG_I("RxFifo0(%d): %d @%08x Size: %dB", + sizeof(CANFD_RX_BUF_T), + psCANFDConf->sElemSize.u32RxFifo0, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXF0C_F0SA, + psCANFDConf->sElemSize.u32RxFifo0 * sizeof(CANFD_RX_BUF_T)); + + LOG_I("RxFifo1(%d): %d @%08x Size: %dB", + sizeof(CANFD_RX_BUF_T), + psCANFDConf->sElemSize.u32RxFifo1, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXF1C_F1SA, + psCANFDConf->sElemSize.u32RxFifo1 * sizeof(CANFD_RX_BUF_T)); + + LOG_I("RxBuf(%d): %d @%08x Size: %dB", + sizeof(CANFD_RX_BUF_T), + psCANFDConf->sElemSize.u32RxBuf, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXBC_RBSA, + psCANFDConf->sElemSize.u32RxBuf * sizeof(CANFD_RX_BUF_T)); + + LOG_I("TxEventFifo(%d): %d @%08x Size: %dB", + sizeof(CANFD_TX_EVENT_T), + psCANFDConf->sElemSize.u32TxEventFifo, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32TXEFC_EFSA, + psCANFDConf->sElemSize.u32TxEventFifo * sizeof(CANFD_TX_EVENT_T)); + + LOG_I("TxBuf(%d): %d @%08x Size: %dB", + sizeof(CANFD_TX_BUF_T), + psCANFDConf->sElemSize.u32TxBuf, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32TXBC_TBSA, + psCANFDConf->sElemSize.u32TxBuf * sizeof(CANFD_TX_BUF_T)); + + LOG_I("TxFifoQueue(%d): %d @%08x Size: %dB", + sizeof(CANFD_TX_BUF_T), + psCANFDConf->sElemSize.u32TxFifoQueue, + CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32TXBC_TBSA + psCANFDElemSize->u32TxBuf * sizeof(CANFD_TX_BUF_T), + psCANFDConf->sElemSize.u32TxFifoQueue * sizeof(CANFD_TX_BUF_T)); + + RT_ASSERT(u32UsedRamSize <= psCANFDConf->u32MRamSize); + + psCANFDConf->sBtConfig.sNormBitRate.u32BitRate = cfg->baud_rate; + psCANFDConf->sBtConfig.sDataBitRate.u32BitRate = 0; + + LOG_I("CAN Baud rate: %d bps", cfg->baud_rate); + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: // Normal + psCANFDConf->sBtConfig.evTestMode = eCANFD_NORMAL; + break; + + case RT_CAN_MODE_LISTEN: // Bus monitor Mode, can't start a transmission + psCANFDConf->sBtConfig.evTestMode = eCANFD_BUS_MONITOR; + break; + + case RT_CAN_MODE_LOOPBACK: // Test - Internal loopback + psCANFDConf->sBtConfig.evTestMode = eCANFD_LOOPBACK_INTERNAL; + break; + + case RT_CAN_MODE_LOOPBACKANLISTEN: + default: + rt_kprintf("Unsupported Operating mode\n"); + goto exit_nu_canfd_configure; + } + CANFD_Open(base, psCANFDConf); + + /* Set FIFO policy */ +#if defined(RT_CAN_USING_HDR) + /* Whitelist filtering */ + CANFD_SetGFC(base, eCANFD_REJ_NON_MATCH_FRM, eCANFD_REJ_NON_MATCH_FRM, 0, 0); +#else + /* Blacklist filtering. */ + CANFD_SetGFC(base, eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0, eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0, 0, 0); +#endif + + /* Enable interrupt */ + nu_canfd_ie(psNuCANFD); + + //LOG_HEX("canfd", 16, (void *)base, sizeof(CANFD_T)); + + /* Lock protected registers & Run */ + CANFD_RunToNormal(base, TRUE); + + return RT_EOK; + +exit_nu_canfd_configure: + + CANFD_Close(base); + + return -(RT_ERROR); +} + +static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg) +{ + rt_uint32_t argval = (rt_uint32_t)arg; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + + switch (cmd) + { + case RT_DEVICE_CTRL_SET_INT: + { + psNuCANFD->int_flag |= argval; + return nu_canfd_configure(can, &can->config); + } + case RT_DEVICE_CTRL_CLR_INT: + { + psNuCANFD->int_flag &= ~argval; + return nu_canfd_configure(can, &can->config); + } + +#if defined(RT_CAN_USING_HDR) + case RT_CAN_CMD_SET_FILTER: + { + struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg; + + RT_ASSERT(filter_cfg); + + for (int i = 0; i < filter_cfg->count; i++) + { + uint32_t u32FEC = (filter_cfg->items[i].mode == RT_CAN_MODE_PRIV) ? eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 : eCANFD_FLTR_ELEM_STO_FIFO0; + + /* Set the filter rule */ + if (filter_cfg->items[i].ide == RT_CAN_STDID) + { + /* for 11-bit */ + CANFD_SID_FILTER_T sStdFilter; + + if (i >= CANFD_MAX_11_BIT_FTR_ELEMS) // Check filter entry limitation + return -(RT_ERROR); + + sStdFilter.SFID2 = filter_cfg->items[i].mask; /*!items[i].id; /*!base, eCANFD_MSG_SID, &sStdFilter, i); + } + else + { + /* for 29-bit */ + CANFD_XID_FILTER_T sXidFilter; + + if (i >= CANFD_MAX_29_BIT_FTR_ELEMS) // Check filter entry limitation + return -(RT_ERROR); + + sXidFilter.EFID1 = filter_cfg->items[i].mask; /*!items[i].id; /*!base, eCANFD_MSG_XID, &sXidFilter, i); + } + + } + } + break; +#endif + + case RT_CAN_CMD_SET_MODE: + { + if ((argval == RT_CAN_MODE_NORMAL) || + (argval == RT_CAN_MODE_LISTEN) || + (argval == RT_CAN_MODE_LOOPBACK) || + (argval == RT_CAN_MODE_LOOPBACKANLISTEN)) + { + if (argval != can->config.mode) + { + can->config.mode = argval; + return nu_canfd_configure(can, &can->config); + } + } + else + { + return -(RT_ERROR); + } + } + break; + + case RT_CAN_CMD_SET_BAUD: + { + if ((argval == CAN1MBaud) || + (argval == CAN800kBaud) || + (argval == CAN500kBaud) || + (argval == CAN250kBaud) || + (argval == CAN125kBaud) || + (argval == CAN100kBaud) || + (argval == CAN50kBaud) || + (argval == CAN20kBaud) || + (argval == CAN10kBaud)) + { + if (argval != can->config.baud_rate) + { + can->config.baud_rate = argval; + return nu_canfd_configure(can, &can->config); + } + } + else + { + return -(RT_ERROR); + } + } + break; + + case RT_CAN_CMD_SET_PRIV: + { + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -(RT_ERROR); + } + if (argval != can->config.privmode) + { + can->config.privmode = argval; + return nu_canfd_configure(can, &can->config); + } + } + break; + + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t u32ErrCounter = psNuCANFD->base->ECR; + rt_uint32_t u32ProtocolStatus = psNuCANFD->base->PSR; + + RT_ASSERT(arg); + + /*Receive Error Counter, return value is with Receive Error Passive.*/ + can->status.rcverrcnt = ((u32ErrCounter & CANFD_ECR_REC_Msk) >> CANFD_ECR_REC_Pos); + + /*Transmit Error Counter*/ + can->status.snderrcnt = ((u32ErrCounter & CANFD_ECR_TEC_Msk) >> CANFD_ECR_TEC_Pos); + + /*Last Error Type*/ + can->status.lasterrtype = ((u32ProtocolStatus & CANFD_PSR_LEC_Msk) >> CANFD_PSR_LEC_Pos); + + /*Status error code*/ + can->status.errcode = (u32ProtocolStatus & CANFD_PSR_EW_Msk) ? 1 : + (u32ProtocolStatus & CANFD_PSR_EP_Msk) ? 2 : + (u32ProtocolStatus & CANFD_PSR_BO_Msk) ? 3 : + 0; + + rt_memcpy(arg, &can->status, sizeof(struct rt_can_status)); + } + break; + + default: + return -(RT_EINVAL); + + } + + return RT_EOK; +} + +static int nu_canfd_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + CANFD_TX_BUF_T sTxMsg = {0}; + + struct rt_can_msg *pmsg = (struct rt_can_msg *)buf; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + RT_ASSERT(buf); + + /* Extended ID */ + sTxMsg.XTD = pmsg->ide; + + /* Message ID */ + if (sTxMsg.XTD) + { + /* 29-bit ID */ + sTxMsg.ID = pmsg->id; + } + else + { + /* 11-bit ID */ + sTxMsg.ID = CANFD_SET_SID(pmsg->id); + } + sTxMsg.BRS = 0; + + /* Remote Transmission Request */ + sTxMsg.RTR = pmsg->rtr; + + /* Check the parameters */ + if (pmsg->len > 0) + { + sTxMsg.DLC = CANFD_EncodeDLC(pmsg->len); + + if (pmsg->len > 0) + { + rt_memcpy(&sTxMsg.DB[0], &pmsg->data[0], pmsg->len); + } + } + + if (CANFD_Transfer(psNuCANFD->base, eCANFD_MSG_DTB, &sTxMsg, boxno) == NULL) + { + goto exit_nu_canfd_sendmsg; + } + + return RT_EOK; + +exit_nu_canfd_sendmsg: + + return -(RT_ERROR); +} + +static int nu_canfd_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + CANFD_RX_BUF_T sRxMsg; + struct rt_can_msg *pmsg; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + RT_ASSERT(buf); + + /* get data */ + if (CANFD_Transfer(psNuCANFD->base, eCANFD_MSG_RF0, &sRxMsg, 0) == NULL) + { + rt_kprintf("No available RX Msg.\n"); + return -(RT_ERROR); + } + + pmsg = (struct rt_can_msg *) buf; +#if defined(RT_CAN_USING_HDR) + /* Hardware filter messages are valid */ + pmsg->hdr_index = boxno; + can->hdr[pmsg->hdr_index].connected = 1; +#endif + + pmsg->ide = (sRxMsg.XTD) ? RT_CAN_EXTID : RT_CAN_STDID; + if (pmsg->ide == RT_CAN_EXTID) + { + pmsg->id = sRxMsg.ID; + } + else + { + pmsg->id = CANFD_GET_SID(sRxMsg.ID); + } + + pmsg->rtr = (sRxMsg.RTR) ? RT_CAN_RTR : RT_CAN_DTR; + pmsg->len = CANFD_DecodeDLC(sRxMsg.DLC); + + if (pmsg->len > 0) + rt_memcpy(&pmsg->data[0], &sRxMsg.DB[0], pmsg->len); + + return RT_EOK; +} + +/** + * Hardware CAN Initialization + */ +static int rt_hw_canfd_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (CANFD_START + 1); i < CANFD_CNT; i++) + { + nu_canfd_arr[i].dev.config = nu_canfd_default_config; +#if defined(RT_CAN_USING_HDR) + nu_canfd_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ; +#endif + /* Register can device */ + ret = rt_hw_can_register(&nu_canfd_arr[i].dev, nu_canfd_arr[i].name, &nu_canfd_ops, NULL); + RT_ASSERT(ret == RT_EOK); + + /* Unmask interrupt. */ + NVIC_EnableIRQ(nu_canfd_arr[i].irqn0); + NVIC_EnableIRQ(nu_canfd_arr[i].irqn1); + } + + return (int)ret; +} +INIT_DEVICE_EXPORT(rt_hw_canfd_init); + +#endif //#if defined(BSP_USING_CANFD) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c new file mode 100644 index 00000000000..e4b18ce378c --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c @@ -0,0 +1,356 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_CLK) + +#include "NuMicro.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.clk" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* pm run mode speed mapping */ +#define CONFIG_HIGH_SPEED_FREQ (__HSI) +#define CONFIG_NORMAL_SPEED_FREQ (__HSI) +#define CONFIG_MEDIMUM_SPEED_FREQ (__HSI/2) +#define CONFIG_LOW_SPEED_FREQ (__HSI/2) + +/* pm sleep mode mapping */ +#define CONFIG_MODE_LIGHT (CLK_PMUCTL_PDMSEL_FWPD) +#define CONFIG_MODE_DEEP (CLK_PMUCTL_PDMSEL_NPD) +#define CONFIG_MODE_STANDBY (CLK_PMUCTL_PDMSEL_SPD) +#define CONFIG_MODE_SHUTDOWN (CLK_PMUCTL_PDMSEL_DPD) +#if defined (NU_CLK_INVOKE_WKTMR) + /* The Wake-up Timer Time-out Interval selection. It could be + * CLK_PMUCTL_WKTMRIS_512 - Select Wake-up Timer Time-out Interval is 512 LIRC clocks (16 ms) + * CLK_PMUCTL_WKTMRIS_1024 - Select Wake-up Timer Time-out Interval is 1204 LIRC clocks (32 ms) + * CLK_PMUCTL_WKTMRIS_2048 - Select Wake-up Timer Time-out Interval is 2048 LIRC clocks (64 ms) + * CLK_PMUCTL_WKTMRIS_4096 - Select Wake-up Timer Time-out Interval is 4096 LIRC clocks (128 ms) + * CLK_PMUCTL_WKTMRIS_8192 - Select Wake-up Timer Time-out Interval is 8192 LIRC clocks (256 ms) + * CLK_PMUCTL_WKTMRIS_16384 - Select Wake-up Timer Time-out Interval is 16384 LIRC clocks (512 ms) + * CLK_PMUCTL_WKTMRIS_32768 - Select Wake-up Timer Time-out Interval is 32768 LIRC clocks (1024 ms) + * CLK_PMUCTL_WKTMRIS_65536 - Select Wake-up Timer Time-out Interval is 65536 LIRC clocks (2048 ms) + * CLK_PMUCTL_WKTMRIS_131072 - Select Wake-up Timer Time-out Interval is 131072 LIRC clocks (4096 ms) + * CLK_PMUCTL_WKTMRIS_262144 - Select Wake-up Timer Time-out Interval is 262144 LIRC clocks (8192 ms) + * CLK_PMUCTL_WKTMRIS_524288 - Select Wake-up Timer Time-out Interval is 524288 LIRC clocks (16384 ms) + * CLK_PMUCTL_WKTMRIS_1048576 - Select Wake-up Timer Time-out Interval is 1048576 LIRC clocks (32768 ms) + * CLK_PMUCTL_WKTMRIS_2097152 - Select Wake-up Timer Time-out Interval is 2097152 LIRC clocks (65536 ms) + * CLK_PMUCTL_WKTMRIS_4194304 - Select Wake-up Timer Time-out Interval is 4194304 LIRC clocks (131072 ms) + */ +#define WKTMR_INTERVAL (CLK_PMUCTL_WKTMRIS_131072) +#endif + +/* Timer module assigned for pm device usage. */ +/* e.g. If TIMERn is reserved for pm, then define the PM_TIMER_USE_INSTANCE + macro to n value (without parentheses). */ +#define PM_TIMER_USE_INSTANCE 3 + +/* Concatenate */ +#define _CONCAT2_(x, y) x##y +#define _CONCAT3_(x, y, z) x##y##z +#define CONCAT2(x, y) _CONCAT2_(x, y) +#define CONCAT3(x, y, z) _CONCAT3_(x, y, z) + +/* Concatenate the macros of timer instance for driver usage. */ +#define PM_TIMER CONCAT2(TIMER, PM_TIMER_USE_INSTANCE) +#define PM_TMR CONCAT2(TMR, PM_TIMER_USE_INSTANCE) +#define PM_TIMER_MODULE CONCAT2(PM_TMR, _MODULE) +#define PM_TIMER_IRQn CONCAT2(PM_TMR, _IRQn) +#define PM_TIMER_IRQHandler CONCAT2(PM_TMR, _IRQHandler) +#define PM_TIMER_SEL_LXT CONCAT3(CLK_CLKSEL1_, PM_TMR, SEL_LXT) + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode); +static void pm_run(struct rt_pm *pm, rt_uint8_t mode); +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout); +static void pm_timer_stop(struct rt_pm *pm); +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm); +static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick); +static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick); +int rt_hw_pm_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_pm_ops ops = +{ + .sleep = pm_sleep, + .run = pm_run, + .timer_start = pm_timer_start, + .timer_stop = pm_timer_stop, + .timer_get_tick = pm_timer_get_tick, +}; + +/* Sleep and power-down mapping */ +static const uint32_t g_au32SleepingMode[PM_SLEEP_MODE_MAX] = +{ + 0, + 0, + CONFIG_MODE_LIGHT, + CONFIG_MODE_DEEP, + CONFIG_MODE_STANDBY, + CONFIG_MODE_SHUTDOWN +}; + +/* Functions Implementation --------------------------------------------------*/ + +rt_weak void pm_get_wksrc(void) +{ + uint32_t u32RegRstsrc; + + if ((u32RegRstsrc = CLK_GetPMUWKSrc()) != 0) + { + /* Release I/O hold status after wake-up from Standby Power-down Mode (SPD) */ + CLK->IOPDCTL = 1; + + rt_kprintf("CLK_PMUSTS: 0x%08X\n", u32RegRstsrc); + + /* Clear Power Manager Status register */ + CLK->PMUSTS = CLK_PMUSTS_CLRWK_Msk; + } +} + +rt_weak void pm_set_wksrc(rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_STANDBY: + /* FALLTHROUGH */ + case PM_SLEEP_MODE_SHUTDOWN: +#if defined (NU_CLK_INVOKE_WKTMR) + /* Enable wake-up timer with pre-defined interval if it is invoked */ + CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL); + CLK_ENABLE_WKTMR(); +#elif defined(BSP_USING_RTC) + /* Enable RTC wake-up. */ + CLK_ENABLE_RTCWK(); +#endif + default: + return; + } +} + +rt_weak void pm_sleep_before(rt_uint8_t mode) +{ +} + +rt_weak void pm_sleep_after(rt_uint8_t mode) +{ +} +static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode) +{ + RT_ASSERT(mode < PM_SLEEP_MODE_MAX); + + /* wake-up source: */ + /* PM_SLEEP_MODE_LIGHT : TIMERn */ + /* PM_SLEEP_MODE_DEEP : TIMERn */ + /* PM_SLEEP_MODE_STANDBY : wake-up timer (optional) */ + /* PM_SLEEP_MODE_SHUTDOWN : wake-up timer (optional) */ + + switch (mode) + { + case PM_SLEEP_MODE_STANDBY: + /* Standby mode, CPU stops, device context loss (can be saved to special peripherals), + usually reset after wake-up */ + + /* FALLTHROUGH */ + + case PM_SLEEP_MODE_SHUTDOWN: + /* Shutdown mode, lower power consumption than Standby mode, context is usually irrecoverable, reset after wake-up */ + + /* FALLTHROUGH */ + + case PM_SLEEP_MODE_LIGHT: + /* Light sleep modes, CPU stops, most clocks and peripherals stop, and time compensation is required after wake-up. */ + + /* FALLTHROUGH */ + + case PM_SLEEP_MODE_DEEP: + /* Deep sleep mode, CPU stops, only a few low power peripheral work, can be awakened by special interrupts */ + + pm_set_wksrc(mode); + + break; + + case PM_SLEEP_MODE_IDLE: + /* The idle mode, which stops CPU and part of the clock when the system is idle. Any event or interrupt can wake up system. */ + CLK_Idle(); + + /* FALLTHROUGH */ + + case PM_SLEEP_MODE_NONE: + /* The system is active without any power reduction. */ + + default: + return; + } + pm_sleep_before(mode); + + /* Flush TX FIFO of default console UART. */ + if (rt_console_get_device()) + rt_device_control(rt_console_get_device(), 9527, 0); + + /* Set Power-down Mode */ + CLK_SetPowerDownMode(g_au32SleepingMode[mode]); + + /* Here, take a break. */ + CLK_PowerDown(); + + /* Do something after wakeup. */ + pm_sleep_after(mode); +} +static void pm_run(struct rt_pm *pm, rt_uint8_t mode) +{ + static uint8_t prev_mode = RT_PM_DEFAULT_RUN_MODE; + + /* ignore it if power mode is the same. */ + if (mode == prev_mode) + return; + + prev_mode = mode; + + /* Switch run mode frequency using PLL + HXT if HXT is enabled. + Otherwise, the system clock will use PLL + HIRC. */ + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + + LOG_I("Set CPU frequency to %d!!!", CONFIG_HIGH_SPEED_FREQ); + CLK_SetCoreClock(CONFIG_HIGH_SPEED_FREQ); + break; + + case PM_RUN_MODE_NORMAL_SPEED: + + LOG_I("Set CPU frequency to %d!!!", CONFIG_NORMAL_SPEED_FREQ); + CLK_SetCoreClock(CONFIG_NORMAL_SPEED_FREQ); + break; + + case PM_RUN_MODE_MEDIUM_SPEED: + + LOG_I("Set CPU frequency to %d!!!", CONFIG_MEDIMUM_SPEED_FREQ); + CLK_SetCoreClock(CONFIG_MEDIMUM_SPEED_FREQ); + break; + + case PM_RUN_MODE_LOW_SPEED: + + LOG_I("Set CPU frequency to %d!!!", CONFIG_LOW_SPEED_FREQ); + CLK_SetCoreClock(CONFIG_LOW_SPEED_FREQ); + break; + + default: + return; + } + + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + LOG_I("Current HCLK/CPU/PCLK0/PCLK1 frequency are %d/%d/%d/%d!!!", + CLK_GetHCLKFreq(), + CLK_GetCPUFreq(), + CLK_GetPCLK0Freq(), + CLK_GetPCLK1Freq()); +} + +static void hw_timer_init(void) +{ + /* Assign a hardware timer for pm usage. */ + CLK_SetModuleClock(PM_TIMER_MODULE, PM_TIMER_SEL_LXT, MODULE_NoMsk); + CLK_EnableModuleClock(PM_TIMER_MODULE); + + /* Initialize timer and enable wakeup function. */ + TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1); + TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0); + TIMER_EnableInt(PM_TIMER); + TIMER_EnableWakeup(PM_TIMER); + NVIC_EnableIRQ(PM_TIMER_IRQn); +} +static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick) +{ + rt_uint32_t hz = TIMER_GetModuleClock(PM_TIMER); + + return (rt_tick_t)(hz * os_tick / RT_TICK_PER_SECOND); +} +static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, hz; + + hz = TIMER_GetModuleClock(PM_TIMER); + ret = (pm_tick * RT_TICK_PER_SECOND + os_tick_remain) / hz; + + os_tick_remain += (pm_tick * RT_TICK_PER_SECOND); + os_tick_remain %= hz; + + return ret; +} +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_tick_t tick = TIMER_GetCounter(PM_TIMER); + + return os_tick_from_pm_tick(tick); +} +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + int tick; + + if (timeout == RT_TICK_MAX) + return; + + /* start pm timer to compensate the os tick in power down mode */ + tick = pm_tick_from_os_tick(timeout); + TIMER_SET_CMP_VALUE(PM_TIMER, tick); + TIMER_Start(PM_TIMER); +} +static void pm_timer_stop(struct rt_pm *pm) +{ + TIMER_Stop(PM_TIMER); + TIMER_ResetCounter(PM_TIMER); +} +int rt_hw_pm_init(void) +{ + rt_uint8_t timer_mask; + + pm_get_wksrc(); + + hw_timer_init(); + + /* Set the bit corresponding to Deep Sleep mode to enable sleep time compensation */ + timer_mask = (1UL << PM_SLEEP_MODE_LIGHT) | (1UL << PM_SLEEP_MODE_DEEP); + + /* initialize system pm module */ + rt_system_pm_init(&ops, timer_mask, RT_NULL); + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_pm_init); + +extern void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode); +void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode) +{ + if ((sleep_mode == PM_SLEEP_MODE_LIGHT) || (sleep_mode == PM_SLEEP_MODE_DEEP)) + { + if (TIMER_GetIntFlag(PM_TIMER)) + { + TIMER_ClearIntFlag(PM_TIMER); + } + + if (TIMER_GetWakeupFlag(PM_TIMER)) + { + TIMER_ClearWakeupFlag(PM_TIMER); + } + + NVIC_ClearPendingIRQ(PM_TIMER_IRQn); + } + + rt_hw_interrupt_enable(ctx); +} +#endif /* BSP_USING_CLK */ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c new file mode 100644 index 00000000000..4b01e2a2e6f --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c @@ -0,0 +1,271 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "NuMicro.h" +#include "board.h" +#include "drv_common.h" +#include "drv_uart.h" +#include +#include "rtthread.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.common" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ + +/* Static Variables ----------------------------------------------------------*/ + +/* Functions Implementation --------------------------------------------------*/ +/** + * This function will initial. + */ +rt_weak void rt_hw_board_init(void) +{ + /* Init System/modules clock */ + void nutool_modclkcfg_init(); + nutool_modclkcfg_init(); + + /* Init all pin function setting */ + void nutool_pincfg_init(void); + nutool_pincfg_init(); + + /* Configure SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); +#if defined(RT_USING_HEAP) + rt_system_heap_init(HEAP_BEGIN, HEAP_END); +#endif /* RT_USING_HEAP */ +#if defined(BSP_USING_UART) + rt_hw_uart_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#if defined(RT_USING_COMPONENTS_INIT) + rt_components_board_init(); +#endif +} + +/** + * The time delay function. + * + * @param microseconds. + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +void nu_pin_func(rt_base_t pin, int data) +{ + uint32_t GPx_MFPx_org; + uint32_t pin_index = NU_GET_PINS(pin); + uint32_t port_index = NU_GET_PORT(pin); + __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFP0) + port_index * 4 + (pin_index / 4); + uint32_t MFP_Msk = NU_MFP_MSK(pin_index); + + GPx_MFPx_org = *GPx_MFPx; + *GPx_MFPx = (GPx_MFPx_org & (~MFP_Msk)) | data; + + //rt_kprintf("Port[%d]-Pin[%d] Addr[%08x] Data[%08x] %08x -> %08x\n", port_index, pin_index, GPx_MFPx, data, GPx_MFPx_org, *GPx_MFPx); +} + +void nu_read_uid(uint32_t *id) +{ + /* Enable FMC ISP function */ + FMC_Open(); + + /* Read Unique ID */ + id[0] = FMC_ReadUID(0); + id[1] = FMC_ReadUID(1); + id[2] = FMC_ReadUID(2); + id[3] = 0; + + /* Disable FMC ISP function */ + FMC_Close(); + +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int reboot(int argc, char **argv) +{ + SYS_UnlockReg(); + + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; + + return 0; +} +MSH_CMD_EXPORT(reboot, Reboot System); +#if defined(RT_USING_SPI) +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t ret = RT_EOK; + struct rt_spi_device *spi_device = (struct rt_spi_device *) +rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + rt_uint32_t *cs_pin = (rt_uint32_t *) +rt_malloc(sizeof(rt_uint32_t)); + RT_ASSERT(cs_pin != RT_NULL); + + *cs_pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + RT_ASSERT(ret == RT_EOK); + + return ret; +} +#endif + +void devmem(int argc, char *argv[]) +{ + /** + * @brief This function may interact with critical system registers. Use with caution. + * + * @details + * This function has the potential to access and modify important system registers + * as part of its operation. Ensure proper validation and system state checks + * before calling this function. Improper or careless usage may lead to system + * instability or unintended behavior. + */ + volatile unsigned int u32Addr; + unsigned int value = 0, mode = 0; + + if (argc < 2 || argc > 3) + { + goto exit_devmem; + } + + if (argc == 3) + { + if (sscanf(argv[2], "0x%x", &value) != 1) + goto exit_devmem; + mode = 1; //Write + } + + if (sscanf(argv[1], "0x%x", &u32Addr) != 1) + goto exit_devmem; + else if (!u32Addr || u32Addr & (4 - 1)) + goto exit_devmem; + + if (mode) + { + *((volatile uint32_t *)u32Addr) = value; + } + rt_kprintf("0x%08x\n", *((volatile uint32_t *)u32Addr)); + + return; +exit_devmem: + rt_kprintf("Read: devmem \n"); + rt_kprintf("Write: devmem \n"); + return; +} +MSH_CMD_EXPORT(devmem, dump device registers); + +#if defined(RT_USING_ULOG) +void devmem2(int argc, char *argv[]) +{ + /** + * @brief This function may interact with critical system registers. Use with caution. + * + * @details + * This function has the potential to access and modify important system registers + * as part of its operation. Ensure proper validation and system state checks + * before calling this function. Improper or careless usage may lead to system + * instability or unintended behavior. + */ + + volatile unsigned int u32Addr; + unsigned int value = 0, word_count = 1; + + if (argc < 2 || argc > 3) + { + goto exit_devmem; + } + + if (argc == 3) + { + if (sscanf(argv[2], "%d", &value) != 1) + goto exit_devmem; + word_count = value; + } + + if (sscanf(argv[1], "0x%x", &u32Addr) != 1) + goto exit_devmem; + else if (!u32Addr || u32Addr & (4 - 1)) + goto exit_devmem; + + if (word_count > 0) + { + LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t)); + } + + return; +exit_devmem: + rt_kprintf("devmem2: \n"); + return; +} +MSH_CMD_EXPORT(devmem2, dump device registers); +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.h new file mode 100644 index 00000000000..605b259b1d9 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.h @@ -0,0 +1,36 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include "NuMicro.h" +#include "rtthread.h" +#include "drv_gpio.h" + +#define NU_MFP_POS(PIN) ((PIN % 4) * 8) +#define NU_MFP_MSK(PIN) (0x1ful << NU_MFP_POS(PIN)) + +#define STR2(x) #x +#define STR(x) STR2(x) +#define INCBIN(name, file) \ + __asm__(".section .rodata\n" \ + ".global incbin_" STR(name) "_start\n" \ + ".balign 16\n" \ + "incbin_" STR(name) "_start:\n" \ + ".incbin \"" file "\"\n" \ + \ + ".global incbin_" STR(name) "_end\n" \ + ".balign 1\n" \ + "incbin_" STR(name) "_end:\n" \ + ".byte 0\n" \ + ); \ + extern const __attribute__((aligned(32))) void* incbin_ ## name ## _start; \ + extern const void* incbin_ ## name ## _end; + +void nu_pin_func(rt_base_t pin, int data); + +#endif /* __DRV_COMMON_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c new file mode 100644 index 00000000000..6ec19a5ef20 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c @@ -0,0 +1,231 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_CRC) + +#include "NuMicro.h" +#include "drv_crc.h" +#include "drv_pdma.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.crc" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define NU_CRYPTO_CRC_NAME "nu_crc" +#define CRC_32_POLY 0x04C11DB7 +#define CRC_CCITT_POLY 0x00001021 +#define CRC_16_POLY 0x00008005 +#define CRC_8_POLY 0x00000007 + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_uint32_t nu_crc_run(uint32_t u32OpMode, + uint32_t u32Seed, + uint32_t u32Attr, + uint8_t *pu8InData, + uint32_t u32DataLen); + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_mutex s_CRC_mutex; + +/* Functions Implementation --------------------------------------------------*/ +void CRC_IRQHandler(void) +{ + uint32_t u32CRCDMAStatus; + + /* enter interrupt */ + rt_interrupt_enter(); + + u32CRCDMAStatus = CRC_GET_DMA_STATUS(); + CRC->DMASTS = u32CRCDMAStatus; + + if (u32CRCDMAStatus & CRC_DMASTS_FINISH_Msk) + rt_kprintf("\tIRQ - CRC DMA Finish\n\n"); + + if (u32CRCDMAStatus & CRC_DMASTS_ABORTED_Msk) + rt_kprintf("\tIRQ - CRC DMA Abort\n"); + + if (u32CRCDMAStatus & CRC_DMASTS_CFGERR_Msk) + rt_kprintf("\tIRQ - CRC DMA CFG Error\n\n"); + + if (u32CRCDMAStatus & CRC_DMASTS_ACCERR_Msk) + rt_kprintf("\tIRQ - CRC DMA Access Error\n\n"); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * @brief Run CRC calculation on input data buffer. + * @param u32OpMode: CRC operation mode (CRC_32, CRC_CCITT, etc.) + * @param u32Seed: Initial CRC seed value + * @param u32Attr: CRC attribute flags (reverse, etc.) + * @param pu8InData: Pointer to input data buffer + * @param u32DataLen: Length of input data in bytes + * @return Calculated CRC checksum + */ +static rt_uint32_t nu_crc_run( + uint32_t u32OpMode, + uint32_t u32Seed, + uint32_t u32Attr, + uint8_t *pu8InData, + uint32_t u32DataLen) + { + uint32_t u32CalChecksum = 0; + uint32_t i = 0; + rt_err_t result; + + // Take mutex to ensure exclusive access to CRC hardware + result = rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + // Configure CRC controller + CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8); + + uint8_t *pu8InTempData = pu8InData; + + while (i < u32DataLen) + { + // If address is not 4-byte aligned or less than 4 bytes left, write byte-by-byte + if ((((uintptr_t)pu8InTempData) % 4 != 0) || (u32DataLen - i < 4)) + { + CRC->CTL &= ~CRC_CTL_DATLEN_Msk; + CRC_WRITE_DATA((*pu8InTempData) & 0xFF); + pu8InTempData++; + i++; + } + else + { + CRC->CTL &= ~CRC_CTL_DATLEN_Msk; + CRC->CTL |= CRC_CPU_WDATA_32; +#if defined (NU_CRC_USE_DEDICATED_DMA) + // Use Dedicated DMA for efficient transfer if enabled + int32_t i32Remain = (u32DataLen - i); + int32_t i32Remain_WordAligned = i32Remain & ~0x3; + + uint32_t u32CRCDMAStatus = 0; + + /* Enable CRC IRQ */ + //NVIC_EnableIRQ(CRC_IRQn); + + CRC_ENABLE_DMA_INT(); + + CRC_SET_DMA_SADDR((uint32_t)pu8InTempData); + CRC_SET_DMA_SIZE(i32Remain_WordAligned); + CRC_DMA_START(); + + while ((u32CRCDMAStatus = CRC_GET_DMA_STATUS()) == 0); + CRC->DMASTS = u32CRCDMAStatus; + + if (u32CRCDMAStatus != CRC_DMASTS_FINISH_Msk) + { + rt_kprintf("CRC DMA Address@0x%08X\n", (uint32_t)pu8InTempData); + rt_kprintf("CRC DMA Length: %d\n", (uint32_t)i32Remain_WordAligned); + + if (u32CRCDMAStatus & CRC_DMASTS_ABORTED_Msk) + rt_kprintf("CRC DMA Abort\n"); + + if (u32CRCDMAStatus & CRC_DMASTS_CFGERR_Msk) + rt_kprintf("CRC DMA CFG Error\n"); + + if (u32CRCDMAStatus & CRC_DMASTS_ACCERR_Msk) + rt_kprintf("CRC DMA Access Error\n"); + } + else + { + pu8InTempData += (i32Remain_WordAligned); + i += (i32Remain_WordAligned); + } +#elif defined (NU_CRC_USE_PDMA) + // Use PDMA for efficient transfer if enabled + int32_t i32DMATransCnt = (u32DataLen - i) / 4; + i32DMATransCnt = nu_pdma_mempush((void *)&CRC->DAT, pu8InTempData, 32, i32DMATransCnt); + if (i32DMATransCnt > 0) + { + pu8InTempData += (i32DMATransCnt * 4); + i += (i32DMATransCnt * 4); + } +#else + // Write 4 bytes at a time + CRC_WRITE_DATA(*(uint32_t *)pu8InTempData); + pu8InTempData += 4; + i += 4; +#endif + } + } + u32CalChecksum = CRC_GetChecksum(); + + // Release mutex + result = rt_mutex_release(&s_CRC_mutex); + RT_ASSERT(result == RT_EOK); + + return u32CalChecksum; +} + +/** + * @brief Initialize CRC hardware and mutex. + * @return RT_EOK on success, error code otherwise. + */ +rt_err_t nu_crc_init(void) +{ + SYS_ResetModule(CRC_RST); + return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO); +} + +/** + * @brief Update CRC calculation with new data. + * @param ctx: Pointer to CRC context/config structure + * @param in: Pointer to input data buffer + * @param length: Length of input data in bytes + * @return Calculated CRC checksum + */ +rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) +{ + uint32_t u32OpMode; + uint32_t u32CRCAttr = 0; + rt_uint32_t crc_result = 0; + + // Select CRC operation mode based on polynomial + switch (ctx->crc_cfg.poly) + { + case CRC_32_POLY: + u32OpMode = CRC_32; + break; + case CRC_CCITT_POLY: + u32OpMode = CRC_CCITT; + break; + case CRC_16_POLY: + u32OpMode = CRC_16; + break; + case CRC_8_POLY: + u32OpMode = CRC_8; + break; + default: + LOG_E("Unsupported CRC polynomial: 0x%08X", ctx->crc_cfg.poly); + return 0; + } + + if (ctx->crc_cfg.flags & CRC_FLAG_REFOUT) + u32CRCAttr |= CRC_CHECKSUM_RVS; // CRC Checksum Reverse + + if (ctx->crc_cfg.flags & CRC_FLAG_REFIN) + u32CRCAttr |= CRC_WDATA_RVS; // CRC Write Data Reverse + + // Calculate CRC checksum, using config's last value as CRC seed + crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length); + + // Update CRC result to config's last value for possible chained calls + ctx->crc_cfg.last_val = crc_result; + + // Apply xorout (final xor value) + return crc_result ^ ctx->crc_cfg.xorout; +} +#endif //#if defined(BSP_USING_CRC) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.h new file mode 100644 index 00000000000..a9f511f6c58 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.h @@ -0,0 +1,19 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_CRC_H__ +#define __DRV_CRC_H__ + +#include "rtdevice.h" + +#define CRC_FLAG_REFIN (0x1 << 0) +#define CRC_FLAG_REFOUT (0x1 << 1) + +rt_err_t nu_crc_init(void); + +rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length); + +#endif /* __DRV_CRC_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crypto.c new file mode 100644 index 00000000000..95e927733a7 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crypto.c @@ -0,0 +1,147 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_CRYPTO) && defined(RT_USING_HWCRYPTO) + +#include "NuMicro.h" +#include "drv_crc.h" +#include "nu_bitutil.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.crypto" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx); +static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx); +static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src); +static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx); + +/* Static Variables ----------------------------------------------------------*/ +static const struct rt_hwcrypto_ops nu_hwcrypto_ops = +{ + .create = nu_hwcrypto_create, + .destroy = nu_hwcrypto_destroy, + .copy = nu_hwcrypto_clone, + .reset = nu_hwcrypto_reset, +}; +#if defined(BSP_USING_CRC) +static const struct hwcrypto_crc_ops nu_crc_ops = +{ + .update = nu_crc_update, +}; +#endif + +/* Functions Implementation --------------------------------------------------*/ + +/* + * @brief Create and initialize a hardware crypto context. + * @param ctx: Pointer to hardware crypto context + * @return RT_EOK on success, negative error code otherwise + */ +static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx) +{ + RT_ASSERT(ctx != RT_NULL); + + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC) + case HWCRYPTO_TYPE_CRC: + ctx->contex = RT_NULL; + // Set CRC operation handlers + ((struct hwcrypto_crc *)ctx)->ops = &nu_crc_ops; + break; +#endif + default: + LOG_E("Unsupported crypto type: 0x%08X", ctx->type); + return -RT_ERROR; + } + + nu_hwcrypto_reset(ctx); + + return RT_EOK; +} + +/* + * @brief Destroy a hardware crypto context and free resources. + * @param ctx: Pointer to hardware crypto context + */ +static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx) +{ + RT_ASSERT(ctx != RT_NULL); + if (ctx->contex) + { + rt_free(ctx->contex); + ctx->contex = RT_NULL; + } +} + +/* + * @brief Clone (copy) a hardware crypto context. + * @param des: Destination context + * @param src: Source context + * @return RT_EOK on success, negative error code otherwise + */ +static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) +{ + RT_ASSERT(des != RT_NULL); + RT_ASSERT(src != RT_NULL); + + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(struct rt_hwcrypto_ctx)); + return RT_EOK; + } + + return -RT_EINVAL; +} + +/* + * @brief Reset a hardware crypto context (currently a stub). + * @param ctx: Pointer to hardware crypto context + */ +static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx) +{ + RT_ASSERT(ctx != RT_NULL); + // Add per-type reset logic if needed in the future + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { + default: + break; + } +} + +/* + * @brief Initialize and register the Nuvoton hardware crypto device. + * @return 0 on success + */ +int nu_hwcrypto_device_init(void) +{ + rt_err_t result; + static struct rt_hwcrypto_device nu_hwcrypto_dev; + + nu_hwcrypto_dev.ops = &nu_hwcrypto_ops; + nu_hwcrypto_dev.id = 0; + nu_hwcrypto_dev.user_data = &nu_hwcrypto_dev; +#if defined(BSP_USING_CRC) + nu_crc_init(); +#endif + + // Register hardware crypto device + result = rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME); + RT_ASSERT(result == RT_EOK); + + return 0; +} +INIT_DEVICE_EXPORT(nu_hwcrypto_device_init); +#endif //#if defined(BSP_USING_CRYPTO) && defined(RT_USING_HWCRYPTO) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eadc.c new file mode 100644 index 00000000000..171b5685b7d --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eadc.c @@ -0,0 +1,303 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_EADC) + +#include "NuMicro.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.eadc" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define CONFIG_MAX_CHN_NUM EADC_CH_NUM +#define DEFINE_NU_EADC(_idx) \ + { \ + .name = "eadc" #_idx, \ + .base = EADC##_idx, \ + .conv_power = 1, \ + .chn_msk = 0, \ + .max_chn_num = CONFIG_MAX_CHN_NUM, \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + EADC_START = -1, +#if defined(BSP_USING_EADC0) && defined(EADC0) + EADC0_IDX, +#endif + EADC_CNT +}; + +enum +{ + EADC_CH_0, + EADC_CH_1, + EADC_CH_2, + EADC_CH_3, + EADC_CH_4, + EADC_CH_5, + EADC_CH_6, + EADC_CH_7, + EADC_CH_8, + EADC_CH_9, + EADC_CH_10, + EADC_CH_11, + EADC_CH_12, + EADC_CH_13, + EADC_CH_14, + EADC_CH_15, + EADC_CH_VBG, // 16, Band-gap voltage + EADC_CH_VTEMP, // 17, Internal Temperature sensor + EADC_CH_AVDD_DIV4, // 18, AVDD/4 + EADC_CH_NUM +}; + +struct nu_eadc +{ + struct rt_adc_device dev; + char *name; + EADC_T *base; + uint32_t conv_power; + uint32_t chn_msk; + uint32_t max_chn_num; +}; +typedef struct nu_eadc *nu_eadc_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled); +static rt_err_t nu_eadc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value); +static rt_uint8_t nu_eadc_get_resolution(struct rt_adc_device *device); +static rt_int16_t nu_eadc_get_vref(struct rt_adc_device *device); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_eadc nu_eadc_arr [] = +{ +#if defined(BSP_USING_EADC0) && defined(EADC0) + DEFINE_NU_EADC(0), +#endif +}; + +static const struct rt_adc_ops nu_adc_ops = +{ + .enabled = nu_eadc_enabled, + .convert = nu_eadc_convert, + .get_resolution = nu_eadc_get_resolution, + .get_vref = nu_eadc_get_vref +}; +typedef struct rt_adc_ops *rt_adc_ops_t; + +static rt_uint32_t s_u32BuiltInBandGapValue = 0; + +/* Functions Implementation --------------------------------------------------*/ +static rt_uint8_t nu_eadc_get_resolution(struct rt_adc_device *device) +{ + return 12; /* 12-bit */ +} + +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ + nu_eadc_t psNuEADC = (nu_eadc_t)device; + + RT_ASSERT(device); + + if (channel >= psNuEADC->max_chn_num) + return -(RT_EINVAL); + + if (enabled) + { + if (psNuEADC->chn_msk == 0) + { + EADC_Open(psNuEADC->base, EADC_CTL_DIFFEN_SINGLE_END); + } + + switch (channel) + { + case EADC_CH_AVDD_DIV4: + /* Enable AVDD/4 */ + SYS->IVSCTL |= SYS_IVSCTL_AVDDDIV4EN_Msk; + break; + + case EADC_CH_VBG: + /* Force to enable internal voltage band-gap. */ + SYS->VREFCTL |= SYS_VREFCTL_VBGFEN_Msk; + break; + + case EADC_CH_VTEMP: + /* Enable temperature sensor */ + SYS->IVSCTL |= SYS_IVSCTL_VTEMPEN_Msk; + break; + + default: + break; + } + + psNuEADC->chn_msk |= (0x1 << channel); + } + else + { + psNuEADC->chn_msk &= ~(0x1 << channel); + + switch (channel) + { + case EADC_CH_AVDD_DIV4: + /* Disable AVDD/4 */ + SYS->IVSCTL &= ~SYS_IVSCTL_AVDDDIV4EN_Msk; + break; + + case EADC_CH_VBG: + /* Force to enable internal voltage band-gap. */ + SYS->VREFCTL &= ~SYS_VREFCTL_VBGFEN_Msk; + break; + + case EADC_CH_VTEMP: + /* Disable temperature sensor */ + SYS->IVSCTL &= ~SYS_IVSCTL_VTEMPEN_Msk; + break; + + default: + break; + } + + if (psNuEADC->chn_msk == 0) + { + EADC_Close(psNuEADC->base); + } + } + + return RT_EOK; +} + +static rt_uint32_t _eadc_convert(nu_eadc_t psNuEADC, rt_uint32_t channel) +{ +#define CONFIG_CONV_INTSEL 0 +#define CONFIG_EXT_SMPL_TIME 0xff +#define CONFIG_SMPL_MODULE_ACU_TIMES (psNuEADC->conv_power << EADC_MCTL1_ACU_Pos) + + rt_uint32_t u32ConvValue, u32ModuleNum; + + if (nu_eadc_enabled((struct rt_adc_device *)psNuEADC, channel, RT_TRUE) != RT_EOK) + { + return 0xFFFFFFFF; + } + + u32ModuleNum = channel; + + /* Configure the sample module for analog input channel and software trigger source. */ + EADC_ConfigSampleModule(psNuEADC->base, u32ModuleNum, EADC_SOFTWARE_TRIGGER, channel); + + /* Set sample module external sampling time to 0xF */ + EADC_SetExtendSampleTime(psNuEADC->base, u32ModuleNum, CONFIG_EXT_SMPL_TIME); + + /* Enable Accumulate feature */ + EADC_ENABLE_ACU(psNuEADC->base, u32ModuleNum, CONFIG_SMPL_MODULE_ACU_TIMES); + + /* Enable Average feature */ + EADC_ENABLE_AVG(psNuEADC->base, u32ModuleNum); + + /* Clear the A/D ADINT0 interrupt flag for safe */ + EADC_CLR_INT_FLAG(psNuEADC->base, EADC_STATUS2_ADIF0_Msk); + + /* Enable the sample module interrupt. */ + EADC_ENABLE_INT(psNuEADC->base, (1 << CONFIG_CONV_INTSEL)); + EADC_ENABLE_SAMPLE_MODULE_INT(psNuEADC->base, CONFIG_CONV_INTSEL, (1 << u32ModuleNum)); + + EADC_START_CONV(psNuEADC->base, (1 << u32ModuleNum)); + while (EADC_GET_INT_FLAG(psNuEADC->base, (1 << CONFIG_CONV_INTSEL)) == 0); + + /* Disable the sample module interrupt. */ + EADC_DISABLE_INT(psNuEADC->base, (1 << CONFIG_CONV_INTSEL)); + + /* Disable Average feature */ + EADC_DISABLE_AVG(psNuEADC->base, u32ModuleNum); + + /* Disable Accumulate feature */ + EADC_DISABLE_ACU(psNuEADC->base, u32ModuleNum); + + u32ConvValue = EADC_GET_CONV_DATA(psNuEADC->base, u32ModuleNum); + + //rt_kprintf("u32ConvValue: %08x\n", u32ConvValue); + + return u32ConvValue; +} + +static rt_int16_t nu_eadc_get_vref(struct rt_adc_device *device) +{ + rt_uint32_t u32VBG; + + RT_ASSERT(device); + + u32VBG = _eadc_convert((nu_eadc_t)device, EADC_CH_VBG); // VBG Channel + + /* Use Conversion result of Band-gap to calculating AVdd */ + /* + u16Vref s_u32BuiltInBandGapValue + ---------- = ------------------------- + 3072 i32ConversionData + */ + // rt_kprintf("u32VBG: %d, AVDD: %d\n", u32VBG, 3072 * s_u32BuiltInBandGapValue / u32VBG); + + return (3072 * s_u32BuiltInBandGapValue / u32VBG); +} + +static rt_err_t nu_eadc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) +{ + nu_eadc_t psNuEADC = (nu_eadc_t)device; + rt_err_t ret = RT_ERROR; + + RT_ASSERT(device); + RT_ASSERT(value); + + if (channel >= psNuEADC->max_chn_num) + { + *value = 0xFFFFFFFF; + ret = RT_EINVAL; + goto exit_nu_eadc_convert; + } + + if ((psNuEADC->chn_msk & (1 << channel)) == 0) + { + *value = 0xFFFFFFFF; + ret = RT_EBUSY; + goto exit_nu_eadc_convert; + } + + *value = _eadc_convert(psNuEADC, channel); + + ret = RT_EOK; + +exit_nu_eadc_convert: + + return -(ret); +} + +int rt_hw_eadc_init(void) +{ + int i; + rt_err_t result; + + /* Invoke ISP function to read built-in band-gap A/D conversion result*/ + FMC_Open(); + s_u32BuiltInBandGapValue = FMC_ReadBandGap(); + FMC_Close(); + + //rt_kprintf("s_u32BuiltInBandGapValue: %d\n", s_u32BuiltInBandGapValue); + + for (i = (EADC_START + 1); i < EADC_CNT; i++) + { + result = rt_hw_adc_register(&nu_eadc_arr[i].dev, nu_eadc_arr[i].name, &nu_adc_ops, NULL); + RT_ASSERT(result == RT_EOK); + } + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_eadc_init); +#endif //#if defined(BSP_USING_EADC) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.c new file mode 100644 index 00000000000..e8756396e68 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.c @@ -0,0 +1,50 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_EBI) + +#include "drv_ebi.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.ebi" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define MAX_BANK EBI_BANK2 + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ + +/* Static Variables ----------------------------------------------------------*/ +static uint8_t nu_ebi_bank_mask = 0; + +/* Functions Implementation --------------------------------------------------*/ +rt_err_t nu_ebi_init(uint32_t u32Bank, + uint32_t u32DataWidth, + uint32_t u32TimingClass, + uint32_t u32BusMode, + uint32_t u32CSActiveLevel) +{ + if (u32Bank > MAX_BANK) + return -(RT_ERROR); + + /* Check this bank is not used */ + if ((1 << u32Bank) & nu_ebi_bank_mask) + return -(RT_ERROR); + + /* Initialize EBI */ + EBI_Open(u32Bank, u32DataWidth, u32TimingClass, u32BusMode, u32CSActiveLevel); + + nu_ebi_bank_mask |= (1 << u32Bank); + + return RT_EOK; +} + +#endif //#if defined(BSP_USING_EBI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.h new file mode 100644 index 00000000000..ca6d940de9d --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ebi.h @@ -0,0 +1,41 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_EBI_H__ +#define __DRV_EBI_H__ +#include "rtdevice.h" +#include "NuMicro.h" + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return RT_EOK/RT_ERROR Bank is used or not + */ +rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +#endif /* __DRV_EBI_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ecap.c new file mode 100644 index 00000000000..a236e5d4a44 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ecap.c @@ -0,0 +1,277 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_ECAP) + +#include "drv_common.h" +#include "drv_sys.h" +#include "nu_bitutil.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.ecap" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define ECAP_CHANNEL_NUM 0x3 +#define ECAP_CHANNEL_MSK ((1 << ECAP_CHANNEL_NUM) - 1) +#define ECAP_CLK_DIV ECAP_CAPTURE_TIMER_CLKDIV_32 +#define NU_ECAP_GET_LEVEL(status, channel) (((status) & (1 << (ECAP_STATUS_CAP0_Pos + (channel)))) ? 0 : 1) +#define DEFINE_NU_ECAP(_mod, _chn) \ + { \ + .base = ECAP##_mod, \ + .name = "ecap" #_mod "i" #_chn, \ + .irqn = ECAP##_mod##_IRQn, \ + .rstidx = ECAP##_mod##_RST, \ + .modid = ECAP##_mod##_MODULE \ + } + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + ECAP_START = -1, +#if defined(BSP_USING_ECAP0) + ECAP0_IDX, + ECAP1_IDX, + ECAP2_IDX, +#endif + ECAP_CNT +}; + +struct nu_ecap +{ + struct rt_inputcapture_device parent; + ECAP_T *base; + char *name; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + + float fUsPerTick; + uint8_t u8Channel; + rt_bool_t bfirstData; + uint32_t u32CurrentCnt; + uint32_t u32LastCnt; + rt_bool_t input_data_level; +}; +typedef struct nu_ecap *nu_ecap_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_ecap_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_ecap_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_ecap_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_ecap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); +static void nu_ecap_isr(nu_ecap_t psNuEcap); +static float get_ecap_tick_time_us(nu_ecap_t psNuEcap); +static void nu_ecap_channel_init(ECAP_T *base); +static int rt_hw_ecap_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_ecap nu_ecap_arr [] = +{ +#if defined(BSP_USING_ECAP0) + DEFINE_NU_ECAP(0, 0), + DEFINE_NU_ECAP(0, 1), + DEFINE_NU_ECAP(0, 2), +#endif +}; + +static struct rt_inputcapture_ops nu_ecap_ops = +{ + .init = nu_ecap_init, + .open = nu_ecap_open, + .close = nu_ecap_close, + .get_pulsewidth = nu_ecap_get_pulsewidth, +}; + +/* Functions Implementation --------------------------------------------------*/ +#if defined(BSP_USING_ECAP0) +void ECAP0_IRQHandler(void) +{ + rt_interrupt_enter(); + + nu_ecap_isr((void *)&nu_ecap_arr[ECAP0_IDX]); + + rt_interrupt_leave(); +} +#endif + +static void nu_ecap_isr(nu_ecap_t psNuEcapBase) +{ + int i32ChnId; + ECAP_T *base = psNuEcapBase->base; + + /* Get input Capture status */ + uint32_t u32Status = ECAP_GET_INT_STATUS(base); + uint32_t u32ChStatus = u32Status & ECAP_CHANNEL_MSK; + + /* Check input capture channel flag */ + /* Find index of pin is attached in pool. */ + while ((i32ChnId = nu_ctz(u32ChStatus)) < ECAP_CHANNEL_NUM) // Count Trailing Zeros == > Find First One + { + if (u32ChStatus & (ECAP_STATUS_CAPTF0_Msk << i32ChnId)) + { + nu_ecap_t psNuEcap = psNuEcapBase + i32ChnId; + struct rt_inputcapture_device *inputcapture = (struct rt_inputcapture_device *)&psNuEcap->parent; + + /* Clear input capture channel flag */ + ECAP_CLR_CAPTURE_FLAG(base, 1 << (ECAP_STATUS_CAPTF0_Pos + i32ChnId)); + + if (inputcapture->ringbuff) + { + psNuEcap->input_data_level = NU_ECAP_GET_LEVEL(u32Status, i32ChnId); + + psNuEcap->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(base, i32ChnId); + + rt_hw_inputcapture_isr(inputcapture, psNuEcap->input_data_level); + } + } + + u32ChStatus &= ~(1 << i32ChnId); + } +} + +static rt_err_t nu_ecap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + float fTempCnt; + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + if (psNuEcap->bfirstData) + { + psNuEcap->bfirstData = RT_FALSE; + ret = RT_ERROR; + + return -(ret); + } + + if (psNuEcap->u32CurrentCnt > psNuEcap->u32LastCnt) + fTempCnt = psNuEcap->u32CurrentCnt - psNuEcap->u32LastCnt; + else /* Overrun case */ + fTempCnt = psNuEcap->u32CurrentCnt + ((0x1000000 - psNuEcap->u32LastCnt) + 1); + + *pulsewidth_us = (int)(fTempCnt * psNuEcap->fUsPerTick); + + psNuEcap->u32LastCnt = psNuEcap->u32CurrentCnt; + + return -(ret); +} + +static float get_ecap_tick_time_us(nu_ecap_t psNuEcap) +{ + uint8_t u8ClockDivider[8] = { 1, 4, 16, 32, 64, 96, 112, 128 }; + + if (psNuEcap->base == ECAP0) + return ((float)1000000 / ((float)CLK_GetPCLK0Freq() / u8ClockDivider[(psNuEcap->base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); + else + return ((float)1000000 / ((float)CLK_GetPCLK1Freq() / u8ClockDivider[(psNuEcap->base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); +} + +static rt_err_t nu_ecap_init(struct rt_inputcapture_device *inputcapture) +{ + return RT_EOK; +} + +static rt_err_t nu_ecap_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + psNuEcap->fUsPerTick = get_ecap_tick_time_us(psNuEcap); + + /* Enable ECAP Input Channel */ + ECAP_ENABLE_INPUT_CHANNEL(psNuEcap->base, 0x1 << (ECAP_CTL0_IC0EN_Pos + psNuEcap->u8Channel)); + + /* Input Channel interrupt enabled */ + ECAP_EnableINT(psNuEcap->base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + psNuEcap->u8Channel)); + + /* ECAP_CNT starts up-counting */ + ECAP_CNT_START(psNuEcap->base); + + return ret; +} + +static rt_err_t nu_ecap_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + /* Input Channel interrupt disabled */ + ECAP_DisableINT(psNuEcap->base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + psNuEcap->u8Channel)); + + /* Disable ECAP Input Channel */ + ECAP_DISABLE_INPUT_CHANNEL(psNuEcap->base, 0x1 << (ECAP_CTL0_IC0EN_Pos + psNuEcap->u8Channel)); + + /* Clear input capture channel flag */ + ECAP_CLR_CAPTURE_FLAG(psNuEcap->base, 0x1 << (ECAP_STATUS_CAPTF0_Pos + psNuEcap->u8Channel)); + + return ret; +} + +static void nu_ecap_channel_init(ECAP_T *base) +{ + /* Enable ECAP */ + ECAP_Open(base, ECAP_DISABLE_COMPARE); + + ECAP_SEL_TIMER_CLK_DIV(base, ECAP_CLK_DIV); + + /* Select Reload function */ + ECAP_SET_CNT_CLEAR_EVENT(base, ECAP_CTL1_OVRLDEN_Msk); + + /* Enable ECAP source IC */ + ECAP_SEL_INPUT_SRC(base, ECAP_IC0, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(base, ECAP_IC1, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(base, ECAP_IC2, ECAP_CAP_INPUT_SRC_FROM_IC); + + /* Select IC detect rising edge */ + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC0, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC1, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC2, ECAP_RISING_FALLING_EDGE); +} + +static int rt_hw_ecap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (ECAP_START + 1); i < ECAP_CNT; i++) + { + nu_ecap_t psNuEcap = &nu_ecap_arr[i]; + + psNuEcap->u8Channel = i % ECAP_CHANNEL_NUM; + psNuEcap->bfirstData = RT_TRUE; + psNuEcap->u32CurrentCnt = 0; + psNuEcap->u32LastCnt = 0; + psNuEcap->parent.ops = &nu_ecap_ops; + + if ((psNuEcap->u8Channel % ECAP_CHANNEL_NUM) == 0) + { + + /* register ecap module */ + CLK_EnableModuleClock(psNuEcap->modid); + SYS_ResetModule(psNuEcap->rstidx); + nu_ecap_channel_init(psNuEcap->base); + NVIC_EnableIRQ((IRQn_Type)psNuEcap->irqn); + } + ret = rt_device_inputcapture_register(&psNuEcap->parent, psNuEcap->name, psNuEcap); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_ecap_init); +#endif //#if defined(BSP_USING_ECAP) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm.c new file mode 100644 index 00000000000..835d67c303d --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm.c @@ -0,0 +1,209 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_EPWM) + +#include "NuMicro.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.epwm" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define MAKE_EPWM_NAME(x) #x +#define MAKE_EPWM_INSTANCE(x) \ + { \ + .name = MAKE_EPWM_NAME(epwm##x), \ + .base = EPWM##x, \ + .rstidx = EPWM##x##_RST, \ + .modid = EPWM##x##_MODULE, \ + }, + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + EPWM_START = -1, +#if defined(BSP_USING_EPWM0) + EPWM0_IDX, +#endif +#if defined(BSP_USING_EPWM1) + EPWM1_IDX, +#endif + EPWM_CNT +}; + +struct nu_epwm +{ + struct rt_device_pwm dev; + char *name; + EPWM_T *base; + uint32_t rstidx; + uint32_t modid; +}; +typedef struct nu_epwm *nu_epwm_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static int rt_hw_epwm_init(void); + +/* Static Variables ----------------------------------------------------------*/ + +static struct nu_epwm nu_epwm_arr [] = +{ +#if defined(BSP_USING_EPWM0) + MAKE_EPWM_INSTANCE(0) +#endif +#if defined(BSP_USING_EPWM1) + MAKE_EPWM_INSTANCE(1) +#endif +}; /* epwm nu_epwm */ + +static struct rt_pwm_ops nu_epwm_ops = +{ + .control = nu_epwm_control +}; + +/* Functions Implementation --------------------------------------------------*/ + +static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + + if (enable == RT_TRUE) + { + EPWM_EnableOutput(pwm_base, 1 << pwm_channel); + EPWM_Start(pwm_base, 1 << pwm_channel); + } + else + { + EPWM_DisableOutput(pwm_base, 1 << pwm_channel); + EPWM_ForceStop(pwm_base, 1 << pwm_channel); + } + + return result; +} + +static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + if ((((struct rt_pwm_configuration *)configuration)->period) <= 0) + return -(RT_ERROR); + + rt_uint8_t pwm_channel_pair; + rt_uint32_t pwm_freq, pwm_dutycycle ; + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period; + rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse; + rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + + if ((pwm_channel % 2) == 0) + pwm_channel_pair = pwm_channel + 1; + else + pwm_channel_pair = pwm_channel - 1; + + pwm_freq = (uint64_t)1000000000 / pwm_period; + pwm_dutycycle = (pwm_pulse * 100) / pwm_period; + + EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ; + + if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0)) + { + if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + } + else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + } + } + return RT_EOK; +} + +static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device) +{ + return CLK_GetPCLK0Freq(); //Both PCLK0 && PCLK1 are the same. +} + +static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel); + rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel); + + u32EPWMClockSrc = nu_epwm_clksr(device); + time_tick = (uint64_t)1000000000000 / u32EPWMClockSrc; + + pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000; + pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000; + ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period; + ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty; + + LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(device); + RT_ASSERT(configuration); + + if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_epwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_epwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return nu_epwm_set(device, configuration); + case PWM_CMD_GET: + return nu_epwm_get(device, configuration); + } + return -(RT_EINVAL); +} + +static int rt_hw_epwm_init(void) +{ + rt_err_t ret; + int i; + + for (i = (EPWM_START + 1); i < EPWM_CNT; i++) + { + + CLK_EnableModuleClock(nu_epwm_arr[i].modid); + + SYS_ResetModule(nu_epwm_arr[i].rstidx); + + ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, &nu_epwm_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_epwm_init); + +#endif //#if defined(BSP_USING_EPWM) \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm_capture.c new file mode 100644 index 00000000000..67e57de6acf --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_epwm_capture.c @@ -0,0 +1,296 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_EPWM_CAPTURE) + +#include "drv_sys.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.epwmcap" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define STR(x) #x +#define XSTR(x) STR(x) +#define CONCAT3(a, b, c) a##b##c +#define XCONCAT3(a, b, c) CONCAT3(a, b, c) +#define MAKE_EPWM_CAPTURE_NAME(x, y) XSTR(XCONCAT3(epwm, x, y)) + +#define MAKE_EPWM_CAPTURE_INSTANCE(x, y, z) \ + { \ + .name = MAKE_EPWM_CAPTURE_NAME(x, y), \ + .base = EPWM##x, \ + .irqn = EPWM##x##P##z##_IRQn, \ + .rstidx = EPWM##x##_RST, \ + .modid = EPWM##x##_MODULE, \ + }, + +#define FOR_EACH_EPWM_CHANNEL(x) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i0, 0) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i1, 0) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i2, 1) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i3, 1) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i4, 2) \ + MAKE_EPWM_CAPTURE_INSTANCE(x, i5, 2) + +#define MAKE_EPWM_ISR(x, y, z) \ + void EPWM##x##P##y##_IRQHandler(void) \ + { \ + rt_interrupt_enter(); \ + nu_epwmcap_isr(&nu_epwmcap_arr[EPWM##x##I##z##_IDX]); \ + nu_epwmcap_isr(&nu_epwmcap_arr[EPWM##x##I##z##_IDX + 1]); \ + rt_interrupt_leave(); \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + EPWM_IDX_START = -1, +#if defined(BSP_USING_EPWM0_CAPTURE) + EPWM0I0_IDX, + EPWM0I1_IDX, + EPWM0I2_IDX, + EPWM0I3_IDX, + EPWM0I4_IDX, + EPWM0I5_IDX, +#endif +#if defined(BSP_USING_EPWM1_CAPTURE) + EPWM1I0_IDX, + EPWM1I1_IDX, + EPWM1I2_IDX, + EPWM1I3_IDX, + EPWM1I4_IDX, + EPWM1I5_IDX, +#endif + EPWM_IDX_CNT +}; + +struct nu_epwmcap +{ + struct rt_inputcapture_device parent; + EPWM_T *base; + char *name; + IRQn_Type irqn; + uint32_t rstidx; + uint64_t modid; + + uint8_t u8Channel; + uint32_t u32CurrentRisingCnt; + uint32_t u32CurrentFallingCnt; + rt_bool_t input_data_level; +}; +typedef struct nu_epwmcap *nu_epwmcap_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_epwmcap_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); +static rt_err_t CalPulseWidth(nu_epwmcap_t psNuEpwmCap); +static void nu_epwmcap_isr(nu_epwmcap_t psNuEpwmCap); +static int rt_hw_epwmcap_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_epwmcap nu_epwmcap_arr [] = +{ +#if defined(BSP_USING_EPWM0_CAPTURE) + FOR_EACH_EPWM_CHANNEL(0) +#endif +#if defined(BSP_USING_EPWM1_CAPTURE) + FOR_EACH_EPWM_CHANNEL(1) +#endif +}; + +static struct rt_inputcapture_ops nu_epwmcap_ops = +{ + .init = nu_epwmcap_init, + .open = nu_epwmcap_open, + .close = nu_epwmcap_close, + .get_pulsewidth = nu_epwmcap_get_pulsewidth, +}; + +/* Functions Implementation --------------------------------------------------*/ +static void nu_epwmcap_isr(nu_epwmcap_t psNuEpwmCap) +{ + if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) != 0) + { + /* Calculate pulse width */ + if (CalPulseWidth(psNuEpwmCap) == RT_EOK) + { + rt_hw_inputcapture_isr(&psNuEpwmCap->parent, psNuEpwmCap->input_data_level); + } + } +} + +#if defined(BSP_USING_EPWM0_CAPTURE) + MAKE_EPWM_ISR(0, 0, 0); + MAKE_EPWM_ISR(0, 1, 2); + MAKE_EPWM_ISR(0, 2, 4); +#endif + +#if defined(BSP_USING_EPWM1_CAPTURE) + MAKE_EPWM_ISR(1, 0, 0); + MAKE_EPWM_ISR(1, 1, 2); + MAKE_EPWM_ISR(1, 2, 4); +#endif + +static rt_err_t CalPulseWidth(nu_epwmcap_t psNuEpwmCap) +{ + rt_bool_t bWrapAroundFlag = RT_FALSE; + + /* Check rising/falling capture counter is overflow or not */ + if (EPWM_GetWrapAroundFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel)) + { + EPWM_ClearWrapAroundFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + bWrapAroundFlag = RT_TRUE; + } + if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) == 1)//Rising edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + + if (bWrapAroundFlag) + { + psNuEpwmCap->u32CurrentRisingCnt = 0x10000; + } + psNuEpwmCap->u32CurrentRisingCnt += EPWM_GET_CAPTURE_RISING_DATA(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + } + else if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) == 2)//Falling edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + if (bWrapAroundFlag) + { + psNuEpwmCap->u32CurrentFallingCnt = 0x10000; + } + psNuEpwmCap->u32CurrentFallingCnt += EPWM_GET_CAPTURE_FALLING_DATA(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + } + else //Rising & Falling edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + return -(RT_ERROR); + } + + return RT_EOK; +} + +static rt_err_t nu_epwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t)inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + if (psNuEpwmCap->u32CurrentFallingCnt) + { + *pulsewidth_us = psNuEpwmCap->u32CurrentFallingCnt; + psNuEpwmCap->input_data_level = RT_FALSE; + psNuEpwmCap->u32CurrentFallingCnt = 0; + } + else if (psNuEpwmCap->u32CurrentRisingCnt) + { + *pulsewidth_us = psNuEpwmCap->u32CurrentRisingCnt; + psNuEpwmCap->input_data_level = RT_TRUE; + psNuEpwmCap->u32CurrentRisingCnt = 0; + } + else + { + ret = RT_ERROR; + } + return -(ret); +} + +static rt_err_t nu_epwmcap_init(struct rt_inputcapture_device *inputcapture) +{ + return RT_EOK; +} + +static rt_err_t nu_epwmcap_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t) inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + /* Set capture time as 1000 nanosecond */ + EPWM_ConfigCaptureChannel(psNuEpwmCap->base, psNuEpwmCap->u8Channel, 1000, 0); + + /* Enable capture rising/falling edge interrupt */ + EPWM_EnableCaptureInt(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable Capture Function for EPWM */ + EPWM_EnableCapture(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Enable rising/falling capture reload */ + psNuEpwmCap->base->CAPCTL |= (0x1 << (EPWM_CAPCTL_RCRLDEN0_Pos + psNuEpwmCap->u8Channel)) + | (0x1 << (EPWM_CAPCTL_FCRLDEN0_Pos + psNuEpwmCap->u8Channel)); + + /* Set counter type as down count */ + EPWM_SET_ALIGNED_TYPE(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel, EPWM_UP_COUNTER); + + /* Enable EPWM Timer */ + EPWM_Start(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Enable EPWMxPx interrupt. */ + NVIC_EnableIRQ(psNuEpwmCap->irqn); + + return ret; +} + +static rt_err_t nu_epwmcap_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t) inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + /* Disable capture rising/falling edge interrupt */ + EPWM_DisableCaptureInt(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Stop EPWM Timer */ + EPWM_ForceStop(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Disable EPWMxPx interrupt */ + if ((psNuEpwmCap->base->CNTEN & (0x3 << (psNuEpwmCap->u8Channel / 2 * 2))) == 0u) + NVIC_DisableIRQ(psNuEpwmCap->irqn); + + return ret; +} + +static int rt_hw_epwmcap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (EPWM_IDX_START + 1); i < EPWM_IDX_CNT; i++) + { + nu_epwmcap_t psNuEpwmCap = &nu_epwmcap_arr[i]; + + psNuEpwmCap->u8Channel = i % EPWM_CHANNEL_NUM; + psNuEpwmCap->u32CurrentRisingCnt = 0; + psNuEpwmCap->u32CurrentFallingCnt = 0; + psNuEpwmCap->parent.ops = &nu_epwmcap_ops; + + if ((psNuEpwmCap->u8Channel % EPWM_CHANNEL_NUM) == 0) + { + /* Enable epwm module */ + CLK_EnableModuleClock(psNuEpwmCap->modid); + SYS_ResetModule(psNuEpwmCap->rstidx); + } + ret = rt_device_inputcapture_register(&psNuEpwmCap->parent, psNuEpwmCap->name, psNuEpwmCap); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_epwmcap_init); +#endif //#if defined(BSP_USING_EPWM_CAPTURE) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c new file mode 100644 index 00000000000..b71b95f909e --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c @@ -0,0 +1,286 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_EQEI) + +#include "drv_eqei.h" +#include "drv_sys.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.eqei" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DEFINE_NU_EQEI(_idx) \ + { \ + .name = "eqei" #_idx, \ + .base = EQEI##_idx, \ + .irqn = EQEI##_idx##_IRQn,\ + .rstidx = EQEI##_idx##_RST,\ + .modid = EQEI##_idx##_MODULE,\ + .max_cntval = 1000, \ + .cmp_val = 100, \ + } + +#define DEFINE_EQEI_IRQ_HANDLER(_idx) \ +void EQEI##_idx##_IRQHandler(void) \ +{ \ + rt_interrupt_enter(); \ + \ + nu_eqei_isr((void *)&nu_eqei_arr[EQEI##_idx##_IDX]); \ + \ + rt_interrupt_leave(); \ +} + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + EQEI_START = -1, +#if defined(BSP_USING_EQEI0) && defined(EQEI0) + EQEI0_IDX, +#endif +#if defined(BSP_USING_EQEI1) && defined(EQEI1) + EQEI1_IDX, +#endif + EQEI_CNT +}; + +struct nu_qei +{ + struct rt_pulse_encoder_device dev; + char *name; + EQEI_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint64_t modid; + + rt_uint32_t max_cntval; + rt_uint32_t cmp_val; + rt_uint8_t qei_flag; +}; +typedef struct nu_qei *nu_eqei_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_uint32_t nu_eqei_type(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_eqei_init(struct rt_pulse_encoder_device *pulse_encoder); +static rt_int32_t nu_eqei_get_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_eqei_clear_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_eqei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args); +static void nu_eqei_isr(nu_eqei_t psNuEqei); +static int rt_hw_qei_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_qei nu_eqei_arr [] = +{ +#if defined(BSP_USING_EQEI0) && defined(EQEI0) + DEFINE_NU_EQEI(0), +#endif + +#if defined(BSP_USING_EQEI1) && defined(EQEI1) + DEFINE_NU_EQEI(1), +#endif +}; + +static const struct rt_pulse_encoder_ops nu_eqei_ops = +{ + .init = nu_eqei_init, + .get_count = nu_eqei_get_count, + .clear_count = nu_eqei_clear_count, + .control = nu_eqei_control, +}; + +/* Functions Implementation --------------------------------------------------*/ +#if defined(BSP_USING_EQEI0) && defined(EQEI0) +DEFINE_EQEI_IRQ_HANDLER(0) +#endif + +#if defined(BSP_USING_EQEI1) && defined(EQEI1) +DEFINE_EQEI_IRQ_HANDLER(1) +#endif + +static rt_uint32_t nu_eqei_type(struct rt_pulse_encoder_device *pulse_encoder) +{ + rt_uint32_t u32type; + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + switch (pulse_encoder->type) + { + case SINGLE_PHASE_PULSE_ENCODER: + u32type = (psNuEqei->cmp_val) ? EQEI_CTL_X2_COMPARE_COUNTING_MODE : EQEI_CTL_X2_FREE_COUNTING_MODE; + break; + + case UNKNOWN_PULSE_ENCODER_TYPE: + case AB_PHASE_PULSE_ENCODER: + default: + u32type = (psNuEqei->cmp_val) ? EQEI_CTL_X4_COMPARE_COUNTING_MODE : EQEI_CTL_X4_FREE_COUNTING_MODE; + break; + } + + rt_kprintf("[%d %d %d]\n", pulse_encoder->type, psNuEqei->cmp_val, u32type); + return u32type; +} + +void nu_eqei_set_cmpval(rt_device_t pulse_encoder, rt_uint32_t u32val) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + psNuEqei->cmp_val = u32val; + if (u32val > 0) + { + EQEI_DisableInt(psNuEqei->base, EQEI_CTL_CMPIEN_Msk); + EQEI_SET_CNT_CMP(psNuEqei->base, u32val); + EQEI_ENABLE_CNT_CMP(psNuEqei->base); + EQEI_EnableInt(psNuEqei->base, EQEI_CTL_CMPIEN_Msk); + } + else + { + EQEI_DisableInt(psNuEqei->base, EQEI_CTL_CMPIEN_Msk); + EQEI_DISABLE_CNT_CMP(psNuEqei->base); + EQEI_SET_CNT_CMP(psNuEqei->base, 0); + } +} + +static rt_err_t nu_eqei_init(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + /* enable noise filter */ + EQEI_ENABLE_NOISE_FILTER(psNuEqei->base, EQEI_CTL_NFCLKSEL_DIV2); + + /* set compare value and interrupt */ + nu_eqei_set_cmpval((rt_device_t)pulse_encoder, psNuEqei->cmp_val); + + /* set qei mode */ + EQEI_Open(psNuEqei->base, nu_eqei_type(pulse_encoder), psNuEqei->max_cntval); + + return RT_EOK; +} + +static rt_int32_t nu_eqei_get_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + return (rt_int32_t)EQEI_GET_CNT_VALUE(psNuEqei->base); +} + +static rt_err_t nu_eqei_clear_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + EQEI_Stop(psNuEqei->base); + EQEI_SET_CNT_VALUE(psNuEqei->base, 0); + EQEI_Start(psNuEqei->base); + + return RT_EOK; +} + +static rt_err_t nu_eqei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) +{ + rt_err_t result = RT_EOK; + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + switch (cmd) + { + case PULSE_ENCODER_CMD_ENABLE: + /* set compare value and interrupt */ + EQEI_Start(psNuEqei->base); + nu_eqei_set_cmpval((rt_device_t)pulse_encoder, psNuEqei->cmp_val); + break; + case PULSE_ENCODER_CMD_DISABLE: + EQEI_Stop(psNuEqei->base); + nu_eqei_set_cmpval((rt_device_t)pulse_encoder, 0); + break; + default: + result = -RT_ENOSYS; + break; + } + + return result; +} + +static void nu_eqei_isr(nu_eqei_t psNuEqei) +{ + if (EQEI_GET_INT_FLAG(psNuEqei->base, EQEI_STATUS_CMPF_Msk)) + { + psNuEqei->qei_flag = 1; + EQEI_CLR_INT_FLAG(psNuEqei->base, EQEI_STATUS_CMPF_Msk); + rt_kprintf("%s: CMP flag rising\n", psNuEqei->name) ; + } +} + +rt_int32_t nu_eqei_get_maxval(rt_device_t pulse_encoder) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + return psNuEqei->max_cntval; +} + +rt_int32_t nu_eqei_get_cmpval(rt_device_t pulse_encoder) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + return psNuEqei->cmp_val; +} + +rt_int32_t nu_eqei_get_type(rt_device_t pulse_encoder) +{ + RT_ASSERT(pulse_encoder != RT_NULL); + return nu_eqei_type((struct rt_pulse_encoder_device *)pulse_encoder); +} + +void nu_eqei_set_maxval_type(rt_device_t pulse_encoder, rt_uint32_t u32val, enum rt_pulse_encoder_type eType) +{ + nu_eqei_t psNuEqei = (nu_eqei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + RT_ASSERT(eType <= AB_PHASE_PULSE_ENCODER); + + psNuEqei->dev.type = eType; + psNuEqei->max_cntval = u32val; + EQEI_Open(psNuEqei->base, nu_eqei_type(&psNuEqei->dev), u32val); +} + +static int rt_hw_qei_init(void) +{ + int i; + rt_err_t result = RT_EOK; + + for (i = (EQEI_START + 1); i < EQEI_CNT; i++) + { + nu_eqei_t psNuEqei = &nu_eqei_arr[i]; + + psNuEqei->dev.type = AB_PHASE_PULSE_ENCODER; + psNuEqei->dev.ops = &nu_eqei_ops; + + /* Enable QEI module */ + CLK_EnableModuleClock(psNuEqei->modid); + SYS_ResetModule(psNuEqei->rstidx); + + result = rt_device_pulse_encoder_register((struct rt_pulse_encoder_device *)&nu_eqei_arr[i].dev, nu_eqei_arr[i].name, (void *)&psNuEqei->qei_flag); + RT_ASSERT(result == RT_EOK); + } + + return (int)result; +} + +INIT_APP_EXPORT(rt_hw_qei_init); + +#endif //#if defined(BSP_USING_EQEI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.h new file mode 100644 index 00000000000..7548be84909 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.h @@ -0,0 +1,18 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_EQEI_H__ +#define __DRV_EQEI_H__ +#include "rtthread.h" +#include "rtdevice.h" + +rt_int32_t nu_eqei_get_maxval(rt_device_t pulse_encoder); +rt_int32_t nu_eqei_get_cmpval(rt_device_t pulse_encoder); +rt_int32_t nu_eqei_get_type(rt_device_t pulse_encoder); +void nu_eqei_set_maxval_type(rt_device_t pulse_encoder, rt_uint32_t u32val, enum rt_pulse_encoder_type eType); +void nu_eqei_set_cmpval(rt_device_t pulse_encoder, rt_uint32_t u32val); + +#endif /* __DRV_EQEI_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c new file mode 100644 index 00000000000..bb44621508b --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c @@ -0,0 +1,391 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_FMC) + +#include "NuMicro.h" +#include "drv_fmc.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.fmc" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define NU_SUPPORT_NONALIGN + +/* Get byte offset within a word (0, 8, 16, 24) */ +#define NU_GETBYTE_OFST(addr) (((addr) & 0x3) * 8) +/* Get word-aligned address (4-byte aligned) */ +#define NU_GET_WALIGN(addr) ((addr) & ~0x3) +/* Get double-word-aligned address (8-byte aligned) */ +#define NU_GET_DWALIGN(addr) ((addr) & ~0x7) +/* Get lowest 2 bits (for word alignment checks) */ +#define NU_GET_LSB2BIT(addr) ((addr) & 0x3) +/* Get lowest 3 bits (for double-word alignment checks) */ +#define NU_GET_LSB3BIT(addr) ((addr) & 0x7) + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +#if defined(RT_USING_FAL) +static int aprom_read(long offset, uint8_t *buf, size_t size); +static int aprom_write(long offset, const uint8_t *buf, size_t size); +static int aprom_erase(long offset, size_t size); + +static int ldrom_read(long offset, uint8_t *buf, size_t size); +static int ldrom_write(long offset, const uint8_t *buf, size_t size); +static int ldrom_erase(long offset, size_t size); + +static int dataflash_read(long offset, uint8_t *buf, size_t size); +static int dataflash_write(long offset, const uint8_t *buf, size_t size); +static int dataflash_erase(long offset, size_t size); +#endif /* RT_USING_FAL */ +static int nu_fmc_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static rt_mutex_t g_mutex_fmc = RT_NULL; + +#if defined(RT_USING_FAL) +const struct fal_flash_dev g_falFMC_AP = +{ + "FMC_AP", + FMC_APROM_BASE, + FMC_APROM_SIZE, + FMC_FLASH_PAGE_SIZE, + { + NULL, + aprom_read, + aprom_write, + aprom_erase + } +}; + +const struct fal_flash_dev g_falFMC_LD = +{ + "FMC_LD", + FMC_LDROM_BASE, + FMC_LDROM_SIZE, + FMC_FLASH_PAGE_SIZE, + { + NULL, + ldrom_read, + ldrom_write, + ldrom_erase + } +}; + +const struct fal_flash_dev g_falFMC_DF = +{ + "FMC_DF", + FMC_DATA_FLASH_BASE, + FMC_DATA_FLASH_SIZE, + FMC_FLASH_PAGE_SIZE, + { + NULL, + dataflash_read, + dataflash_write, + dataflash_erase + } +}; +#endif /* RT_USING_FAL */ + +/* Functions Implementation --------------------------------------------------*/ + +/** + * @brief Read data from FMC flash memory. + * @param addr: Start address to read from + * @param buf: Buffer to store read data + * @param size: Number of bytes to read + * @return Number of bytes actually read + */ +int nu_fmc_read(long addr, uint8_t *buf, size_t size) +{ + size_t read_size = 0; + uint32_t addr_end = addr + size; + uint32_t isp_rdata = 0; + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + + // If address is not word-aligned, read the aligned word first + if (NU_GET_LSB2BIT(addr)) + isp_rdata = FMC_Read(NU_GET_WALIGN(addr)); + + for (; addr < addr_end;) + { + if (NU_GET_LSB2BIT(addr) == 0) + { + isp_rdata = FMC_Read(addr); + if (addr_end - addr >= 4) + { + *(uint32_t *)buf = isp_rdata; + addr += 4; + buf += 4; + read_size += 4; + continue; + } + } + *buf = (uint8_t)(isp_rdata >> NU_GETBYTE_OFST(addr)); + addr++; + buf++; + read_size++; + } + + rt_mutex_release(g_mutex_fmc); + return read_size; +} + +/** + * @brief Write data to FMC flash memory. + * @param addr: Start address to write to + * @param buf: Buffer containing data to write + * @param size: Number of bytes to write + * @return Number of bytes actually written + */ +int nu_fmc_write(long addr, const uint8_t *buf, size_t size) +{ + size_t write_size = 0; + uint32_t addr_end = addr + size; + uint64_t isp_rdata = 0; + + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + + // Enable APROM, LDROM or DATAFLASH update depending on address + if (addr < FMC_APROM_END) + FMC_ENABLE_AP_UPDATE(); + else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE) + FMC_ENABLE_LD_UPDATE(); + else if ((addr < FMC_DATA_FLASH_END) && addr >= FMC_DATA_FLASH_BASE) + FMC_ENABLE_DF_UPDATE(); + else + goto Exit2; + + // If address is not dword-aligned, read the aligned dword first + if (NU_GET_LSB3BIT(addr)) + { + FMC_Read64(NU_GET_DWALIGN(addr), &isp_rdata); + } + + for (; addr < addr_end;) + { + if ((addr_end - addr >= 8) && (NU_GET_LSB3BIT(addr) == 0)) + { + FMC_Write64(addr, *((uint64_t *)buf)); + addr += 8; + buf += 8; + write_size += 8; + continue; + } + + if (NU_GET_LSB3BIT(addr) == 0) + { + FMC_Read64(NU_GET_DWALIGN(addr), &isp_rdata); + } + + int byte_ofs = addr & 0x7; + isp_rdata = (isp_rdata & ~((uint64_t)0xFF << (byte_ofs * 8))) | + ((uint64_t)(*buf) << (byte_ofs * 8)); + + if (NU_GET_LSB3BIT(addr) == 0x7) + { + FMC_Write64(NU_GET_DWALIGN(addr), isp_rdata); + } + + addr ++; + buf++; + write_size++; + } + if (NU_GET_LSB3BIT(addr)) + FMC_Write64(NU_GET_DWALIGN(addr), isp_rdata); + + FMC_DISABLE_AP_UPDATE(); + FMC_DISABLE_LD_UPDATE(); + FMC_DISABLE_DF_UPDATE(); + +Exit2: + + rt_mutex_release(g_mutex_fmc); + return write_size; +} + +/** + * @brief Erase flash memory region. + * @param addr: Start address to erase + * @param size: Number of bytes to erase + * @return Number of bytes actually erased + */ +int nu_fmc_erase(long addr, size_t size) +{ + size_t erased_size = 0; + uint32_t addrptr; + uint32_t addr_end = addr + size; +#if defined(NU_SUPPORT_NONALIGN) + uint8_t *page_sdtemp = RT_NULL; + uint8_t *page_edtemp = RT_NULL; + + // Save data before the first page boundary if not aligned + addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + page_sdtemp = rt_malloc(addrptr); + if (page_sdtemp == RT_NULL) + { + erased_size = 0; + goto Exit3; + } + if (nu_fmc_read(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr) + { + erased_size = 0; + goto Exit3; + } + } + addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + page_edtemp = rt_malloc(FMC_FLASH_PAGE_SIZE - addrptr); + if (page_edtemp == RT_NULL) + { + erased_size = 0; + goto Exit3; + } + if (nu_fmc_read(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr) + { + erased_size = 0; + goto Exit3; + } + } +#endif + + rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER); + + // Enable APROM, LDROM or DATAFLASH update depending on address + if (addr <= FMC_APROM_END) + FMC_ENABLE_AP_UPDATE(); + else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE) + FMC_ENABLE_LD_UPDATE(); + else if ((addr < FMC_DATA_FLASH_END) && addr >= FMC_DATA_FLASH_BASE) + FMC_ENABLE_DF_UPDATE(); + else + goto Exit2; + + // Erase each page in the region + addrptr = (addr & ~(FMC_FLASH_PAGE_SIZE - 1)); + while (addrptr < addr_end) + { + if (FMC_Erase(addrptr) != RT_EOK) + goto Exit1; + erased_size += FMC_FLASH_PAGE_SIZE; + addrptr += FMC_FLASH_PAGE_SIZE; + } + +Exit1: + + FMC_DISABLE_AP_UPDATE(); + FMC_DISABLE_LD_UPDATE(); + +Exit2: + + rt_mutex_release(g_mutex_fmc); +#if defined(NU_SUPPORT_NONALIGN) + // Restore saved data if needed + if (erased_size >= size) + { + addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + if (nu_fmc_write(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr) + goto Exit3; + erased_size += addrptr; + } + addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1); + if (addrptr) + { + if (nu_fmc_write(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr) + goto Exit3; + erased_size += FMC_FLASH_PAGE_SIZE - addrptr; + } + } + else + erased_size = 0; + +Exit3: + if (page_sdtemp != RT_NULL) + rt_free(page_sdtemp); + if (page_edtemp != RT_NULL) + rt_free(page_edtemp); +#endif + return erased_size; +} +#if defined(RT_USING_FAL) + +static int aprom_read(long offset, uint8_t *buf, size_t size) +{ + return nu_fmc_read(g_falFMC_AP.addr + offset, buf, size); +} + +static int aprom_write(long offset, const uint8_t *buf, size_t size) +{ + return nu_fmc_write(g_falFMC_AP.addr + offset, buf, size); +} + +static int aprom_erase(long offset, size_t size) +{ + return nu_fmc_erase(g_falFMC_AP.addr + offset, size); +} + +static int ldrom_read(long offset, uint8_t *buf, size_t size) +{ + return nu_fmc_read(g_falFMC_LD.addr + offset, buf, size); +} + +static int ldrom_write(long offset, const uint8_t *buf, size_t size) +{ + return nu_fmc_write(g_falFMC_LD.addr + offset, buf, size); +} + +static int ldrom_erase(long offset, size_t size) +{ + return nu_fmc_erase(g_falFMC_LD.addr + offset, size); +} + +static int dataflash_read(long offset, uint8_t *buf, size_t size) +{ + return nu_fmc_read(g_falFMC_DF.addr + offset, buf, size); +} + +static int dataflash_write(long offset, const uint8_t *buf, size_t size) +{ + return nu_fmc_write(g_falFMC_DF.addr + offset, buf, size); +} + +static int dataflash_erase(long offset, size_t size) +{ + return nu_fmc_erase(g_falFMC_DF.addr + offset, size); +} +#endif /* RT_USING_FAL */ + +static int nu_fmc_init(void) +{ + FMC_ENABLE_ISP(); + + g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_PRIO); + RT_ASSERT(g_mutex_fmc); + +#if defined(RT_USING_FAL) + /* RT_USING_FAL */ + extern int fal_init_check(void); + if (!fal_init_check()) + fal_init(); +#endif + + return (int)RT_EOK; +} + +INIT_APP_EXPORT(nu_fmc_init); + +#endif //#if defined(BSP_USING_FMC) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h new file mode 100644 index 00000000000..0b16d76bb4d --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h @@ -0,0 +1,22 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_FMC_H__ +#define __DRV_FMC_H__ +#include "rtthread.h" + +#if defined(RT_USING_FAL) +#include "fal.h" + + extern const struct fal_flash_dev g_falFMC_AP; + extern const struct fal_flash_dev g_falFMC_LD; + extern const struct fal_flash_dev g_falFMC_DF; +#endif + +int nu_fmc_read(long offset, uint8_t *buf, size_t size); +int nu_fmc_write(long offset, const uint8_t *buf, size_t size); +int nu_fmc_erase(long offset, size_t size); +#endif /* __DRV_FMC_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c new file mode 100644 index 00000000000..45dec56d915 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c @@ -0,0 +1,348 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) + +#include "NuMicro.h" +#include "drv_gpio.h" +#include "nu_bitutil.h" +#include +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.gpio" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define PORT_OFFSET 0x40 +#define IRQ_MAX_NUM 32 +#define MAX_PORTH_PIN_MAX 11 + +#define DEFINE_GPIO_IRQ_HANDLER(_port) \ +void GP##_port##_IRQHandler(void) \ +{ \ + rt_uint32_t int_status; \ + \ + rt_interrupt_enter(); \ + \ + int_status = P##_port->INTSRC; \ + pin_irq_hdr(int_status, NU_P##_port); \ + P##_port->INTSRC = int_status; \ + \ + rt_interrupt_leave(); \ +} + +#if !defined(GPIO_PIN_DATA) +#define GPIO_PIN_DATA GPIO_PIN_DATA_S +#endif + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); +static int nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_base_t pin); +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); +static rt_base_t nu_gpio_pin_get(const char *name); +static rt_err_t nu_port_check(rt_int32_t pin); +static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index); +static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index); +static int rt_hw_gpio_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM]; + +static struct rt_pin_ops nu_gpio_ops = +{ + nu_gpio_mode, + nu_gpio_write, + nu_gpio_read, + nu_gpio_attach_irq, + nu_gpio_detach_irq, + nu_gpio_irq_enable, + nu_gpio_pin_get, +}; + +static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn}; + +static rt_uint32_t g_u32PinIrqMask = 0x0; + +/* Functions Implementation --------------------------------------------------*/ + +DEFINE_GPIO_IRQ_HANDLER(A) +DEFINE_GPIO_IRQ_HANDLER(B) +DEFINE_GPIO_IRQ_HANDLER(C) +DEFINE_GPIO_IRQ_HANDLER(D) +DEFINE_GPIO_IRQ_HANDLER(E) +DEFINE_GPIO_IRQ_HANDLER(F) +DEFINE_GPIO_IRQ_HANDLER(G) +DEFINE_GPIO_IRQ_HANDLER(H) + +static rt_err_t nu_port_check(rt_int32_t pin) +{ + if (NU_GET_PORT(pin) >= NU_PORT_CNT) + return -(RT_ERROR); + else if ((NU_GET_PORT(pin) == NU_PH) && (NU_GET_PINS(pin) > MAX_PORTH_PIN_MAX)) + return -(RT_ERROR); + + return RT_EOK; +} + +static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index) +{ + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros == > Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin_index) + return irqindex; + + u32PinIrqStatus &= ~(1 << irqindex); + } + + return -(RT_ERROR); +} + +static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index) +{ + rt_int32_t irqindex, i; + rt_int32_t pinindex = port_index * GPIO_PIN_MAX ; + + while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros == > Find First One + { + int pin_mask = (1 << i); + irqindex = nu_find_irqindex(pinindex + i); + if (irqindex != -(RT_ERROR)) + { + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } + irq_status &= ~pin_mask; + } +} + +static rt_base_t nu_gpio_pin_get(const char *name) +{ + /* Get pin number by name, such as PA.0, PF12 */ + if ((name[2] == '\0') || ((name[2] == '.') && (name[3] == '\0'))) + return -(RT_EINVAL); + + long number; + + if ((name[2] == '.')) + number = atol(&name[3]); + else + number = atol(&name[2]); + + if (number > 15) + return -(RT_EINVAL); + + if (name[1] >= 'A' && name[1] <= 'H') + return ((name[1] - 'A') * 0x10) + number; + + if (name[1] >= 'a' && name[1] <= 'h') + return ((name[1] - 'a') * 0x10) + number; + + return -(RT_EINVAL); +} + +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode) +{ + GPIO_T *PORT; + + if (nu_port_check(pin)) + return; + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + if (mode == PIN_MODE_INPUT_PULLUP) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN); + } + else if (mode == PIN_MODE_OUTPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT); + } + else if (mode == PIN_MODE_INPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } +} + +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) +{ + if (nu_port_check(pin)) + return; + + GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; +} + +static int nu_gpio_read(struct rt_device *device, rt_base_t pin) +{ + if (nu_port_check(pin)) + return PIN_LOW; + + return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); +} + +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + // Find index of pin is attached in pool. + if ((irqindex = nu_find_irqindex(pin)) >= 0) + goto exit_nu_gpio_attach_irq; + + // Find available index of pin in pool. + if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones == > Find First Zero + goto exit_nu_gpio_attach_irq; + + rt_hw_interrupt_enable(level); + + return -(RT_EBUSY); + +exit_nu_gpio_attach_irq: + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + + g_u32PinIrqMask |= (1 << irqindex); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_base_t pin) +{ + rt_base_t level; + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros == > Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + g_u32PinIrqMask &= ~(1 << irqindex); + break; + } + u32PinIrqStatus &= ~(1 << irqindex); + } + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) +{ + GPIO_T *PORT; + rt_base_t level; + uint32_t u32IntAttribs; + rt_int32_t irqindex; + rt_err_t ret = RT_EOK; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + irqindex = nu_find_irqindex(pin); + if (irqindex == -(RT_ERROR)) + { + ret = RT_ERROR; + goto exit_nu_gpio_irq_enable; + } + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + if (enabled == PIN_IRQ_ENABLE) + { + if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING) + u32IntAttribs = GPIO_INT_RISING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING) + u32IntAttribs = GPIO_INT_FALLING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING) + u32IntAttribs = GPIO_INT_BOTH_EDGE; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL) + u32IntAttribs = GPIO_INT_HIGH; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL) + u32IntAttribs = GPIO_INT_LOW; + else + goto exit_nu_gpio_irq_enable; + + GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs); + + NVIC_EnableIRQ(au32GPIRQ[NU_GET_PORT(pin)]); + } + else + { + GPIO_DisableInt(PORT, NU_GET_PINS(pin)); + } + +exit_nu_gpio_irq_enable: + + rt_hw_interrupt_enable(level); + return -(ret); +} + +static int rt_hw_gpio_init(void) +{ + rt_int32_t irqindex; + for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + } + + return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL); +} + +INIT_BOARD_EXPORT(rt_hw_gpio_init); + +#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.h new file mode 100644 index 00000000000..57ffe5a40a5 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.h @@ -0,0 +1,26 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +typedef enum +{ + NU_PA, + NU_PB, + NU_PC, + NU_PD, + NU_PE, + NU_PF, + NU_PG, + NU_PH, + NU_PORT_CNT, +} nu_gpio_port; +#define NU_GET_PININDEX(port, pin) ((port)*16+(pin)) +#define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F) +#define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F) +#define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin)) +#endif /* __DRV_GPIO_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c new file mode 100644 index 00000000000..a40c387a387 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c @@ -0,0 +1,373 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_I2C) + +#include "NuMicro.h" +#include "drv_i2c.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.i2c" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DEFINE_NU_I2C(_idx) \ + { \ + .base = I2C##_idx, \ + .name = "i2c" #_idx, \ + } + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + I2C_START = -1, +#if defined(BSP_USING_I2C0) + I2C0_IDX, +#endif +#if defined(BSP_USING_I2C1) + I2C1_IDX, +#endif +#if defined(BSP_USING_I2C2) + I2C2_IDX, +#endif + I2C_CNT +}; + +struct nu_i2c_bus +{ + struct rt_i2c_bus_device parent; + I2C_T *base; + char *name; + struct rt_i2c_msg *msg; +}; +typedef struct nu_i2c_bus *nu_i2c_bus_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_ssize_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); +static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, int i32Cmd, void *pvArg); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_i2c_bus nu_i2c_arr [ ] = +{ +#if defined(BSP_USING_I2C0) + DEFINE_NU_I2C(0), +#endif +#if defined(BSP_USING_I2C1) + DEFINE_NU_I2C(1), +#endif +#if defined(BSP_USING_I2C2) + DEFINE_NU_I2C(2), +#endif +#if defined(BSP_USING_I2C3) && defined(I2C3) + DEFINE_NU_I2C(3), +#endif +}; + +#if defined(BSP_USING_I2C) +static const struct rt_i2c_bus_device_ops nu_i2c_ops = +{ + .master_xfer = nu_i2c_mst_xfer, + .slave_xfer = NULL, + .i2c_bus_control = nu_i2c_bus_control +}; +#endif + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, int i32Cmd, void *pvArg) +{ + nu_i2c_bus_t nu_i2c; + rt_ubase_t uctrl_arg = (rt_ubase_t)pvArg; + + RT_ASSERT(bus); + nu_i2c = (nu_i2c_bus_t) bus; + + switch (i32Cmd) + { + case RT_I2C_DEV_CTRL_CLK: + I2C_SetBusClockFreq(nu_i2c->base, (uint32_t)uctrl_arg); + break; + default: + return -RT_EIO; + } + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t bus) +{ + rt_tick_t start = rt_tick_get(); + while (!(bus->base->CTL0 & I2C_CTL0_SI_Msk)) + { + if ((rt_tick_get() - start) > bus->parent.timeout) + { + LOG_E("\ni2c: timeout!\n"); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t nu_i2c, rt_uint8_t data) +{ + I2C_SET_DATA(nu_i2c->base, data); + I2C_SET_CONTROL_REG(nu_i2c->base, I2C_CTL_SI); + return nu_i2c_wait_ready_with_timeout(nu_i2c); +} + +static rt_err_t nu_i2c_send_address(nu_i2c_bus_t nu_i2c, + struct rt_i2c_msg *msg) + { + rt_uint16_t flags = msg->flags; + rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + rt_uint8_t addr1, addr2; + rt_err_t ret; + + if (flags & RT_I2C_ADDR_10BIT) + { + nu_i2c->base->CTL1 |= I2C_CTL1_ADDR10EN_Msk; + addr1 = 0xf0 | ((msg->addr >> 7) & 0x06); + addr2 = msg->addr & 0xff; + + LOG_D("address1: %d, address2: %d\n", addr1, addr2); + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending first address failed\n"); + + return -RT_EIO; + } + + ret = nu_i2c_send_data(nu_i2c, addr2); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending second address failed\n"); + + return -RT_EIO; + } + + if (flags & RT_I2C_RD) + { + LOG_D("send repeated START signal\n"); + + I2C_SET_CONTROL_REG(nu_i2c->base, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack) + { + //LOG_E("sending repeated START failed\n"); + + return -RT_EIO; + } + + addr1 |= 0x01; + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending read address failed\n"); + + return -RT_EIO; + } + } + } + else + { + /* 7-bit addr */ + addr1 = msg->addr << 1; + if (flags & RT_I2C_RD) + addr1 |= 1; + + /* Send device address */ + ret = nu_i2c_send_data(nu_i2c, addr1); /* Send Address */ + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->base) + != ((flags & RT_I2C_RD) ? NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK)) + && !ignore_nack) + { + //LOG_E("sending address failed\n"); + return -RT_EIO; + } + } + + return RT_EOK; +} + +static rt_ssize_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) + { + struct rt_i2c_msg *msg; + nu_i2c_bus_t nu_i2c; + rt_size_t i; + rt_uint32_t cnt_data; + rt_uint16_t ignore_nack; + rt_err_t ret; + + RT_ASSERT(bus != RT_NULL); + nu_i2c = (nu_i2c_bus_t) bus; + + nu_i2c->msg = msgs; + + nu_i2c->base->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + { + rt_set_errno(-RT_ETIMEOUT); + return 0; + } + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_START) + { + i = 0; + LOG_E("Send START Failed"); + return i; + } + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + + if (!(msg->flags & RT_I2C_NO_START)) + { + if (i) + { + I2C_SET_CONTROL_REG(nu_i2c->base, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_REPEAT_START) + { + i = 0; + //LOG_E("Send repeat START Fail"); + break; + } + } + + if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg)) + && !ignore_nack) + { + i = 0; + //LOG_E("Send Address Fail"); + break; + } + } + + if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */ + { + rt_uint32_t do_rd_nack = (i == (num - 1)); + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */ + if (do_rd_nack == 2) + { + I2C_SET_CONTROL_REG(nu_i2c->base, I2C_CTL_SI); + } + else + { + I2C_SET_CONTROL_REG(nu_i2c->base, I2C_CTL_SI_AA); + } + + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (nu_i2c->base->CTL0 & I2C_CTL_AA) + { + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_RECEIVE_DATA_ACK) + { + i = 0; + break; + } + } + else + { + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_RECEIVE_DATA_NACK) + { + i = 0; + break; + } + } + + nu_i2c->msg[i].buf[cnt_data] = nu_i2c->base->DAT; + } + } + else /* Send Bytes */ + { + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + /* Send register number and MSB of data */ + ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data])); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_TRANSMIT_DATA_ACK + && !ignore_nack + ) /* Send aata and get Ack */ + { + i = 0; + break; + } + } + } + } + + I2C_STOP(nu_i2c->base); + + RT_ASSERT(I2C_GET_STATUS(nu_i2c->base) == NU_I2C_MASTER_STATUS_BUS_RELEASED); + if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_BUS_RELEASED) + { + i = 0; + } + + nu_i2c->msg = RT_NULL; + nu_i2c->base->CTL1 = 0; /*clear all sub modes like 10 bit mode*/ + return i; +} + +static int rt_hw_i2c_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (I2C_START + 1); i < I2C_CNT; i++) + { + /* Reset and initial IP engine. */ + I2C_Close(nu_i2c_arr[i].base); + I2C_Open(nu_i2c_arr[i].base, 100000); + + nu_i2c_arr[i].parent.ops = &nu_i2c_ops; + + ret = rt_i2c_bus_device_register(&nu_i2c_arr[i].parent, nu_i2c_arr[i].name); + RT_ASSERT(RT_EOK == ret); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* BSP_USING_I2C */ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.h new file mode 100644 index 00000000000..b5bc4de24d6 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.h @@ -0,0 +1,40 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ +#define NU_I2C_MASTER_STATUS_START 0x08UL +#define NU_I2C_MASTER_STATUS_REPEAT_START 0x10UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK 0x18UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK 0x20UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_DATA_ACK 0x28UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_DATA_NACK 0x30UL +#define NU_I2C_MASTER_STATUS_ARBITRATION_LOST 0x38UL +#define NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK 0x40UL +#define NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK 0x48UL +#define NU_I2C_MASTER_STATUS_RECEIVE_DATA_ACK 0x50UL +#define NU_I2C_MASTER_STATUS_RECEIVE_DATA_NACK 0x58UL +#define NU_I2C_MASTER_STATUS_BUS_ERROR 0x00UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_REPEAT_START_OR_STOP 0xA0UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_ADDRESS_ACK 0xA8UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_DATA_ACK 0xB8UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_DATA_NACK 0xC0UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_LAST_DATA_ACK 0xC8UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_ADDRESS_ACK 0x60UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_ARBITRATION_LOST 0x68UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_DATA_ACK 0x80UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_DATA_NACK 0x88UL + +#define NU_I2C_SLAVE_GC_ADDRESS_ACK 0x70UL +#define NU_I2C_SLAVE_GC_ARBITRATION_LOST 0x78UL +#define NU_I2C_SLAVE_GC_DATA_ACK 0x90UL +#define NU_I2C_SLAVE_GC_DATA_NACK 0x98UL +#define NU_I2C_SLAVE_GC_ADDRESS_TRANSMIT_ARBITRATION_LOST 0xB0UL +#define NU_I2C_STATUS_BUS_RELEASED 0xF8UL +#define NU_I2C_MASTER_STATUS_BUS_RELEASED NU_I2C_STATUS_BUS_RELEASED +#define NU_I2C_SLAVE_STATUS_BUS_RELEASED NU_I2C_STATUS_BUS_RELEASED + +#endif /* __DRV_I2C_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.c new file mode 100644 index 00000000000..a786c9272d0 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.c @@ -0,0 +1,607 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_I2S) + +#include "drv_i2s.h" +#include "drv_pdma.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.i2s" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "i2s" +#define DBG_COLOR + +#define DEFINE_NU_I2S(_idx) \ + { \ + .name = "sound" #_idx, \ + .i2s_base = I2S##_idx, \ + .i2s_rst = I2S##_idx##_RST, \ + .i2s_dais = { \ + [NU_I2S_DAI_PLAYBACK] = { \ + .pdma_perp = PDMA_I2S##_idx##_TX, \ + }, \ + [NU_I2S_DAI_CAPTURE] = { \ + .pdma_perp = PDMA_I2S##_idx##_RX, \ + } \ + } \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + I2S_START = -1, +#if defined(BSP_USING_I2S0) + I2S0_IDX, +#endif + I2S_CNT +}; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_init(struct rt_audio_device *audio); +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream); +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_i2s nu_i2s_arr[] = +{ +#if defined(BSP_USING_I2S0) + DEFINE_NU_I2S(0), +#endif +}; + +/* Functions Implementation --------------------------------------------------*/ +rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t); +static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + // Report a buffer ready. + rt_uint8_t *pbuf_old = &psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ; + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuI2s->audio); + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + I2S_T *i2s_base; + nu_i2s_dai_t psNuI2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + struct nu_pdma_chn_cb sChnCB; + + RT_ASSERT(psNuI2s != RT_NULL); + + /* Get base address of i2s register */ + i2s_base = psNuI2s->i2s_base; + psNuI2sDai = &psNuI2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_i2s_tx_cb; + u32Src = (uint32_t)&psNuI2sDai->fifo[0]; + u32Dst = (uint32_t)&i2s_base->TXFIFO; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_i2s_rx_cb; + u32Src = (uint32_t)&i2s_base->RXFIFO; + u32Dst = (uint32_t)&psNuI2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = pfm_pdma_cb; + sChnCB.m_pvUserData = (void *)psNuI2s; + + nu_pdma_filtering_set(psNuI2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE); + result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid, &sChnCB); + + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid, // Channel ID + psNuI2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor + 0); // Interrupt assert when every SG-table done. + RT_ASSERT(result == RT_EOK); + } + result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + case 24: + case 32: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_i2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + rt_uint32_t real_samplerate; + + /* Open I2S */ + if (nu_i2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + real_samplerate = I2S_Open(psNuI2s->i2s_base, + (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos), + (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO, + I2S_FORMAT_I2S); + LOG_I("Open I2S."); + + /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */ + if (pconfig->samplerate != real_samplerate) + { + LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate); + } + I2S_EnableMCLK(psNuI2s->i2s_base, 12000000); + + /* Set unmute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_i2s_dai_setup: + + return result; +} + +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } + + } + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuI2s->config.channels; + caps->udata.config.samplebits = psNuI2s->config.samplebits; + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuI2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuI2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } + break; + + default: + result = -RT_ERROR; + break; + + } + + return result; +} + +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuI2s->AcodecOps->nu_acodec_mixer_control) + psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuI2s->config.samplerate != caps->udata.config.samplebits) + { + psNuI2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuI2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuI2s->config.samplerate != caps->udata.config.samplerate) + { + psNuI2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } + + if (bNeedReset) + { + return nu_i2s_start(audio, stream); + } + } + break; + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t nu_i2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Reset this module */ + SYS_ResetModule(psNuI2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Restart all: I2S and codec. */ + nu_i2s_stop(audio, stream); + if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + I2S_ENABLE_TXDMA(psNuI2s->i2s_base); + + /* Enable I2S Tx function */ + I2S_ENABLE_TX(psNuI2s->i2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + I2S_ENABLE_RXDMA(psNuI2s->i2s_base); + + /* Enable I2S Rx function */ + I2S_ENABLE_RX(psNuI2s->i2s_base); + + LOG_I("Start record."); + } + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + nu_i2s_dai_t psNuI2sDai = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + I2S_DISABLE_TXDMA(psNuI2s->i2s_base); + I2S_DISABLE_TX(psNuI2s->i2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + I2S_DISABLE_RXDMA(psNuI2s->i2s_base); + I2S_DISABLE_RX(psNuI2s->i2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid); + + /* Close I2S */ + if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) + { + I2S_DisableMCLK(psNuI2s->i2s_base); + I2S_Close(psNuI2s->i2s_base); + LOG_I("Close I2S."); + } + rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuI2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + info->buffer = (rt_uint8_t *)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ; + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + //rt_kprintf("info->buffer=%08x\n", (uint32_t)info->buffer); + //rt_kprintf("info->total_size=%d\n", (uint32_t)info->total_size); + //rt_kprintf("info->block_size=%d\n", (uint32_t)info->block_size); + //rt_kprintf("info->block_count=%d\n", (uint32_t)info->block_count); + + return; +} + +static struct rt_audio_ops nu_i2s_audio_ops = +{ + .getcaps = nu_i2s_getcaps, + .configure = nu_i2s_configure, + + .init = nu_i2s_init, + .start = nu_i2s_start, + .stop = nu_i2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_i2s_buffer_info +}; + +static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0) + { + goto nu_hw_i2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_i2s_pdma_allocate: + + return -(RT_ERROR); +} + +int rt_hw_i2s_init(void) +{ + int i, j; + nu_i2s_dai_t psNuI2sDai; + + for (j = (I2S_START + 1); j < I2S_CNT; j++) + { + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(pu8ptr != RT_NULL); + psNuI2sDai = &nu_i2s_arr[j].i2s_dais[i]; + psNuI2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuI2sDai->fifo != RT_NULL); + rt_kprintf("psNuI2sDai->fifo=%08x\n", (uint32_t)psNuI2sDai->fifo); + + psNuI2sDai->pdma_chanid = -1; + psNuI2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK); + + RT_ASSERT(nu_pdma_sgtbls_allocate(psNuI2sDai->pdma_chanid, &psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + nu_i2s_arr[j].audio.ops = &nu_i2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&nu_i2s_arr[j].audio, nu_i2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &nu_i2s_arr[j]); + } + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2s_init); +#endif //#if defined(BSP_USING_I2S) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h new file mode 100644 index 00000000000..26c4f01b7fc --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h @@ -0,0 +1,84 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_I2S_H__ +#define __DRV_I2S_H__ +#include "rtdevice.h" +#include "NuMicro.h" +#include "drv_pdma.h" + +#if !defined(NU_I2S_DMA_FIFO_SIZE) +#define NU_I2S_DMA_FIFO_SIZE (RT_AUDIO_RECORD_PIPE_SIZE) +#endif +#if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER) + +#define NU_I2S_DMA_BUF_BLOCK_NUMBER (2) +#endif +#if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 ) + #error "Please give an aligned definition" +#endif + +#define NU_I2S_DMA_BUF_BLOCK_SIZE (NU_I2S_DMA_FIFO_SIZE/NU_I2S_DMA_BUF_BLOCK_NUMBER) + +typedef enum +{ + NU_I2S_DAI_PLAYBACK, + NU_I2S_DAI_CAPTURE, + NU_I2S_DAI_CNT +} E_NU_I2S_DAI; + +typedef enum +{ + NU_ACODEC_ROLE_MASTER, + NU_ACODEC_ROLE_SLAVE, +} E_NU_ACODEC_ROLE; + +typedef struct +{ + char *name; + + E_NU_ACODEC_ROLE role; + + struct rt_audio_configure config; + + rt_err_t (*nu_acodec_init)(void); + + rt_err_t (*nu_acodec_reset)(void); + + rt_err_t (*nu_acodec_dsp_control)(struct rt_audio_configure *config); + + rt_err_t (*nu_acodec_mixer_control)(rt_uint32_t ui32Item, rt_uint32_t ui32Value); + + rt_err_t (*nu_acodec_mixer_query)(rt_uint32_t ui32Item, rt_uint32_t *ui32Value); + +} nu_acodec_ops; + +typedef nu_acodec_ops *nu_acodec_ops_t; + +struct nu_i2s_dai +{ + int32_t pdma_perp; + int32_t pdma_chanid; + rt_uint8_t *fifo; + int16_t fifo_block_idx; + nu_pdma_desc_t pdma_descs[NU_I2S_DMA_BUF_BLOCK_NUMBER]; +}; +typedef struct nu_i2s_dai *nu_i2s_dai_t; + +struct nu_i2s +{ + struct rt_audio_device audio; + struct rt_audio_configure config; + + char *name; + I2S_T *i2s_base; + uint32_t i2s_rst; + + struct nu_i2s_dai i2s_dais[NU_I2S_DAI_CNT]; + nu_acodec_ops_t AcodecOps; +}; +typedef struct nu_i2s *nu_i2s_t; +#endif /* __DRV_I2S_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c new file mode 100644 index 00000000000..0110defef4c --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c @@ -0,0 +1,434 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_LLSI) + +#include "drv_llsi.h" +#include "drv_pdma.h" +#include "nu_bitutil.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.llsi" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define MAKE_LLSI_NAME(x) #x +#define MAKE_PDMA_LLSI_TX(x) PDMA_LLSI##x##_TX +#define MAKE_PDMA_ELLSI_TX(x) PDMA_ELLSI##x##_TX + +#if defined(BSP_USING_PDMA_LLSI_TX) +#define MAKE_LLSI_PDMA_TX_REQ(t) .pdma_perp_tx = t +#else +#define MAKE_LLSI_PDMA_TX_REQ(t) +#endif +#define MAKE_LLSI_INSTANCE(x, t) \ + { \ + .name = MAKE_LLSI_NAME(llsi##x), \ + .base = LLSI##x, \ + .rst = LLSI##x##_RST, \ + .irqn = LLSI##x##_IRQn, \ + .modid = LLSI##x##_MODULE, \ + MAKE_LLSI_PDMA_TX_REQ(t) \ + }, +#define MAKE_ELLSI_INSTANCE(x, t) \ + { \ + .name = MAKE_LLSI_NAME(ellsi##x), \ + .base = (LLSI_T*)ELLSI##x, \ + .rst = ELLSI##x##_RST, \ + .irqn = ELLSI##x##_IRQn, \ + .modid = ELLSI##x##_MODULE, \ + MAKE_LLSI_PDMA_TX_REQ(t) \ + }, + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + LLSI_START = -1, +#if defined(BSP_USING_LLSI0) + LLSI0_IDX, +#endif +#if defined(BSP_USING_LLSI1) + LLSI1_IDX, +#endif +#if defined(BSP_USING_LLSI2) + LLSI2_IDX, +#endif +#if defined(BSP_USING_LLSI3) + LLSI3_IDX, +#endif +#if defined(BSP_USING_LLSI4) + LLSI4_IDX, +#endif +#if defined(BSP_USING_LLSI5) + LLSI5_IDX, +#endif +#if defined(BSP_USING_LLSI6) + LLSI6_IDX, +#endif +#if defined(BSP_USING_LLSI7) + LLSI7_IDX, +#endif +#if defined(BSP_USING_LLSI8) + LLSI8_IDX, +#endif +#if defined(BSP_USING_LLSI9) + LLSI9_IDX, +#endif +#if defined(BSP_USING_ELLSI0) + ELLSI0_IDX, +#endif + LLSI_CNT +}; + +struct nu_llsi +{ + struct rt_device device; + char *name; + LLSI_T *base; + uint32_t rst; + uint32_t modid; + IRQn_Type irqn; +#if defined(BSP_USING_PDMA_LLSI_TX) + uint32_t dma_flag; + + int32_t pdma_perp_tx; + int32_t pdma_chanid_tx; + + nu_pdma_desc_t pdma_tx_desc; +#endif + + S_LLSI_CONFIG_T config; +}; +typedef struct nu_llsi *nu_llsi_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static void dump_interrupt_event(uint32_t u32Status); +static void nu_llsi_isr(nu_llsi_t llsi); +static rt_err_t llsi_init(rt_device_t dev); +static rt_err_t llsi_open(rt_device_t dev, rt_uint16_t oflag); +static rt_err_t llsi_close(rt_device_t dev); +static rt_err_t llsi_control(rt_device_t dev, int cmd, void *args); +static rt_size_t llsi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); +static void nu_pdma_llsi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData); +static rt_size_t llsi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); +static int nu_hw_llsi_dma_allocate(nu_llsi_t psNuLlsi); +static rt_err_t llsi_register(struct rt_device *device, const char *name, void *user_data); + +/* Static Variables ----------------------------------------------------------*/ +static const S_LLSI_CONFIG_T s_sLlsiConfig = NU_LLSI_CONFIG_DEFAULT; + +static struct nu_llsi nu_llsi_arr [] = +{ +#if defined(BSP_USING_LLSI0) + MAKE_LLSI_INSTANCE(0, MAKE_PDMA_LLSI_TX(0)) +#endif +#if defined(BSP_USING_LLSI1) + MAKE_LLSI_INSTANCE(1, MAKE_PDMA_LLSI_TX(1)) +#endif +#if defined(BSP_USING_LLSI2) + MAKE_LLSI_INSTANCE(2, MAKE_PDMA_LLSI_TX(2)) +#endif +#if defined(BSP_USING_LLSI3) + MAKE_LLSI_INSTANCE(3, MAKE_PDMA_LLSI_TX(3)) +#endif +#if defined(BSP_USING_LLSI4) + MAKE_LLSI_INSTANCE(4, MAKE_PDMA_LLSI_TX(4)) +#endif +#if defined(BSP_USING_LLSI5) + MAKE_LLSI_INSTANCE(5, MAKE_PDMA_LLSI_TX(5)) +#endif +#if defined(BSP_USING_LLSI6) + MAKE_LLSI_INSTANCE(6, MAKE_PDMA_LLSI_TX(6)) +#endif +#if defined(BSP_USING_LLSI7) + MAKE_LLSI_INSTANCE(7, MAKE_PDMA_LLSI_TX(7)) +#endif +#if defined(BSP_USING_LLSI8) + MAKE_LLSI_INSTANCE(8, MAKE_PDMA_LLSI_TX(8)) +#endif +#if defined(BSP_USING_LLSI9) + MAKE_LLSI_INSTANCE(9, MAKE_PDMA_LLSI_TX(9)) +#endif +#if defined(BSP_USING_ELLSI0) + MAKE_ELLSI_INSTANCE(0, MAKE_PDMA_ELLSI_TX(0)) +#endif +}; + +static const char *szIR[] = +{ + "LLSI_RSTCIF - Reset Command Interrupt", + "LLSI_EMPIF - Transmit FIFO buffer is empty", + "LLSI_FULIF - Transmit FIFO buffer is full", + "LLSI_TXTHIF - FIFO buffer is less than or equal to the setting", + "LLSI_UNDFLIF - Valid data in FIFO is less than 3 bytes", + "LLSI_FENDIF - Finished data transmission", + "RESERVE", + "RESERVE", + "LLSI_LDT - Last Data Transmit", +}; + +#if defined(RT_USING_DEVICE_OPS) +static struct rt_device_ops llsi_ops = +{ + .init = llsi_init, + .open = llsi_open, + .close = llsi_close, + .read = llsi_read, + .write = llsi_write, + .control = llsi_control, +}; +#endif + +/* Functions Implementation --------------------------------------------------*/ +static void dump_interrupt_event(uint32_t u32Status) +{ + uint32_t idx; + while ((idx = nu_ctz(u32Status)) < 32) // Count Trailing Zeros == > Find First One + { + LOG_D("[%s]", szIR[idx]); + u32Status &= ~(1 << idx); + } +} + +static void nu_llsi_isr(nu_llsi_t llsi) +{ + LLSI_T *base = llsi->base; + uint32_t u32IntSts; + + u32IntSts = base->STATUS; + + /* Dump IR event */ + dump_interrupt_event(u32IntSts); + + base->STATUS = u32IntSts; +} +#define MAKE_LLSI_ISR(x) \ + void LLSI##x##_IRQHandler(void) \ + { \ + rt_interrupt_enter(); \ + nu_llsi_isr(&nu_llsi_arr[LLSI##x##_IDX]); \ + rt_interrupt_leave(); \ + } +#define MAKE_ELLSI_ISR(x) \ + void ELLSI##x##_IRQHandler(void) \ + { \ + rt_interrupt_enter(); \ + nu_llsi_isr(&nu_llsi_arr[ELLSI##x##_IDX]); \ + rt_interrupt_leave(); \ + } +#if defined(BSP_USING_LLSI0) + MAKE_LLSI_ISR(0); +#endif +#if defined(BSP_USING_LLSI1) + MAKE_LLSI_ISR(1); +#endif +#if defined(BSP_USING_LLSI2) + MAKE_LLSI_ISR(2); +#endif +#if defined(BSP_USING_LLSI3) + MAKE_LLSI_ISR(3); +#endif +#if defined(BSP_USING_LLSI4) + MAKE_LLSI_ISR(4); +#endif +#if defined(BSP_USING_LLSI5) + MAKE_LLSI_ISR(5); +#endif +#if defined(BSP_USING_LLSI6) + MAKE_LLSI_ISR(6); +#endif +#if defined(BSP_USING_LLSI7) + MAKE_LLSI_ISR(7); +#endif +#if defined(BSP_USING_LLSI8) + MAKE_LLSI_ISR(8); +#endif +#if defined(BSP_USING_LLSI9) + MAKE_LLSI_ISR(9); +#endif +#if defined(BSP_USING_ELLSI0) + MAKE_ELLSI_ISR(0); +#endif + +/* common device interface */ +static rt_err_t llsi_init(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t llsi_open(rt_device_t dev, rt_uint16_t oflag) +{ + nu_llsi_t psNuLlsi = (nu_llsi_t)dev; + + RT_ASSERT(psNuLlsi); + + /* Reset IP */ + SYS_ResetModule(psNuLlsi->rst); + + LLSI_OpenbyConfig(psNuLlsi->base, &psNuLlsi->config); + + /* Enable reset command function */ + LLSI_ENABLE_RESET_COMMAND(psNuLlsi->base); + + /* Unmask External LLSI Interrupt */ + NVIC_EnableIRQ(psNuLlsi->irqn); + + return RT_EOK; +} + +static rt_err_t llsi_close(rt_device_t dev) +{ + nu_llsi_t psNuLlsi = (nu_llsi_t)dev; + + RT_ASSERT(psNuLlsi); + + /* Mask External LLSI Interrupt */ + NVIC_DisableIRQ(psNuLlsi->irqn); + + LLSI_Close(psNuLlsi->base); + + return RT_EOK; +} + +static rt_err_t llsi_control(rt_device_t dev, int cmd, void *args) +{ + nu_llsi_t psNuLlsi = (nu_llsi_t)dev; + + RT_ASSERT(psNuLlsi); + + switch (cmd) + { + default: + { + S_LLSI_CONFIG_T *pconfig = (S_LLSI_CONFIG_T *)args; + + RT_ASSERT(args); + + rt_memcpy(&psNuLlsi->config, pconfig, sizeof(S_LLSI_CONFIG_T)); + } + break; + } + + return RT_EOK; +} + +static rt_size_t llsi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + nu_llsi_t psNuLlsi = (nu_llsi_t)dev; + rt_err_t ret = -RT_ERROR; + + RT_ASSERT(psNuLlsi); + + return 0; +} + +static void nu_pdma_llsi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of LLSI */ + LLSI_T *base = (LLSI_T *)pvUserData; + + /* Trigger PDMA transfer. */ + LLSI_ENABLE(base); +} + +static rt_size_t llsi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + nu_llsi_t psNuLlsi = (nu_llsi_t)dev; + rt_err_t ret = -RT_ERROR; + struct nu_pdma_chn_cb sChnCB; + + RT_ASSERT(psNuLlsi); + + /* Register llsi trigger callback function */ + sChnCB.m_eCBType = eCBType_Trigger; + sChnCB.m_pfnCBHandler = nu_pdma_llsi_tx_cb_trigger; + sChnCB.m_pvUserData = (void *)psNuLlsi->base; + ret = nu_pdma_callback_register(psNuLlsi->pdma_chanid_tx, &sChnCB); + RT_ASSERT(ret == RT_EOK); + + ret = nu_pdma_transfer(psNuLlsi->pdma_chanid_tx, + 32, + (uint32_t)buffer, + (uint32_t)&psNuLlsi->base->DATA, + RT_ALIGN(size, 4) / 4, + 0); // wait-forever + RT_ASSERT(ret == RT_EOK); + + return size; +} + +static int nu_hw_llsi_dma_allocate(nu_llsi_t psNuLlsi) +{ + rt_err_t ret = -RT_ERROR; + + RT_ASSERT(psNuLlsi); + + psNuLlsi->dma_flag = 0; + + /* Allocate LLSI nu_dma channel */ + if (psNuLlsi->pdma_perp_tx != NU_PDMA_UNUSED) + { + psNuLlsi->pdma_chanid_tx = nu_pdma_channel_allocate(psNuLlsi->pdma_perp_tx); + if (psNuLlsi->pdma_chanid_tx >= 0) + { + psNuLlsi->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + ret = RT_EOK; + } + } + + return ret; +} +static rt_err_t llsi_register(struct rt_device *device, const char *name, void *user_data) +{ + RT_ASSERT(device); + + device->type = RT_Device_Class_Miscellaneous; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; +#if defined(RT_USING_DEVICE_OPS) + device->ops = &llsi_ops; +#else + device->init = llsi_init; + device->open = llsi_open; + device->close = llsi_close; + device->read = llsi_read; + device->write = llsi_write; + device->control = llsi_control; +#endif + + device->user_data = user_data; + + return rt_device_register(device, name, RT_DEVICE_FLAG_WRONLY); +} + +/** + * Hardware LLSI Initialization + */ +int rt_hw_llsi_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (LLSI_START + 1); i < LLSI_CNT; i++) + { + nu_llsi_arr[i].config = s_sLlsiConfig; +#if defined(BSP_USING_PDMA_LLSI_TX) + ret = nu_hw_llsi_dma_allocate(&nu_llsi_arr[i]); + RT_ASSERT(ret == RT_EOK); +#endif + + ret = llsi_register(&nu_llsi_arr[i].device, nu_llsi_arr[i].name, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_llsi_init); +#endif //#if defined(BSP_USING_LLSI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.h new file mode 100644 index 00000000000..1a2b3ef58ce --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.h @@ -0,0 +1,44 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_LLSI_H__ +#define __DRV_LLSI_H__ +#include "NuMicro.h" + +typedef enum +{ + evR, + evG, + evB, + evCNT +} E_COLOR; + +typedef struct +{ + uint8_t r; + uint8_t g; + uint8_t b; +} S_LLSI_RGB; + +/* Default config for serial_configure structure */ +#define DEFAULT_PIXEL_COUNT 8 /* Number of LEDs in the strip */ +#define NU_LLSI_CONFIG_DEFAULT \ +{ \ + .u32LLSIMode = LLSI_MODE_PDMA, /*!< Transfer mode */ \ + .u32OutputFormat = LLSI_FORMAT_GRB, /*!< Output format */ \ + .sTimeInfo = { /*!< Timing information */ \ + .u32BusClock = __HSI, /*!< Bus clock in HZ */ \ + .u32TransferTimeNsec = 1200, /*!< Transfer time in nsec */ \ + .u32T0HTimeNsec = 300, /*!< T0H time in nsec */ \ + .u32T1HTimeNsec = 900, /*!< T1H time in nsec */ \ + .u32ResetTimeNsec = 50000 /*!< Reset time in nsec */ \ + }, \ + .u32PCNT = DEFAULT_PIXEL_COUNT, /*!< Frame size */ \ + .u32IDOS = LLSI_IDLE_LOW, /*!< Idle output state */ \ +} + +typedef void (*nu_llsi_event_handler_t)(void *pvData, uint32_t u32EvtMask); +#endif /* __DRV_LLSI_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h new file mode 100644 index 00000000000..b5e835774e3 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c new file mode 100644 index 00000000000..c8ee51a6e19 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c @@ -0,0 +1,1261 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_PDMA) + +#include "drv_pdma.h" +#include "drv_sys.h" +#include "nu_bitutil.h" +#include "rtdevice.h" +#include "rthw.h" +#include "rtthread.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.pdma" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#ifndef NU_PDMA_MEMFUN_ACTOR_MAX +#define NU_PDMA_MEMFUN_ACTOR_MAX (4) +#endif +#define NU_PDMA_SG_TBL_MAXSIZE (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T)) + +#define NU_PDMA_CH_MAX (PDMA_CNT*PDMA_CH_MAX) +#define NU_PDMA_CH_Msk ((1<>NU_PDMA_CHN_IDX_Pos) +#define NU_PDMA_GET_MOD_IDX(ch) ((ch&NU_PDMA_IDX_Msk)>>NU_PDMA_IDX_Pos) +#define NU_PDMA_GET_BASE(ch) ((PDMA_T *)nu_pdma_arr[NU_PDMA_GET_MOD_IDX(ch)].m_module.m_pvBase) +#define NU_PDMA_GET_ARRAY_IDX(iModChnID) ((NU_PDMA_GET_IDX(iModChnID)*PDMA_CH_MAX)+NU_PDMA_GET_CHN_ID(iModChnID)) +#define DEF_SGTBL_TOKEN_NUM (RT_ALIGN(NU_PDMA_SGTBL_POOL_SIZE, 32) / 32) + +#define DEFINE_NU_PDMA(_idx) \ + [(_idx)] = \ + { \ + .m_module = { \ + .name = "pdma" #_idx, \ + .m_pvBase = (void *)PDMA##_idx, \ + .u32RstId = PDMA##_idx##_RST,\ + .eIRQn = PDMA##_idx##_IRQn \ + } \ + } + +/* Types / Structures ---------------------------------------------------------*/ +struct nu_pdma_periph_ctl +{ + uint32_t m_u32Peripheral; + nu_pdma_memctrl_t m_eMemCtl; +}; +typedef struct nu_pdma_periph_ctl nu_pdma_periph_ctl_t; + +struct nu_pdma_chn +{ + struct nu_pdma_chn_cb m_sCB_Event; + struct nu_pdma_chn_cb m_sCB_Trigger; + struct nu_pdma_chn_cb m_sCB_Disable; + + nu_pdma_desc_t *m_ppsSgtbl; + uint32_t m_u32WantedSGTblNum; + + uint32_t m_u32EventFilter; + uint32_t m_u32IdleTimeout_us; + nu_pdma_periph_ctl_t m_spPeripCtl; + +}; +typedef struct nu_pdma_chn nu_pdma_chn_t; + +struct nu_pdma_memfun_actor +{ + int m_i32ModChnID; + uint32_t m_u32Result; + rt_sem_t m_psSemMemFun; +} ; +typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t; + +struct nu_pdma +{ + const struct nu_module m_module; + uint32_t m_u32SGTblToken[DEF_SGTBL_TOKEN_NUM]; + DSCT_T *m_psSGTbl; +}; +typedef struct nu_pdma *nu_pdma_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static int nu_pdma_peripheral_query(uint32_t u32PeriphType); +static void nu_pdma_init(void); +static void nu_pdma_channel_enable(int i32ModChnID); +static void nu_pdma_channel_disable(int i32ModChnID); +static void nu_pdma_channel_reset(int i32ModChnID); +static rt_err_t nu_pdma_timeout_set(int i32ModChnID, int i32Timeout_us); +static void nu_pdma_periph_ctrl_fill(int i32ModChnID, int i32CtlPoolIdx); +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl); +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events); +static void nu_pdma_memfun_actor_init(void); +static int nu_pdma_memfun_employ(void); + +/* Static Variables ----------------------------------------------------------*/ +static volatile int nu_pdma_inited = 0; +static volatile uint32_t nu_pdma_chn_mask_arr[PDMA_CNT] = {0}; +static nu_pdma_chn_t nu_pdma_chn_arr[NU_PDMA_CH_MAX]; +static volatile uint32_t nu_pdma_memfun_actor_mask = 0; +static volatile uint32_t nu_pdma_memfun_actor_maxnum = 0; +static rt_sem_t nu_pdma_memfun_actor_pool_sem = RT_NULL; +static rt_mutex_t nu_pdma_memfun_actor_pool_lock = RT_NULL; + +static struct nu_pdma nu_pdma_arr[] = +{ + DEFINE_NU_PDMA(0), +}; + +static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] = +{ + // M2M + { PDMA_MEM, eMemCtl_SrcInc_DstInc }, + + // M2P + { PDMA_UART0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART4_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_USCI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_USCI1_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_QSPI0_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_SPI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI2_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_LLSI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI4_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI5_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI6_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI7_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI8_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_LLSI9_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_ELLSI0_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix }, + + // P2M + { PDMA_UART0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART3_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART4_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_USCI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_USCI1_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_QSPI0_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_SPI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI2_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc }, +}; + +static struct nu_pdma_memfun_actor nu_pdma_memfun_actor_arr[NU_PDMA_MEMFUN_ACTOR_MAX]; + +/* Functions Implementation --------------------------------------------------*/ +int nu_pdma_non_transfer_count_get(int32_t i32ModChnID); +#define NU_PERIPHERAL_SIZE ( sizeof(g_nu_pdma_peripheral_ctl_pool) / sizeof(nu_pdma_periph_ctl_t) ) + +static int nu_pdma_check_is_nonallocated(uint32_t i32ModChnID) +{ + uint32_t mod_idx = NU_PDMA_GET_MOD_IDX(i32ModChnID); + + RT_ASSERT(mod_idx < PDMA_CNT); + return !(nu_pdma_chn_mask_arr[mod_idx] & (1 << NU_PDMA_GET_MOD_CHIDX(i32ModChnID))); +} + +static int nu_pdma_peripheral_query(uint32_t u32PeriphType) +{ + int idx = 0; + + while (idx < NU_PERIPHERAL_SIZE) + { + if (g_nu_pdma_peripheral_ctl_pool[idx].m_u32Peripheral == u32PeriphType) + return idx; + idx++; + } + return -1; +} + +static void nu_pdma_periph_ctrl_fill(int i32ModChnID, int i32CtlPoolIdx) +{ + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)]; + + psPdmaChann->m_spPeripCtl.m_u32Peripheral = NU_PDMA_GET_REQ_SRC_ID(g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_u32Peripheral); + psPdmaChann->m_spPeripCtl.m_eMemCtl = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_eMemCtl; +} + +/** + * Hardware PDMA Initialization + */ +static void nu_pdma_init(void) +{ + int i, latest = 0; + if (nu_pdma_inited) + return; + + rt_memset(nu_pdma_chn_arr, 0x00, sizeof(nu_pdma_chn_arr)); + + for (i = (PDMA_START + 1); i < PDMA_CNT; i++) + { + PDMA_T *pdma = (PDMA_T *)nu_pdma_arr[i].m_module.m_pvBase; + nu_pdma_chn_mask_arr[i] = ~(NU_PDMA_CH_Msk); + + nu_pdma_arr[i].m_psSGTbl = rt_malloc_align(sizeof(DSCT_T) * NU_PDMA_SGTBL_POOL_SIZE, 32); + RT_ASSERT(nu_pdma_arr[i].m_psSGTbl); + + /* Initialize sg table array. */ + rt_memset(nu_pdma_arr[i].m_psSGTbl, 0x00, sizeof(DSCT_T) * NU_PDMA_SGTBL_POOL_SIZE); + + /* Initialize sg table token pool. */ + rt_memset(&nu_pdma_arr[i].m_u32SGTblToken[0], 0xff, sizeof(uint32_t)*DEF_SGTBL_TOKEN_NUM); + if (NU_PDMA_SGTBL_POOL_SIZE % 32) + { + latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32; + nu_pdma_arr[i].m_u32SGTblToken[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ; + } + + SYS_ResetModule(nu_pdma_arr[i].m_module.u32RstId); + + /* Initialize PDMA setting */ + PDMA_Open(pdma, PDMA_CH_Msk); + PDMA_Close(pdma); + + /* Enable PDMA interrupt */ + NVIC_EnableIRQ(nu_pdma_arr[i].m_module.eIRQn); + + /* Assign first SG table address as PDMA SG table base address */ + pdma->SCATBA = (uint32_t)nu_pdma_arr[i].m_psSGTbl; + rt_kprintf("Set %s SCATBA address to 0x%08x.\n", nu_pdma_arr[i].m_module.name, pdma->SCATBA); + } + + nu_pdma_inited = 1; +} + +static inline void nu_pdma_channel_enable(int i32ModChnID) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + int u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ModChnID); + + /* Clean descriptor table control register. */ + pdma->DSCT[u32ModChannId].CTL = 0UL; + + /* Enable the channel */ + pdma->CHCTL |= (1 << u32ModChannId); +} + +static inline void nu_pdma_channel_disable(int i32ModChnID) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + + pdma->CHCTL &= ~(1 << NU_PDMA_GET_MOD_CHIDX(i32ModChnID)); +} + +static inline void nu_pdma_channel_reset(int i32ModChnID) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + int u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ModChnID); + + pdma->CHRST = (1 << u32ModChannId); + + /* Wait for cleared channel CHCTL. */ + while ((pdma->CHCTL & (1 << u32ModChannId))); +} + +void nu_pdma_channel_reset_user(int i32ChannID) +{ + nu_pdma_channel_reset(i32ChannID); +} + +void nu_pdma_channel_terminate(int i32ModChnID) +{ + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_pdma_channel_terminate; + + LOG_I("[%s] %d", __func__, i32ModChnID); + + /* Reset specified channel. */ + nu_pdma_channel_reset(i32ModChnID); + + /* Enable specified channel after reset. */ + nu_pdma_channel_enable(i32ModChnID); + +exit_pdma_channel_terminate: + + return; +} + +static rt_err_t nu_pdma_timeout_set(int i32ModChnID, int i32Timeout_us) +{ + rt_err_t ret = RT_EINVAL; + PDMA_T *pdma = NULL; + uint32_t u32ModChannId; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_timeout_set; + + pdma = NU_PDMA_GET_BASE(i32ModChnID); + + u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ModChnID); + + nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_u32IdleTimeout_us = i32Timeout_us; + + if (i32Timeout_us) + { + uint32_t u32ToClk_Max = 1000000 / (CLK_GetHCLKFreq() / (1 << 8)); + uint32_t u32Divider = (i32Timeout_us / u32ToClk_Max) / (1 << 16); + uint32_t u32TOutCnt = (i32Timeout_us / u32ToClk_Max) % (1 << 16); + + LOG_I("CLK_GetHCLKFreq(): %d, u32ToClk_Max: %d, u32Divider: %d, u32TOutCnt:%d", + CLK_GetHCLKFreq(), u32ToClk_Max, u32Divider, u32TOutCnt); + + PDMA_DisableTimeout(pdma, 1 << u32ModChannId); + PDMA_EnableInt(pdma, u32ModChannId, PDMA_INT_TIMEOUT); // Interrupt type + + if (u32Divider > 7) + { + u32Divider = 7; + u32TOutCnt = (1 << 16); + } + + if (u32ModChannId < 8) + pdma->TOUTPSC0_7 = (pdma->TOUTPSC0_7 & ~(0x7ul << (PDMA_TOUTPSC0_7_TOUTPSC0_Pos * u32ModChannId))) | (u32Divider << (PDMA_TOUTPSC0_7_TOUTPSC0_Pos * u32ModChannId)); + else + pdma->TOUTPSC8_15 = (pdma->TOUTPSC8_15 & ~(0x7ul << (PDMA_TOUTPSC8_15_TOUTPSC8_Pos * (u32ModChannId % 8)))) | (u32Divider << (PDMA_TOUTPSC8_15_TOUTPSC8_Pos * (u32ModChannId % 8))); + + PDMA_SetTimeOut(pdma, u32ModChannId, 1, u32TOutCnt); + + ret = RT_EOK; + } + else + { + PDMA_DisableInt(pdma, u32ModChannId, PDMA_INT_TIMEOUT); // Interrupt type + PDMA_DisableTimeout(pdma, 1 << u32ModChannId); + } + +exit_nu_pdma_timeout_set: + + return -(ret); +} + +int nu_pdma_channel_allocate(int32_t i32PeripType) +{ + int i32PeripCtlIdx, j; + + nu_pdma_init(); + + if ((j = NU_PDMA_GET_IDX(i32PeripType)) >= PDMA_CNT) + goto exit_nu_pdma_channel_allocate; + + if ((i32PeripCtlIdx = nu_pdma_peripheral_query(i32PeripType)) < 0) + goto exit_nu_pdma_channel_allocate; + + for (; j < PDMA_CNT; j++) + { + pdma_chid_t mod_chn_id; + + /* Find the position of first '0' in nu_pdma_chn_mask_arr[j]. */ + mod_chn_id.u16ChnIdx = nu_cto(nu_pdma_chn_mask_arr[j]); + if (mod_chn_id.u16ChnIdx < PDMA_CH_MAX) + { + mod_chn_id.u16ModIdx = j; + + nu_pdma_chn_mask_arr[j] |= (1 << mod_chn_id.u16ChnIdx); + + rt_memset(&nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(mod_chn_id.u32ChID)], 0x00, sizeof(nu_pdma_chn_t)); + + /* Set idx number of g_nu_pdma_peripheral_ctl_pool */ + nu_pdma_periph_ctrl_fill(mod_chn_id.u32ChID, i32PeripCtlIdx); + + /* Reset channel */ + nu_pdma_channel_terminate(mod_chn_id.u32ChID); + + return mod_chn_id.u32ChID; + } + } + +exit_nu_pdma_channel_allocate: + + // No channel available + return -(RT_ERROR); +} + +rt_err_t nu_pdma_channel_free(int i32ModChnID) +{ + rt_err_t ret = RT_EINVAL; + + if (!nu_pdma_inited) + goto exit_nu_pdma_channel_free; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_channel_free; + + if ((NU_PDMA_GET_MOD_IDX(i32ModChnID) < NU_PDMA_CH_MAX) && (NU_PDMA_GET_MOD_IDX(i32ModChnID) >= 0)) + { + nu_pdma_chn_mask_arr[NU_PDMA_GET_MOD_IDX(i32ModChnID)] &= ~(1 << NU_PDMA_GET_MOD_CHIDX(i32ModChnID)); + nu_pdma_channel_disable(i32ModChnID); + ret = RT_EOK; + } + +exit_nu_pdma_channel_free: + + return -(ret); +} + +rt_err_t nu_pdma_filtering_set(int i32ModChnID, uint32_t u32EventFilter) +{ + rt_err_t ret = RT_EINVAL; + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_filtering_set; + + nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_u32EventFilter = u32EventFilter; + + ret = RT_EOK; + +exit_nu_pdma_filtering_set: + + return -(ret) ; +} + +uint32_t nu_pdma_filtering_get(int i32ModChnID) +{ + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_filtering_get; + + return nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_u32EventFilter; + +exit_nu_pdma_filtering_get: + + return 0; +} + +rt_err_t nu_pdma_callback_register(int i32ModChnID, nu_pdma_chn_cb_t psChnCb) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_chn_cb_t psChnCb_Current = RT_NULL; + + RT_ASSERT(psChnCb != RT_NULL); + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_callback_register; + + switch (psChnCb->m_eCBType) + { + case eCBType_Event: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Event; + break; + case eCBType_Trigger: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Trigger; + break; + case eCBType_Disable: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Disable; + break; + default: + goto exit_nu_pdma_callback_register; + } + + psChnCb_Current->m_pfnCBHandler = psChnCb->m_pfnCBHandler; + psChnCb_Current->m_pvUserData = psChnCb->m_pvUserData; + + ret = RT_EOK; + +exit_nu_pdma_callback_register: + + return -(ret) ; +} + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ModChnID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack) +{ + nu_pdma_chn_cb_t psChnCb_Current = RT_NULL; + struct nu_pdma_chn_cb sChnCB_Tmp; + + RT_ASSERT(psChnCb_Hijack != NULL); + + sChnCB_Tmp.m_pfnCBHandler = RT_NULL; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_callback_hijack; + + switch (eCBType) + { + case eCBType_Event: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Event; + break; + case eCBType_Trigger: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Trigger; + break; + case eCBType_Disable: + psChnCb_Current = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_sCB_Disable; + break; + default: + goto exit_nu_pdma_callback_hijack; + } + sChnCB_Tmp.m_pfnCBHandler = psChnCb_Current->m_pfnCBHandler; + sChnCB_Tmp.m_pvUserData = psChnCb_Current->m_pvUserData; + + /* Update */ + psChnCb_Current->m_pfnCBHandler = psChnCb_Hijack->m_pfnCBHandler; + psChnCb_Current->m_pvUserData = psChnCb_Hijack->m_pvUserData; + + /* Restore */ + psChnCb_Hijack->m_pfnCBHandler = sChnCB_Tmp.m_pfnCBHandler; + psChnCb_Hijack->m_pvUserData = sChnCB_Tmp.m_pvUserData; + +exit_nu_pdma_callback_hijack: + + return sChnCB_Tmp.m_pfnCBHandler; +} + +int nu_pdma_non_transfer_count_get(int32_t i32ModChnID) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + return ((pdma->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ModChnID)].CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1; +} + +int nu_pdma_transferred_byte_get(int32_t i32ModChnID, int32_t i32TriggerByteLen) +{ + int i32BitWidth = 0; + int cur_txcnt = 0; + PDMA_T *pdma; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_transferred_byte_get; + + pdma = NU_PDMA_GET_BASE(i32ModChnID); + + i32BitWidth = pdma->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ModChnID)].CTL & PDMA_DSCT_CTL_TXWIDTH_Msk; + i32BitWidth = (i32BitWidth == PDMA_WIDTH_8) ? 1 : (i32BitWidth == PDMA_WIDTH_16) ? 2 : (i32BitWidth == PDMA_WIDTH_32) ? 4 : 0; + + cur_txcnt = nu_pdma_non_transfer_count_get(i32ModChnID); + + return (i32TriggerByteLen - (cur_txcnt) * i32BitWidth); + +exit_nu_pdma_transferred_byte_get: + + return -1; +} + +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ModChnID) +{ + nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_channel_memctrl_get; + + eMemCtrl = nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_spPeripCtl.m_eMemCtl; + +exit_nu_pdma_channel_memctrl_get: + + return eMemCtrl; +} + +rt_err_t nu_pdma_channel_memctrl_set(int i32ModChnID, nu_pdma_memctrl_t eMemCtrl) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)]; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_channel_memctrl_set; + else if ((eMemCtrl < eMemCtl_SrcFix_DstFix) || (eMemCtrl > eMemCtl_SrcInc_DstInc)) + goto exit_nu_pdma_channel_memctrl_set; + + /* PDMA_MEM/SAR_FIX/BURST mode is not supported. */ + if ((psPdmaChann->m_spPeripCtl.m_u32Peripheral == PDMA_MEM) && + ((eMemCtrl == eMemCtl_SrcFix_DstInc) || (eMemCtrl == eMemCtl_SrcFix_DstFix))) + goto exit_nu_pdma_channel_memctrl_set; + + nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_spPeripCtl.m_eMemCtl = eMemCtrl; + + ret = RT_EOK; + +exit_nu_pdma_channel_memctrl_set: + + return -(ret); +} + +static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu32SrcCtl, uint32_t *pu32DstCtl) +{ + switch ((int)eMemCtl) + { + case eMemCtl_SrcFix_DstFix: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcFix_DstInc: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_INC; + break; + case eMemCtl_SrcInc_DstFix: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcInc_DstInc: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_INC; + break; + default: + break; + } +} +rt_err_t nu_pdma_desc_setup(int i32ModChnID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, + uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent) + { + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + PDMA_T *pdma = NULL; + int isPdmaDescReg = 0; + + uint32_t u32SrcCtl = 0; + uint32_t u32DstCtl = 0; + + rt_err_t ret = RT_EINVAL; + + if (!dma_desc) + goto exit_nu_pdma_desc_setup; + else if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_desc_setup; + else if (!(u32DataWidth == 8 || u32DataWidth == 16 || u32DataWidth == 32)) + goto exit_nu_pdma_desc_setup; + else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8))) + goto exit_nu_pdma_desc_setup; + else if (i32TransferCnt > NU_PDMA_MAX_TXCNT) + goto exit_nu_pdma_desc_setup; + + pdma = NU_PDMA_GET_BASE(i32ModChnID); + + for (int i = 0; i < PDMA_CH_MAX; i++) + { + if ((nu_pdma_desc_t)&pdma->DSCT[i] == dma_desc) + { + isPdmaDescReg = 1; + break; + } + } + + psPeriphCtl = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_spPeripCtl; + + nu_pdma_channel_memctrl_fill(psPeriphCtl->m_eMemCtl, &u32SrcCtl, &u32DstCtl); + + dma_desc->CTL = ((i32TransferCnt - 1) << PDMA_DSCT_CTL_TXCNT_Pos) | + ((u32DataWidth == 8) ? PDMA_WIDTH_8 : (u32DataWidth == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32) | + u32SrcCtl | + u32DstCtl | + ((isPdmaDescReg) ? PDMA_OP_STOP : PDMA_OP_BASIC); + + dma_desc->SA = u32AddrSrc; + dma_desc->DA = u32AddrDst; + dma_desc->NEXT = 0; /* Terminating node by default. */ + + if (psPeriphCtl->m_u32Peripheral == PDMA_MEM) + { + /* For M2M transfer */ + dma_desc->CTL |= (PDMA_REQ_BURST | PDMA_BURST_32); + } + else + { + /* For P2M and M2P transfer */ + dma_desc->CTL |= (PDMA_REQ_SINGLE); + } + + if (next) + { + /* Link to Next and modify to scatter-gather DMA mode. */ + dma_desc->NEXT = (uint32_t)next - (pdma->SCATBA); + dma_desc->CTL = (dma_desc->CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + } + if (u32BeSilent) + dma_desc->CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + + ret = RT_EOK; + +exit_nu_pdma_desc_setup: + + return -(ret); +} + +static int nu_pdma_sgtbls_token_allocate(nu_pdma_t psPDMA) +{ + int idx, i; + + for (i = 0; i < DEF_SGTBL_TOKEN_NUM; i++) + { + if ((idx = nu_ctz(psPDMA->m_u32SGTblToken[i])) != 32) + { + psPDMA->m_u32SGTblToken[i] &= ~(1 << idx); + idx += i * 32; + + return idx; + } + } + return -1; +} + +static void nu_pdma_sgtbls_token_free(nu_pdma_t psPDMA, nu_pdma_desc_t psSgtbls) +{ + int idx = (int)(psSgtbls - &psPDMA->m_psSGTbl[0]); + RT_ASSERT(idx >= 0); + RT_ASSERT((idx + 1) <= NU_PDMA_SGTBL_POOL_SIZE); + psPDMA->m_u32SGTblToken[idx / 32] |= (1 << (idx % 32)); +} + +void nu_pdma_sgtbls_free(int i32ModChnID, nu_pdma_desc_t *ppsSgtbls, int num) +{ + int i; + rt_base_t level; + uint32_t mod_idx = NU_PDMA_GET_MOD_IDX(i32ModChnID); + + RT_ASSERT(ppsSgtbls != NULL); + RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE); + + level = rt_hw_interrupt_disable(); + + for (i = 0; i < num; i++) + { + if (ppsSgtbls[i] != NULL) + { + nu_pdma_sgtbls_token_free(&nu_pdma_arr[mod_idx], ppsSgtbls[i]); + } + + ppsSgtbls[i] = NULL; + } + + rt_hw_interrupt_enable(level); +} + +rt_err_t nu_pdma_sgtbls_allocate(int i32ModChnID, nu_pdma_desc_t *ppsSgtbls, int num) +{ + int i, idx; + rt_base_t level; + uint32_t mod_idx = NU_PDMA_GET_MOD_IDX(i32ModChnID); + + RT_ASSERT(ppsSgtbls); + RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE); + + level = rt_hw_interrupt_disable(); + + for (i = 0; i < num; i++) + { + ppsSgtbls[i] = NULL; + /* Get token. */ + if ((idx = nu_pdma_sgtbls_token_allocate(&nu_pdma_arr[mod_idx])) < 0) + { + rt_kprintf("No available sgtbl.\n"); + goto fail_nu_pdma_sgtbls_allocate; + } + + ppsSgtbls[i] = (nu_pdma_desc_t)&nu_pdma_arr[mod_idx].m_psSGTbl[idx]; + } + + rt_hw_interrupt_enable(level); + + return RT_EOK; + +fail_nu_pdma_sgtbls_allocate: + + /* Release allocated tables. */ + nu_pdma_sgtbls_free(i32ModChnID, ppsSgtbls, i); + + rt_hw_interrupt_enable(level); + + return -RT_ERROR; +} + +static rt_err_t nu_pdma_sgtbls_valid(int i32ModChnID, nu_pdma_desc_t head) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + + uint32_t node_addr; + nu_pdma_desc_t node = head; + + do + { + node_addr = (uint32_t)node; + if ((node_addr < pdma->SCATBA) || (node_addr - pdma->SCATBA) >= NU_PDMA_SG_LIMITED_DISTANCE) + { + rt_kprintf("The distance is over %d between 0x%08x and 0x%08x. \n", NU_PDMA_SG_LIMITED_DISTANCE, pdma->SCATBA, node); + rt_kprintf("Please use nu_pdma_sgtbl_allocate to allocate valid sg-table.\n"); + return RT_ERROR; + } + + node = (nu_pdma_desc_t)(node->NEXT + pdma->SCATBA); + + } + while (((uint32_t)node != pdma->SCATBA) && (node != head)); + + return RT_EOK; +} + +static void _nu_pdma_transfer(int i32ModChnID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)]; + + PDMA_DisableTimeout(pdma, 1 << NU_PDMA_GET_MOD_CHIDX(i32ModChnID)); + + PDMA_EnableInt(pdma, NU_PDMA_GET_MOD_CHIDX(i32ModChnID), PDMA_INT_TRANS_DONE); + + nu_pdma_timeout_set(i32ModChnID, u32IdleTimeout_us); + + /* Set scatter-gather mode and head */ + /* Take care the head structure, you should make sure cache-coherence. */ + PDMA_SetTransferMode(pdma, + NU_PDMA_GET_MOD_CHIDX(i32ModChnID), + u32Peripheral, + (head->NEXT != 0) ? 1 : 0, + (uint32_t)head); + + /* If peripheral is M2M, trigger it. */ + if (u32Peripheral == PDMA_MEM) + { + PDMA_Trigger(pdma, NU_PDMA_GET_MOD_CHIDX(i32ModChnID)); + } + else if (psPdmaChann->m_sCB_Trigger.m_pfnCBHandler) + { + psPdmaChann->m_sCB_Trigger.m_pfnCBHandler(psPdmaChann->m_sCB_Trigger.m_pvUserData, psPdmaChann->m_sCB_Trigger.m_u32Reserved); + } +} + +static void _nu_pdma_sgtbls_free(int i32ModChnID, nu_pdma_chn_t *psPdmaChann) +{ + if (psPdmaChann->m_ppsSgtbl) + { + nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + psPdmaChann->m_ppsSgtbl = RT_NULL; + psPdmaChann->m_u32WantedSGTblNum = 0; + } +} + +static rt_err_t _nu_pdma_transfer_chain(int i32ModChnID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t u32TransferCnt, uint32_t u32IdleTimeout_us) +{ + int i = 0; + rt_err_t ret = RT_ERROR; + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)]; + + nu_pdma_memctrl_t eMemCtl = nu_pdma_channel_memctrl_get(i32ModChnID); + + rt_uint32_t u32Offset = 0; + rt_uint32_t u32TxCnt = 0; + + psPeriphCtl = &psPdmaChann->m_spPeripCtl; + + if (psPdmaChann->m_u32WantedSGTblNum != (u32TransferCnt / NU_PDMA_MAX_TXCNT + 1)) + { + if (psPdmaChann->m_u32WantedSGTblNum > 0) + { + nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + _nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann); + } + + psPdmaChann->m_u32WantedSGTblNum = u32TransferCnt / NU_PDMA_MAX_TXCNT + 1; + + psPdmaChann->m_ppsSgtbl = (nu_pdma_desc_t *) +rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 32); + + if (!psPdmaChann->m_ppsSgtbl) + goto exit__nu_pdma_transfer_chain; + + ret = nu_pdma_sgtbls_allocate(i32ModChnID, psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + if (ret != RT_EOK) + goto exit__nu_pdma_transfer_chain; + } + + for (i = 0; i < psPdmaChann->m_u32WantedSGTblNum; i++) + { + u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt; + + ret = nu_pdma_desc_setup(i32ModChnID, + psPdmaChann->m_ppsSgtbl[i], + u32DataWidth, + (eMemCtl & 0x2ul) ? u32AddrSrc + u32Offset : u32AddrSrc, /* Src address is Inc or not. */ + (eMemCtl & 0x1ul) ? u32AddrDst + u32Offset : u32AddrDst, /* Dst address is Inc or not. */ + u32TxCnt, + ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? RT_NULL : psPdmaChann->m_ppsSgtbl[i + 1], + ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? 0 : 1); // Silent, w/o TD interrupt + + if (ret != RT_EOK) + goto exit__nu_pdma_transfer_chain; + + u32TransferCnt -= u32TxCnt; + u32Offset += (u32TxCnt * u32DataWidth / 8); + } + + _nu_pdma_transfer(i32ModChnID, psPeriphCtl->m_u32Peripheral, psPdmaChann->m_ppsSgtbl[0], u32IdleTimeout_us); + + ret = RT_EOK; + + return ret; + +exit__nu_pdma_transfer_chain: + + _nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann); + + return -(ret); +} + +rt_err_t nu_pdma_transfer(int i32ModChnID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t u32TransferCnt, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + PDMA_T *pdma = NU_PDMA_GET_BASE(i32ModChnID); + nu_pdma_desc_t head; + nu_pdma_chn_t *psPdmaChann; + + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_transfer; + else if (!u32TransferCnt) + goto exit_nu_pdma_transfer; + else if (u32TransferCnt > NU_PDMA_MAX_TXCNT) + return _nu_pdma_transfer_chain(i32ModChnID, u32DataWidth, u32AddrSrc, u32AddrDst, u32TransferCnt, u32IdleTimeout_us); + + psPdmaChann = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)]; + psPeriphCtl = &psPdmaChann->m_spPeripCtl; + + head = &pdma->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ModChnID)]; + + ret = nu_pdma_desc_setup(i32ModChnID, + head, + u32DataWidth, + u32AddrSrc, + u32AddrDst, + u32TransferCnt, + RT_NULL, + 0); + if (ret != RT_EOK) + goto exit_nu_pdma_transfer; + + _nu_pdma_transfer(i32ModChnID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_transfer: + + return -(ret); +} + +rt_err_t nu_pdma_sg_transfer(int i32ModChnID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (!head) + goto exit_nu_pdma_sg_transfer; + else if (nu_pdma_check_is_nonallocated(i32ModChnID)) + goto exit_nu_pdma_sg_transfer; + else if ((ret = nu_pdma_sgtbls_valid(i32ModChnID, head)) != RT_EOK) /* Check SG-tbls. */ + goto exit_nu_pdma_sg_transfer; + + psPeriphCtl = &nu_pdma_chn_arr[NU_PDMA_GET_ARRAY_IDX(i32ModChnID)].m_spPeripCtl; + + _nu_pdma_transfer(i32ModChnID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_sg_transfer: + + return -(ret); +} + +void pdma_isr(PDMA_T *pdma, int idx) +{ + int i; + + uint32_t intsts = PDMA_GET_INT_STATUS(pdma); + uint32_t abtsts = PDMA_GET_ABORT_STS(pdma); + uint32_t tdsts = PDMA_GET_TD_STS(pdma); + uint32_t unalignsts = PDMA_GET_ALIGN_STS(pdma); + uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk; + uint32_t reqto_ch = (reqto >> PDMA_INTSTS_REQTOFn_Pos); + + int allch_sts = (reqto_ch | tdsts | abtsts | unalignsts); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) + { + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(pdma, abtsts); + } + if (intsts & PDMA_INTSTS_TDIF_Msk) + { + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(pdma, tdsts); + } + if (intsts & PDMA_INTSTS_ALIGNF_Msk) + { + // Clear all Unaligned flags + PDMA_CLR_ALIGN_FLAG(pdma, unalignsts); + } + if (reqto) + { + // Clear all Timeout flags + pdma->INTSTS = reqto; + } + while ((i = nu_ctz(allch_sts)) < PDMA_CH_MAX) + { + int module_id = idx; + int j = i + (module_id * PDMA_CH_MAX); + int ch_mask = (1 << i); + + if (nu_pdma_chn_mask_arr[module_id] & ch_mask) + { + int ch_event = 0; + nu_pdma_chn_t *dma_chn = &nu_pdma_chn_arr[j]; + + if (dma_chn->m_sCB_Event.m_pfnCBHandler) + { + if (abtsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_ABORT; + } + + if (tdsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_TRANSFER_DONE; + } + + if (unalignsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_ALIGNMENT; + } + + if (reqto_ch & ch_mask) + { + PDMA_DisableTimeout(pdma, ch_mask); + ch_event |= NU_PDMA_EVENT_TIMEOUT; + } + + if (dma_chn->m_sCB_Disable.m_pfnCBHandler) + dma_chn->m_sCB_Disable.m_pfnCBHandler(dma_chn->m_sCB_Disable.m_pvUserData, dma_chn->m_sCB_Disable.m_u32Reserved); + + if (dma_chn->m_u32EventFilter & ch_event) + dma_chn->m_sCB_Event.m_pfnCBHandler(dma_chn->m_sCB_Event.m_pvUserData, ch_event); + + if (reqto_ch & ch_mask) + nu_pdma_timeout_set(j, dma_chn->m_u32IdleTimeout_us); + + } + + } + allch_sts &= ~ch_mask; + + } +} + +void PDMA0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + pdma_isr(PDMA0, PDMA0_IDX); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void nu_pdma_memfun_actor_init(void) +{ + int i = 0 ; + nu_pdma_init(); + for (i = 0; i < NU_PDMA_MEMFUN_ACTOR_MAX; i++) + { + rt_memset(&nu_pdma_memfun_actor_arr[i], 0, sizeof(struct nu_pdma_memfun_actor)); + if (-(RT_ERROR) != (nu_pdma_memfun_actor_arr[i].m_i32ModChnID = nu_pdma_channel_allocate(PDMA_MEM))) + { + nu_pdma_memfun_actor_arr[i].m_psSemMemFun = rt_sem_create("memactor_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(nu_pdma_memfun_actor_arr[i].m_psSemMemFun != RT_NULL); + } + else + break; + } + if (i) + { + nu_pdma_memfun_actor_maxnum = i; + nu_pdma_memfun_actor_mask = ~(((1 << i) - 1)); + + nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO); + RT_ASSERT(nu_pdma_memfun_actor_pool_sem != RT_NULL); + + nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO); + RT_ASSERT(nu_pdma_memfun_actor_pool_lock != RT_NULL); + } +} + +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events) +{ + rt_err_t result = RT_EOK; + + nu_pdma_memfun_actor_t psMemFunActor = (nu_pdma_memfun_actor_t)pvUserData; + psMemFunActor->m_u32Result = u32Events; + + result = rt_sem_release(psMemFunActor->m_psSemMemFun); + RT_ASSERT(result == RT_EOK); +} + +static int nu_pdma_memfun_employ(void) +{ + int idx = -1 ; + rt_err_t result = RT_EOK; + + /* Headhunter */ + if (nu_pdma_memfun_actor_pool_sem && + ((result = rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER)) == RT_EOK)) + { + RT_ASSERT(result == RT_EOK); + + result = rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + /* Find the position of first '0' in nu_pdma_memfun_actor_mask. */ + idx = nu_cto(nu_pdma_memfun_actor_mask); + if (idx != 32) + { + nu_pdma_memfun_actor_mask |= (1 << idx); + } + else + { + idx = -1; + } + result = rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + RT_ASSERT(result == RT_EOK); + } + + return idx; +} + +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl) +{ + nu_pdma_memfun_actor_t psMemFunActor = NULL; + struct nu_pdma_chn_cb sChnCB; + rt_err_t result = RT_ERROR; + + int idx; + rt_size_t ret = 0; + + /* Employ actor */ + while ((idx = nu_pdma_memfun_employ()) < 0); + + psMemFunActor = &nu_pdma_memfun_actor_arr[idx]; + + /* Set PDMA memory control to eMemCtl. */ + nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ModChnID, eMemCtl); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_memfun_cb; + sChnCB.m_pvUserData = (void *)psMemFunActor; + + nu_pdma_filtering_set(psMemFunActor->m_i32ModChnID, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE); + nu_pdma_callback_register(psMemFunActor->m_i32ModChnID, &sChnCB); + + psMemFunActor->m_u32Result = 0; + + //rt_kprintf("idx=%d, src@%08x -> dest@%08x, u32DataWidth: %08x, u32TransferCnt:%d\n", + // idx, src, dest, u32DataWidth, u32TransferCnt); + + /* Trigger it */ + nu_pdma_transfer(psMemFunActor->m_i32ModChnID, + u32DataWidth, + (uint32_t)src, + (uint32_t)dest, + u32TransferCnt, + 0); + + /* Wait it done. */ + result = rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + /* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/ + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE) + { + ret += u32TransferCnt; + } + else + { + ret += (u32TransferCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ModChnID)); + } + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT) + { + nu_pdma_channel_terminate(psMemFunActor->m_i32ModChnID); + } + + result = rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + nu_pdma_memfun_actor_mask &= ~(1 << idx); + + result = rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + RT_ASSERT(result == RT_EOK); + + /* Fire actor */ + result = rt_sem_release(nu_pdma_memfun_actor_pool_sem); + RT_ASSERT(result == RT_EOK); + + return ret; +} + +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count) +{ + if (data_width == 8 || data_width == 16 || data_width == 32) + return nu_pdma_memfun(dest, src, data_width, transfer_count, eMemCtl_SrcInc_DstFix); + return 0; +} + +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count) +{ + int i = 0; + uint32_t u32Offset = 0; + uint32_t u32Remaining = count; + + for (i = 4; (i > 0) && (u32Remaining > 0) ; i >>= 1) + { + uint32_t u32src = (uint32_t)src + u32Offset; + uint32_t u32dest = (uint32_t)dest + u32Offset; + + if (((u32src % i) == (u32dest % i)) && + ((u32src % i) == 0) && + (RT_ALIGN_DOWN(u32Remaining, i) >= i)) + { + uint32_t u32TXCnt = u32Remaining / i; + if (u32TXCnt != nu_pdma_memfun((void *)u32dest, (void *)u32src, i * 8, u32TXCnt, eMemCtl_SrcInc_DstInc)) + goto exit_nu_pdma_memcpy; + + u32Offset += (u32TXCnt * i); + u32Remaining -= (u32TXCnt * i); + } + } + + if (count == u32Offset) + return dest; + +exit_nu_pdma_memcpy: + + return NULL; +} + +/** + * PDMA memfun actor initialization + */ +int rt_hw_pdma_memfun_init(void) +{ + nu_pdma_memfun_actor_init(); + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_pdma_memfun_init); +#endif //#if defined(BSP_USING_PDMA) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h new file mode 100644 index 00000000000..19b5da2216a --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h @@ -0,0 +1,109 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_PDMA_H__ +#define __DRV_PDMA_H__ +#include "rtconfig.h" +#include "rtthread.h" +#include "NuMicro.h" + +#ifndef NU_PDMA_SGTBL_POOL_SIZE +#define NU_PDMA_SGTBL_POOL_SIZE (16) +#endif + +enum +{ + PDMA_START = -1, + PDMA0_IDX, + PDMA_CNT +}; +#define NU_PDMA_CAP_NONE (0 << 0) + +#define NU_PDMA_EVENT_ABORT (1 << 0) +#define NU_PDMA_EVENT_TRANSFER_DONE (1 << 1) +#define NU_PDMA_EVENT_ALIGNMENT (1 << 2) +#define NU_PDMA_EVENT_TIMEOUT (1 << 3) +#define NU_PDMA_EVENT_ALL (NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) +#define NU_PDMA_EVENT_MASK NU_PDMA_EVENT_ALL +#define NU_PDMA_UNUSED (-1) +#define NU_PDMA_SG_LIMITED_DISTANCE ((PDMA_DSCT_NEXT_NEXT_Msk>>PDMA_DSCT_NEXT_NEXT_Pos) + 1) +#define NU_PDMA_MAX_TXCNT ((PDMA_DSCT_CTL_TXCNT_Msk>>PDMA_DSCT_CTL_TXCNT_Pos) + 1) + +typedef enum +{ + eMemCtl_SrcFix_DstFix, + eMemCtl_SrcFix_DstInc, + eMemCtl_SrcInc_DstFix, + eMemCtl_SrcInc_DstInc, + eMemCtl_Undefined = (-1) +} nu_pdma_memctrl_t; + +typedef DSCT_T *nu_pdma_desc_t; + +typedef void (*nu_pdma_cb_handler_t)(void *, uint32_t); + +typedef enum +{ + eCBType_Event, + eCBType_Trigger, + eCBType_Disable, + eCBType_Undefined = (-1) +} nu_pdma_cbtype_t; + +typedef struct +{ + union + { + uint32_t u32ChID; + struct + { + uint32_t u16ChnIdx : 16; + uint32_t u16ModIdx : 16; +#define NU_PDMA_CHN_IDX_Pos (0) +#define NU_PDMA_CHN_IDX_Msk (0xFFFF<> NU_PDMA_IDX_Pos) + +struct nu_pdma_chn_cb +{ + nu_pdma_cbtype_t m_eCBType; + nu_pdma_cb_handler_t m_pfnCBHandler; + void *m_pvUserData; + uint32_t m_u32Reserved; +}; +typedef struct nu_pdma_chn_cb *nu_pdma_chn_cb_t; + +int nu_pdma_channel_allocate(int32_t i32PeripType); +rt_err_t nu_pdma_channel_free(int i32ChannID); +rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_chn_cb_t psChnCb); +rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t i32TransferCnt, uint32_t u32IdleTimeout_us); +int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen); +void nu_pdma_channel_terminate(int i32ChannID); +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID); +rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl); + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack); +rt_err_t nu_pdma_filtering_set(int i32ChannID, uint32_t u32EventFilter); +uint32_t nu_pdma_filtering_get(int i32ChannID); + +// For scatter-gather DMA +rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent); +rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us); +rt_err_t nu_pdma_sgtbls_allocate(int i32ChannID, nu_pdma_desc_t *ppsSgtbls, int num); +void nu_pdma_sgtbls_free(int i32ChannID, nu_pdma_desc_t *ppsSgtbls, int num); + +// For memory actor +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count); +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count); +#endif /* __DRV_PDMA_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c new file mode 100644 index 00000000000..062ba753f68 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c @@ -0,0 +1,417 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_QSPI) + +#include "drv_spi.h" +#include "rtdef.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.qspi" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_QSPI0_PDMA) +#define QSPI0_PDMA_INIT \ + .pdma_perp_tx = PDMA_QSPI0_TX, \ + .pdma_perp_rx = PDMA_QSPI0_RX, +#else +#define QSPI0_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#else +#define QSPI0_PDMA_INIT +#endif + +#define DEFINE_NU_QSPI(_idx, _pdma_init) \ + { \ + .name = "qspi" #_idx, \ + .spi_base = (SPI_T *)QSPI##_idx, \ + .rstidx = QSPI##_idx##_RST, \ + _pdma_init \ + } + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + QSPI_START = -1, +#if defined(BSP_USING_QSPI0) + QSPI0_IDX, +#endif + QSPI_CNT +}; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_ssize_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name); + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_spi_ops nu_qspi_poll_ops = +{ + .configure = nu_qspi_bus_configure, + .xfer = nu_qspi_bus_xfer, +}; + +static struct nu_spi nu_qspi_arr [] = +{ +#if defined(BSP_USING_QSPI0) + DEFINE_NU_QSPI(0, QSPI0_PDMA_INIT), +#endif +}; /* qspi nu_qspi */ + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) + { + struct nu_spi *spi_bus; + rt_uint32_t u32SPIMode; + rt_uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_qspi_bus_configure; + } + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_qspi_bus_configure; + } + u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + LOG_W("%s clock max frequency is %dHz ( != %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0) + { + rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration)); + + QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_qspi_bus_configure: + + return -(ret); +} + +static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines) +{ + QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; + if (qspi_lines > 1) + { + if (tx) + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base); + break; + default: + LOG_E("Data line is not supported.\n"); + break; + } + } + else + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base); + break; + default: + LOG_E("Data line is not supported.\n"); + break; + } + } + } + else + { + QSPI_DISABLE_DUAL_MODE(qspi_base); + QSPI_DISABLE_QUAD_MODE(qspi_base); + } + return qspi_lines; +} + +static rt_ssize_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *qspi_bus; + struct rt_qspi_configuration *qspi_configuration; + struct rt_qspi_message *qspi_message; + rt_uint8_t u8last = 1; + rt_uint8_t bytes_per_word; + QSPI_T *qspi_base; + rt_uint32_t u32len = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(message != RT_NULL); + + qspi_bus = (struct nu_spi *) device->bus; + qspi_base = (QSPI_T *)qspi_bus->spi_base; + qspi_configuration = &qspi_bus->configuration; + + bytes_per_word = qspi_configuration->parent.data_width / 8; + + if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_HIGH(qspi_base); + } + else + { + QSPI_SET_SS_LOW(qspi_base); + } + } + + qspi_message = (struct rt_qspi_message *)message; + + /* Command + Address + Dummy + Data */ + /* Command stage */ + if (qspi_message->instruction.content != 0) + { + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &qspi_message->instruction.content, + RT_NULL, + 1, + 1); + } + if (qspi_message->address.size > 0) + { + rt_uint32_t u32ReversedAddr = 0; + rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8; + switch (u32AddrNumOfByte) + { + case 1: + u32ReversedAddr = (qspi_message->address.content & 0xff); + break; + case 2: + nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 3: + nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 4: + nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + default: + RT_ASSERT(0); + break; + } + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &u32ReversedAddr, + RT_NULL, + u32AddrNumOfByte, + 1); + } + if ((qspi_message->alternate_bytes.size > 0) && (qspi_message->alternate_bytes.size <= 4)) + { + rt_uint32_t u32AlternateByte = 0; + rt_uint32_t u32NumOfByte = qspi_message->alternate_bytes.size / 8; + switch (u32NumOfByte) + { + case 1: + u32AlternateByte = (qspi_message->alternate_bytes.content & 0xff); + break; + case 2: + nu_set16_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + case 3: + nu_set24_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + case 4: + nu_set32_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + default: + RT_ASSERT(0); + break; + } + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32AlternateByte, RT_NULL, qspi_message->alternate_bytes.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &u32AlternateByte, + RT_NULL, + u32NumOfByte, + 1); + } + if (qspi_message->dummy_cycles > 0) + { + qspi_bus->dummy[0] = 0x00; + + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy[0], RT_NULL, u8last); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &qspi_bus->dummy[0], + RT_NULL, + qspi_message->dummy_cycles / (8 / u8last), + 1); + } + + if (message->length > 0) + { + /* Data stage */ + nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) message->send_buf, + (rt_uint8_t *) message->recv_buf, + message->length, + bytes_per_word); + u32len = message->length; + } + else + { + u32len = 1; + } + + if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_LOW(qspi_base); + } + else + { + QSPI_SET_SS_HIGH(qspi_base); + } + } + + return u32len; +} + +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name) +{ + return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_qspi_init(void) +{ + rt_uint8_t i; + + for (i = (QSPI_START + 1); i < QSPI_CNT; i++) + { + SYS_ResetModule(nu_qspi_arr[i].rstidx); + + nu_qspi_arr[i].dummy = rt_malloc_align(RT_ALIGN_SIZE, RT_ALIGN_SIZE); + RT_ASSERT(nu_qspi_arr[i].dummy); +#if defined(BSP_USING_SPI_PDMA) + nu_qspi_arr[i].pdma_chanid_tx = -1; + nu_qspi_arr[i].pdma_chanid_rx = -1; +#endif +#if defined(BSP_USING_QSPI_PDMA) + if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK) + { + LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name); + } + } +#endif + nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_qspi_init); + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()) +{ + struct rt_qspi_device *qspi_device = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4); + + qspi_device = (struct rt_qspi_device *) +rt_malloc(sizeof(struct rt_qspi_device)); + if (qspi_device == RT_NULL) + { + LOG_E("no memory, qspi bus attach device failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + qspi_device->enter_qspi_mode = enter_qspi_mode; + qspi_device->exit_qspi_mode = exit_qspi_mode; + qspi_device->config.qspi_dl_width = data_line_width; + + result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL); + +__exit: + if (result != RT_EOK) + { + if (qspi_device) + { + rt_free(qspi_device); + } + } + + return result; +} +#endif //#if defined(BSP_USING_QSPI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.h new file mode 100644 index 00000000000..fb13f5f66bf --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.h @@ -0,0 +1,12 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_QSPI_H__ +#define __DRV_QSPI_H__ +#include "rtdevice.h" + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()); +#endif /* __DRV_QSPI_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c new file mode 100644 index 00000000000..4b470ff6e3b --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c @@ -0,0 +1,242 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_RTC) + +#include "NuMicro.h" +#include "sys/time.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.rtc" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define CONV_TO_TM_YEAR(year) ((year) - 1900) +#define CONV_TO_TM_MON(mon) ((mon) - 1) + +#define CONV_FROM_TM_YEAR(tm_year) ((tm_year) + 1900) +#define CONV_FROM_TM_MON(tm_mon) ((tm_mon) + 1) + +#define RTC_TM_UPPER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2038), \ + .tm_mon = CONV_TO_TM_MON(1), \ + .tm_mday = 19, \ + .tm_hour = 3, \ + .tm_min = 14, \ + .tm_sec = 07, \ +} +#define RTC_TM_LOWER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2000), \ + .tm_mon = CONV_TO_TM_MON(1), \ + .tm_mday = 1, \ + .tm_hour = 0, \ + .tm_min = 0, \ + .tm_sec = 0, \ +} + +/* Types / Structures ---------------------------------------------------------*/ + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args); +static rt_err_t nu_rtc_is_date_valid(const time_t t); +static rt_err_t nu_rtc_init(void); +#if defined(RT_USING_ALARM) +static void nu_rtc_alarm_reset(void); +#endif + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_device device_rtc; + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_rtc_init(void) +{ + /* hw rtc initialise */ + RTC_Open(NULL); + RTC_DisableInt(RTC_INTEN_ALMIEN_Msk | RTC_INTEN_TICKIEN_Msk); +#if defined(RT_USING_ALARM) + nu_rtc_alarm_reset(); + RTC_EnableInt(RTC_INTEN_ALMIEN_Msk); + NVIC_EnableIRQ(RTC_IRQn); +#endif + + return RT_EOK; +} +#if defined(RT_USING_ALARM) +/* Reset alarm settings to avoid the unwanted values remain in rtc registers. */ +static void nu_rtc_alarm_reset(void) +{ + S_RTC_TIME_DATA_T alarm; + + /* Reset alarm time and calendar. */ + alarm.u32Year = RTC_YEAR2000; + alarm.u32Month = 0; + alarm.u32Day = 0; + alarm.u32Hour = 0; + alarm.u32Minute = 0; + alarm.u32Second = 0; + alarm.u32TimeScale = RTC_CLOCK_24; + + RTC_SetAlarmDateAndTime(&alarm); + + /* Reset alarm time mask and calendar mask. */ + RTC_SetAlarmDateMask(0, 0, 0, 0, 0, 0); + RTC_SetAlarmTimeMask(0, 0, 0, 0, 0, 0); + + /* Clear alarm flag for safe */ + RTC_CLEAR_ALARM_INT_FLAG(); +} +#endif + +/* rtc device driver initialise. */ +int rt_hw_rtc_init(void) +{ + rt_err_t ret; + + nu_rtc_init(); + + /* register rtc device IO operations */ + device_rtc.type = RT_Device_Class_RTC; + device_rtc.init = NULL; + device_rtc.open = NULL; + device_rtc.close = NULL; + device_rtc.control = nu_rtc_control; + device_rtc.read = NULL; + device_rtc.write = NULL; + + device_rtc.user_data = RT_NULL; + device_rtc.rx_indicate = RT_NULL; + device_rtc.tx_complete = RT_NULL; + + ret = rt_device_register(&device_rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_rtc_init); + +static rt_err_t nu_rtc_is_date_valid(const time_t t) +{ + static struct tm tm_upper = RTC_TM_UPPER_BOUND; + static struct tm tm_lower = RTC_TM_LOWER_BOUND; + static time_t t_upper, t_lower; + static rt_bool_t initialised = RT_FALSE; + + if (!initialised) + { + t_upper = timegm((struct tm *)&tm_upper); + t_lower = timegm((struct tm *)&tm_lower); + initialised = RT_TRUE; + } + if ((t > t_upper) || (t < t_lower)) + return -(RT_EINVAL); + + return RT_EOK; +} + +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) +{ + struct tm tm_out, tm_in; + time_t *time; + S_RTC_TIME_DATA_T hw_time; +#if defined(RT_USING_ALARM) + + struct rt_rtc_wkalarm *wkalarm; + S_RTC_TIME_DATA_T hw_alarm; +#endif + + if ((dev == NULL) || (args == NULL)) + return -(RT_EINVAL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + + time = (time_t *)args; + RTC_GetDateAndTime(&hw_time); + + tm_out.tm_year = CONV_TO_TM_YEAR(hw_time.u32Year); + tm_out.tm_mon = CONV_TO_TM_MON(hw_time.u32Month); + tm_out.tm_mday = hw_time.u32Day; + tm_out.tm_hour = hw_time.u32Hour; + tm_out.tm_min = hw_time.u32Minute; + tm_out.tm_sec = hw_time.u32Second; + *time = timegm(&tm_out); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + + time = (time_t *) args; + + if (nu_rtc_is_date_valid(*time) != RT_EOK) + return -(RT_ERROR); + + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; + hw_time.u32TimeScale = RTC_CLOCK_24; + hw_time.u32AmPm = 0; + + RTC_SetDateAndTime(&hw_time); + break; +#if defined(RT_USING_ALARM) + case RT_DEVICE_CTRL_RTC_GET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + RTC_GetAlarmDateAndTime(&hw_alarm); + + wkalarm->tm_hour = hw_alarm.u32Hour; + wkalarm->tm_min = hw_alarm.u32Minute; + wkalarm->tm_sec = hw_alarm.u32Second; + break; + + case RT_DEVICE_CTRL_RTC_SET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + hw_alarm.u32Hour = wkalarm->tm_hour; + hw_alarm.u32Minute = wkalarm->tm_min; + hw_alarm.u32Second = wkalarm->tm_sec; + + RTC_SetAlarmDateMask(1, 1, 1, 1, 1, 1); + RTC_SetAlarmDateAndTime(&hw_alarm); + break; + + default: + return -(RT_EINVAL); +#endif + } + + return RT_EOK; +} +/* rtc interrupt entry */ +void RTC_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (RTC_GET_TICK_INT_FLAG()) + { + RTC_CLEAR_TICK_INT_FLAG(); + } +#if defined(RT_USING_ALARM) + + if (RTC_GET_ALARM_INT_FLAG()) + { + RTC_CLEAR_ALARM_INT_FLAG(); + + /* Send an alarm event to notify rt-thread alarm service. */ + rt_alarm_update(&device_rtc, 0); + } +#endif + + rt_interrupt_leave(); +} +#endif //#if defined(BSP_USING_RTC) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c new file mode 100644 index 00000000000..aa248173f97 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c @@ -0,0 +1,762 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_SDH) + +#include "NuMicro.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.sdh" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#if defined(RT_USING_CACHE) +#define SDH_ALIGN_LEN 32 +#else +#define SDH_ALIGN_LEN 4 +#endif +#define SDH_BUFF_SIZE 512 +#define SDH_SetClock SDH_Set_clock +#define DEFINE_NU_SDH(_idx, _cachebuf) \ + { \ + .name = "sdh" #_idx, \ + .base = SDH##_idx, \ + .irqn = SDH##_idx##_IRQn, \ + .rstidx = SDH##_idx##_RST, \ + .modid = SDH##_idx##_MODULE, \ + .cachebuf = (uint8_t *)(_cachebuf), \ + } + +#define DEFINE_SDH_IRQ_HANDLER(_idx) \ +void SDH##_idx##_IRQHandler(void) \ +{ \ + rt_interrupt_enter(); \ + \ + nu_sdh_isr(&nu_sdh_arr[SDH##_idx##_IDX]); \ + \ + rt_interrupt_leave(); \ +} + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + SDH_START = -1, +#if defined(BSP_USING_SDH0) + SDH0_IDX, +#endif + SDH_CNT +}; + +struct nu_sdh +{ + struct rt_mmcsd_host *host; + char *name; + SDH_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint64_t modid; + + uint8_t *cachebuf; + uint32_t u32CmdResp0; + uint32_t u32CmdResp1; + uint32_t u32CurClk; + rt_tick_t LastNotice; +}; +typedef struct nu_sdh *nu_sdh_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static int SDH_SetBusWidth(SDH_T *sdh, uint32_t bw); +static int SDH_GetBusStatus(SDH_T *sdh, uint32_t mask); + +/* Static Variables ----------------------------------------------------------*/ +#if defined(BSP_USING_SDH0) +static uint32_t g_au32CacheBuf_SDH0[SDH_BUFF_SIZE / 4]; +#endif + +static struct nu_sdh nu_sdh_arr [] = +{ +#if defined(BSP_USING_SDH0) + DEFINE_NU_SDH(0, g_au32CacheBuf_SDH0), +#endif +}; /* struct nu_sdh nu_sdh_arr [] */ + +/* Functions Implementation --------------------------------------------------*/ +static int SDH_SetBusWidth(SDH_T *sdh, uint32_t bw) +{ + if (bw == 4) + { + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if (bw == 1) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + else + { + goto exit_SDH_SetBusWidth; + } + + return 0; + +exit_SDH_SetBusWidth: + + return -1; + +} + +static int SDH_GetBusStatus(SDH_T *sdh, uint32_t mask) +{ + int cnt = 0x100000; + while (cnt-- > 0) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while (sdh->CTL & SDH_CTL_CLK8OEN_Msk) +{ } + + if (SDH_GET_INT_FLAG(sdh, SDH_INTSTS_DAT0STS_Msk)) + break; + } + return (cnt == 0) ? -1 : 0 ; +} + +static int SDH_GetCD(SDH_T *sdh) +{ + int i32CD = 0; + if ((sdh->GCTL & SDH_GCTL_SDEN_Msk) == SDH_GCTL_SDEN_Msk) + { + if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + i32CD = (sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) ? 0 : 1; + } + else /* Card detect pin from DAT3 mode */ + { + __IO uint32_t i; + + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for (i = 0ul; i < 5000ul; i++) { } + + i32CD = ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) ? 1 : 0; + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + } + return i32CD; +} + +static void SDH_Enable(SDH_T *sdh) +{ + /* Reset sdh and its DMA engine at first. */ + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk | SDH_DMACTL_DMAEN_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) { } + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + sdh->DMAINTSTS = SDH_DMAINTSTS_ABORTIF_Msk | SDH_DMAINTSTS_WEOTIF_Msk; // clear all interrupt flag + + sdh->GCTL = SDH_GCTL_GCTLRST_Msk; + while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) { } + sdh->GINTSTS = SDH_GINTSTS_DTAIF_Msk; + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; + while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) { } + + sdh->INTSTS = 0xFFFFFFFF; // clear all interrupt flag + + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; +} + +/** + * @brief This function get command responding. + * @param sdh SDH instance + * @param cmd rt_mmcsd_cmd + * @retval none + */ +static void nu_sdh_sendcmd_done(SDH_T *sdh, struct rt_mmcsd_cmd *cmd) +{ + if (resp_type(cmd) == RESP_R2) + { + volatile uint8_t *c = (volatile uint8_t *)&sdh->FB[0]; + int i, j, tmp[5]; + + for (i = 0, j = 0; j < 5; i += 4, j++) + { + tmp[j] = (*(c + i) << 24) | (*(c + i + 1) << 16) | (*(c + i + 2) << 8) | (*(c + i + 3)); + } + for (i = 0; i < 4; i++) + { + cmd->resp[i] = ((tmp[i] & 0x00ffffff) << 8) | + ((tmp[i + 1] & 0xff000000) >> 24); + } + } + else + { + cmd->resp[0] = (sdh->RESP0 << 8) | (sdh->RESP1 & 0xff); + cmd->resp[1] = cmd->resp[2] = cmd->resp[3] = 0; + } +} + +/** + * @brief This function wait data-sending/receiving. + * @param sdh SDH instance + * @param data rt_mmcsd_data + * @retval error code + */ +static int nu_sdh_xfer_data(SDH_T *sdh, struct rt_mmcsd_data *data) +{ + while (!SDH_GET_INT_FLAG(sdh, SDH_INTSTS_BLKDIF_Msk)) { } + + SDH_CLR_INT_FLAG(sdh, SDH_INTSTS_BLKDIF_Msk); + + if (data->flags & DATA_DIR_WRITE) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + + while (!SDH_GET_INT_FLAG(sdh, SDH_INTSTS_DAT0STS_Msk)) { } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return 0; +} + +/** + * @brief This function send command and wait its response. + * @param host rt_mmcsd_host + * @param cmd rt_mmcsd_cmd + * @param data rt_mmcsd_data + * @retval error code + */ +static int nu_sdh_sendcmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, struct rt_mmcsd_data *data) +{ + int ret; + nu_sdh_t NuSdh = (nu_sdh_t)host->private_data; + SDH_T *sdh = NuSdh->base; + + volatile uint32_t ctl = 0, tout = 0; + + switch (host->io_cfg.bus_width) + { + case MMCSD_BUS_WIDTH_1: + ctl &= ~SDH_CTL_DBW_Msk; + break; + + case MMCSD_BUS_WIDTH_4: + ctl |= SDH_CTL_DBW_Msk; + break; + + case MMCSD_BUS_WIDTH_8: + default: + return -1; + } + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk | SDH_DMACTL_DMAEN_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) { } + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + sdh->DMAINTSTS = SDH_DMAINTSTS_ABORTIF_Msk | SDH_DMAINTSTS_WEOTIF_Msk; // clear all interrupt flag + + if (resp_type(cmd) != RESP_NONE) + { + if (resp_type(cmd) == RESP_R2) + { + ctl |= SDH_CTL_R2EN_Msk; + } + else + { + ctl |= SDH_CTL_RIEN_Msk; + } + tout = 0xFFFF; + } + ctl |= ((9 << SDH_CTL_SDNWR_Pos) | (1 << SDH_CTL_BLKCNT_Pos)); + ctl |= ((cmd->cmd_code << SDH_CTL_CMDCODE_Pos) | SDH_CTL_COEN_Msk); + + /* Set Transfer mode regarding to data flag */ + if (data != RT_NULL) + { + sdh->BLEN = data->blksize - 1; + + if (data->blksize <= 0x200) + { + if (data->blks < 256) + { + ctl = (ctl & ~SDH_CTL_BLKCNT_Msk) | (data->blks << SDH_CTL_BLKCNT_Pos); + } + else + { + LOG_E("SD Max block transfer is 255!!"); + } + } + + if (data->flags & DATA_DIR_READ) + { + tout = 0xFFFFFF; + ctl |= SDH_CTL_DIEN_Msk; // Data-in + sdh->DMASA = (uint32_t)data->buf; // Read from dest + } + else if (data->flags & DATA_DIR_WRITE) + { + ctl |= SDH_CTL_DOEN_Msk; // Data-out + sdh->DMASA = (uint32_t)data->buf; // Write to dest + } + } + else if (resp_type(cmd) == RESP_R1B) + { + } + SDH_CLR_INT_FLAG(sdh, SDH_INTSTS_RTOIF_Msk); + sdh->TOUT = tout; + + /* Set argument and start a transaction. */ + sdh->CMDARG = cmd->arg; + sdh->CTL = ctl; + + /* Wait a command done. */ + while ((sdh->CTL & (SDH_CTL_COEN_Msk)) == SDH_CTL_COEN_Msk) { } + + if (resp_type(cmd) != RESP_NONE) + { + if (resp_type(cmd) == RESP_R2) + { + /* Wait to receive a response R2 from SD card and store the response data into DMC's Flash buffer (exclude CRC7). */ + while (sdh->CTL & SDH_CTL_R2EN_Msk) + { + /* When get a Response timeout, break the polling. */ + if (SDH_GET_INT_FLAG(sdh, SDH_INTSTS_RTOIF_Msk)) + { + ret = __LINE__; + goto exit_nu_sdh_sendcmd; + } + } + } + else + { + /* Wait to receive a response from SD card. */ + while ((sdh->CTL & SDH_CTL_RIEN_Msk)) + { + /* When get a Response timeout, break the polling. */ + if (SDH_GET_INT_FLAG(sdh, SDH_INTSTS_RTOIF_Msk)) + { + ret = __LINE__; + goto exit_nu_sdh_sendcmd; + } + } + if (cmd->cmd_code == 5) + { + if ((NuSdh->u32CmdResp0 == sdh->RESP0) && (NuSdh->u32CmdResp1 == sdh->RESP1)) + { + LOG_E("False CMD5-RESP issue occured.\n"); + ret = __LINE__; + goto exit_nu_sdh_sendcmd; + } + } + NuSdh->u32CmdResp0 = sdh->RESP0; + NuSdh->u32CmdResp1 = sdh->RESP1; + } + nu_sdh_sendcmd_done(sdh, cmd); + } + + if (data != RT_NULL) + { + /* Wait data processing done */ + nu_sdh_xfer_data(sdh, data); + + ret = SDH_GetBusStatus(sdh, 0); + if (ret) + { + LOG_E("ERROR: Busy %d\n", ret); + ret = __LINE__; + goto exit_nu_sdh_sendcmd; + } + } + if (SDH_GET_INT_FLAG(sdh, SDH_INTSTS_CRCIF_Msk)) // Fault + { + uint32_t u32INTSTS = sdh->INTSTS; + SDH_CLR_INT_FLAG(sdh, SDH_INTSTS_CRCIF_Msk); + ret = __LINE__; + + if ((resp_type(cmd) != RESP_R3) && (u32INTSTS & SDH_INTSTS_CRC7_Msk) == 0) //CRC7, Ignore R3 + { + LOG_E("CRC7 error! (resp_type=%d)", resp_type(cmd)); + goto exit_nu_sdh_sendcmd; + } + + if ((u32INTSTS & SDH_INTSTS_CRC16_Msk) == 0) //CRC16 + { + LOG_E("CRC16 error! (resp_type=%d)", resp_type(cmd)); + goto exit_nu_sdh_sendcmd; + } + } + + return 0; + +exit_nu_sdh_sendcmd: + + LOG_D("[%s %d] cmdid=%d error line=%d", __func__, __LINE__, cmd->cmd_code, ret); + + cmd->resp[0] = cmd->resp[1] = cmd->resp[2] = cmd->resp[3] = 0; + sdh->TOUT = 0; + SDH_Enable(sdh); + + return -ret; +} + +/** + * @brief This function send request. + * @param host rt_mmcsd_host + * @param req request + * @retval None + */ +static void nu_sdh_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + nu_sdh_t NuSdh; + SDH_T *sdh; + + RT_ASSERT(host); + RT_ASSERT(req); + + NuSdh = (nu_sdh_t)host->private_data; + sdh = NuSdh->base; + + if (!SDH_GetCD(sdh)) // card is not present + { + LOG_E("Card is not present"); + req->cmd->err = -RT_EIO; + goto exit_nu_sdh_request; + } + + if (req->cmd != RT_NULL) + { + struct rt_mmcsd_cmd *cmd = req->cmd; + struct rt_mmcsd_data *data = req->data; + + LOG_D("[%s%s%s%s%s]REQ: CMD:%d ARG:0x%08x RESP_TYPE:%d rw:%c addr:%08x, blks:%d, blksize:%d datalen:%d", + (host->card == RT_NULL) ? "Unknown" : "", + (host->card) && (host->card->card_type == CARD_TYPE_MMC) ? "MMC" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SD) ? "SD" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SDIO) ? "SDIO" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SDIO_COMBO) ? "SDIO_COMBO" : "", + cmd->cmd_code, + cmd->arg, + resp_type(cmd), + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->buf : 0, + data ? data->blks : 0, + data ? data->blksize : 0, + data ? data->blks * data->blksize : 0); + + if (data != RT_NULL) + { + rt_uint32_t size; + rt_int32_t IsNonaligned = 0; + rt_uint32_t *org_data_buf = data->buf; + + size = data->blksize * data->blks; + + RT_ASSERT(org_data_buf); + + IsNonaligned = (((rt_uint32_t)data->buf & (SDH_ALIGN_LEN - 1)) > 0) ? 1 : 0; + if (IsNonaligned) + { + data->buf = (rt_uint32_t *)NuSdh->cachebuf; + if (data->flags & DATA_DIR_WRITE) + { + LOG_D("Un-aligned, prepare into cache buf(%d)", size); + rt_memcpy(data->buf, org_data_buf, size); + } + } +#if defined(RT_USING_CACHE) + if (!IsNonaligned) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH_INVALIDATE, (void *)data->buf, size); + + cmd->err = nu_sdh_sendcmd(host, cmd, data); + + if (!IsNonaligned) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)data->buf, size); +#else + cmd->err = nu_sdh_sendcmd(host, cmd, data); +#endif + + if (!cmd->err && IsNonaligned) + { + if (data->flags & DATA_DIR_READ) + { + LOG_D("Un-aligned, restore from cache buf(%d)", size); + rt_memcpy(org_data_buf, data->buf, size); + } + } + data->buf = org_data_buf; + + LOG_HEX("data.dest", 16, (void *)data->buf, size); + } + else + { + cmd->err = nu_sdh_sendcmd(host, cmd, NULL); + } + + if (resp_type(cmd) != RESP_NONE) + LOG_HEX("cmd->resp", 16, (void *)&cmd->resp[0], 16); + } + + if (req->stop != RT_NULL) + { + struct rt_mmcsd_cmd *stop = req->stop; + + stop->err = nu_sdh_sendcmd(host, stop, NULL); + + if (resp_type(stop) != RESP_NONE) + LOG_HEX("stop->resp", 16, (void *)&stop->resp[0], 16); + + } + +exit_nu_sdh_request: + + mmcsd_req_complete(host); +} + +/** + * @brief This function config. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void nu_sdh_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + nu_sdh_t NuSdh; + rt_uint32_t clk; + SDH_T *sdh; + + RT_ASSERT(host); + RT_ASSERT(io_cfg); + + NuSdh = (nu_sdh_t)host->private_data; + sdh = NuSdh->base; + clk = io_cfg->clock; + + LOG_D("[%s]clk:%d width(%d):%s%s%s power:%s%s%s", + NuSdh->name, + clk, + io_cfg->bus_width, + (io_cfg->bus_width) == MMCSD_BUS_WIDTH_8 ? "8" : "", + (io_cfg->bus_width) == MMCSD_BUS_WIDTH_4 ? "4" : "", + (io_cfg->bus_width) == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""); + + /* Clock */ + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk < host->freq_min) + clk = host->freq_min; + + LOG_D("[%s] ExceptedFreq: %d kHz", NuSdh->name, clk / 1000); + if (NuSdh->u32CurClk != (clk / 1000)) + { + SDH_SetClock(sdh, clk / 1000); + NuSdh->u32CurClk = (clk / 1000); + } + + switch (io_cfg->power_mode) + { + case MMCSD_POWER_UP: + if (clk <= 400000) + { + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) + { + } + } + break; + + case MMCSD_POWER_ON: + break; + + case MMCSD_POWER_OFF: + break; + + default: + break; + } + switch ((io_cfg->bus_width)) + { + case MMCSD_BUS_WIDTH_1: + SDH_SetBusWidth(sdh, 1); + break; + + case MMCSD_BUS_WIDTH_4: + SDH_SetBusWidth(sdh, 4); + break; + + case MMCSD_BUS_WIDTH_8: + default: + break; + } + +} + +/** + * @brief This function detect sdcard. + * @param host rt_mmcsd_host + * @retval card detection status + */ +static rt_int32_t nu_sdh_card_detect(struct rt_mmcsd_host *host) +{ + nu_sdh_t NuSdh; + RT_ASSERT(host); + + NuSdh = (nu_sdh_t)host->private_data; + SDH_T *sdh = NuSdh->base; + + LOG_D("try to detect device"); + return SDH_GetCD(sdh); +} + +static void nu_sdh_isr(nu_sdh_t NuSdh) +{ + SDH_T *sdh = NuSdh->base; + uint32_t isr = sdh->INTSTS; + + /* card detected */ + if (isr & SDH_INTSTS_CDIF_Msk) + { + rt_tick_t cur_tick = rt_tick_get(); + rt_tick_t diff_tick; + + /* ready to change */ + if (cur_tick >= NuSdh->LastNotice) + diff_tick = (cur_tick - NuSdh->LastNotice); + else + diff_tick = ((rt_tick_t) -1) - NuSdh->LastNotice + cur_tick; + + if (!NuSdh->LastNotice || (diff_tick > (RT_TICK_PER_SECOND / 5))) // Debounce 200ms + { + NuSdh->LastNotice = cur_tick; + mmcsd_change(NuSdh->host); + } + SDH_CLR_INT_FLAG(sdh, SDH_INTSTS_CDIF_Msk); + } +} + +#if defined(BSP_USING_SDH0) +DEFINE_SDH_IRQ_HANDLER(0) +#endif + +#if defined(BSP_USING_SDH1) +DEFINE_SDH_IRQ_HANDLER(1) +#endif + +/** + * @brief This function update sdh interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void nu_sdh_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + nu_sdh_t NuSdh = (nu_sdh_t)host->private_data; + SDH_T *sdh = NuSdh->base; + + if (enable) + { + LOG_D("Enable %s irq", NuSdh->name); + SDH_ENABLE_INT(sdh, SDH_INTSTS_CDIF_Msk); + } + else + { + LOG_D("Disable %s irq", NuSdh->name); + SDH_DISABLE_INT(sdh, SDH_INTSTS_CDIF_Msk); + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + nu_sdh_request, + nu_sdh_iocfg, + nu_sdh_card_detect, + nu_sdh_irq_update, +}; + +/** + * @brief This function create mmcsd host. + * @param sdh nu_sdh_t + * @retval nuvton + */ +void nu_sdh_host_init(nu_sdh_t sdh) +{ + struct rt_mmcsd_host *host = mmcsd_alloc_host(); + RT_ASSERT(host); + + /* set host default attributes */ + host->ops = &ops; + host->freq_min = 300 * 1000; + host->freq_max = 48 * 1000 * 1000; + host->valid_ocr = VDD_26_27 | VDD_27_28 | VDD_28_29 | VDD_29_30 | VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34; + + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; + + host->max_seg_size = SDH_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = SDH_BLOCK_SIZE; + host->max_blk_count = (SDH_BUFF_SIZE / SDH_BLOCK_SIZE); + + /* link up host and sdio */ + host->private_data = sdh; + sdh->host = host; + + /* Enable DMA engine at first. */ + SDH_Enable(sdh->base); + + /* Install ISR. */ + NVIC_EnableIRQ(sdh->irqn); + + /* ready to change */ + //mmcsd_change(host); +} + +static int rt_hw_sdh_init(void) +{ + int i; + + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + CLK_EnableModuleClock(nu_sdh_arr[i].modid); + SYS_ResetModule(nu_sdh_arr[i].rstidx); + + nu_sdh_host_init(&nu_sdh_arr[i]); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdh_init); + +void nu_sd_attach(void) +{ + int i; + /* ready to change */ + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + if (nu_sdh_arr[i].host) + mmcsd_change(nu_sdh_arr[i].host); + } +} +MSH_CMD_EXPORT(nu_sd_attach, attach card); + +void nu_sd_regdump(void) +{ + int i; + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + if (nu_sdh_arr[i].host) + LOG_HEX("sdh_reg", 16, (void *)nu_sdh_arr[i].base, sizeof(SDH_T)); + } +} +MSH_CMD_EXPORT(nu_sd_regdump, dump sdh registers); +#endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_softi2c.c new file mode 100644 index 00000000000..6e44986b541 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_softi2c.c @@ -0,0 +1,219 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if (defined(BSP_USING_SOFT_I2C) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) + +#include "NuMicro.h" +#include "rtdevice.h" +#include "rthw.h" +#include "rtthread.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.softi2c" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DEFINE_NU_SOFT_I2C_BUS_CONFIG(_idx, _scl, _sda) \ + { \ + .scl = _scl, \ + .sda = _sda, \ + .bus_name = "softi2c" #_idx, \ + } + +#if defined(BSP_USING_SOFT_I2C0) +#define NU_SOFT_I2C0_BUS_CONFIG \ + DEFINE_NU_SOFT_I2C_BUS_CONFIG(0, BSP_SOFT_I2C0_SCL_PIN, BSP_SOFT_I2C0_SDA_PIN) +#endif + +#if defined(BSP_USING_SOFT_I2C1) +#define NU_SOFT_I2C1_BUS_CONFIG \ + DEFINE_NU_SOFT_I2C_BUS_CONFIG(1, BSP_SOFT_I2C1_SCL_PIN, BSP_SOFT_I2C1_SDA_PIN) +#endif + +#if (!defined(BSP_USING_SOFT_I2C0) && !defined(BSP_USING_SOFT_I2C1)) + #error "Please define at least one BSP_USING_SOFT_I2Cx" +#endif + + +/* Types / Structures ---------------------------------------------------------*/ +struct nu_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; + +struct nu_soft_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device soft_i2c_bus; +}; + +/* Static Function Prototypes ------------------------------------------------*/ +static void nu_soft_i2c_udelay(rt_uint32_t us); +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state); +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state); +static rt_int32_t nu_soft_i2c_get_sda(void *data); +static rt_int32_t nu_soft_i2c_get_scl(void *data); + +/* Static Variables ----------------------------------------------------------*/ +static const struct nu_soft_i2c_config nu_soft_i2c_cfg[] = +{ +#if defined(BSP_USING_SOFT_I2C0) + NU_SOFT_I2C0_BUS_CONFIG, +#endif +#if defined(BSP_USING_SOFT_I2C1) + NU_SOFT_I2C1_BUS_CONFIG, +#endif +}; + +static struct nu_soft_i2c nu_soft_i2c_obj[sizeof(nu_soft_i2c_cfg) / sizeof(nu_soft_i2c_cfg[0])]; + +static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops = +{ + .data = RT_NULL, + .set_sda = nu_soft_i2c_set_sda, + .set_scl = nu_soft_i2c_set_scl, + .get_sda = nu_soft_i2c_get_sda, + .get_scl = nu_soft_i2c_get_scl, + .udelay = nu_soft_i2c_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/* Functions Implementation --------------------------------------------------*/ +/** + * The time delay function. + * + * @param microseconds. + */ +static void nu_soft_i2c_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +/** + * This function initializes the soft i2c pin. + * + * @param soft i2c config class. + */ +static void nu_soft_i2c_gpio_init(const struct nu_soft_i2c_config *cfg) +{ + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * if i2c is locked, this function will unlock it + * + * @param soft i2c config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + nu_soft_i2c_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + nu_soft_i2c_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * This function sets the sda pin. + * + * @param soft i2c config class. + * @param The sda pin state. + */ +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->sda, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function sets the scl pin. + * + * @param soft i2c config class. + * @param The scl pin state. + */ +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->scl, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t nu_soft_i2c_get_sda(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t nu_soft_i2c_get_scl(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + return rt_pin_read(cfg->scl); +} +int rt_soft_i2c_init(void) +{ + rt_size_t obj_num = sizeof(nu_soft_i2c_obj) / sizeof(struct nu_soft_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + nu_soft_i2c_obj[i].ops = nu_soft_i2c_bit_ops; + nu_soft_i2c_obj[i].ops.data = (void *)&nu_soft_i2c_cfg[i]; + nu_soft_i2c_obj[i].soft_i2c_bus.priv = &nu_soft_i2c_obj[i].ops; + nu_soft_i2c_gpio_init(&nu_soft_i2c_cfg[i]); + + result = rt_i2c_bit_add_bus(&nu_soft_i2c_obj[i].soft_i2c_bus, nu_soft_i2c_cfg[i].bus_name); + RT_ASSERT(result == RT_EOK); + + nu_soft_i2c_bus_unlock(&nu_soft_i2c_cfg[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + nu_soft_i2c_cfg[i].bus_name, + nu_soft_i2c_cfg[i].scl, + nu_soft_i2c_cfg[i].sda); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_soft_i2c_init); +#endif //#if (defined(BSP_USING_SOFT_I2C) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c new file mode 100644 index 00000000000..60648cd4b60 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c @@ -0,0 +1,705 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_SPI) + +#include "drv_spi.h" +#include "rtdef.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.spi" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI0_PDMA) +#define SPI0_PDMA_INIT \ + .pdma_perp_tx = PDMA_SPI0_TX, \ + .pdma_perp_rx = PDMA_SPI0_RX, +#else +#define SPI0_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif + +#if defined(BSP_USING_SPI1_PDMA) +#define SPI1_PDMA_INIT \ + .pdma_perp_tx = PDMA_SPI1_TX, \ + .pdma_perp_rx = PDMA_SPI1_RX, +#else +#define SPI1_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif + +#if defined(BSP_USING_SPI2_PDMA) +#define SPI2_PDMA_INIT \ + .pdma_perp_tx = PDMA_SPI2_TX, \ + .pdma_perp_rx = PDMA_SPI2_RX, +#else +#define SPI2_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#else +#define SPI0_PDMA_INIT +#define SPI1_PDMA_INIT +#define SPI2_PDMA_INIT +#endif + +#define DEFINE_NU_SPI(_idx, _pdma_init) \ + { \ + .name = "spi" #_idx, \ + .spi_base = SPI##_idx, \ + .rstidx = SPI##_idx##_RST, \ + _pdma_init \ + } + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + SPI_START = -1, +#if defined(BSP_USING_SPI0) + SPI0_IDX, +#endif +#if defined(BSP_USING_SPI1) + SPI1_IDX, +#endif +#if defined(BSP_USING_SPI2) + SPI2_IDX, +#endif + SPI_CNT +}; +/* Static Function Prototypes ------------------------------------------------*/ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name); +static rt_ssize_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +#if defined(BSP_USING_SPI_PDMA) + static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter); + static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); + static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); + static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +#endif +/* Static Variables ----------------------------------------------------------*/ +static struct rt_spi_ops nu_spi_poll_ops = +{ + .configure = nu_spi_bus_configure, + .xfer = nu_spi_bus_xfer, +}; + +static struct nu_spi nu_spi_arr [] = +{ +#if defined(BSP_USING_SPI0) + DEFINE_NU_SPI(0, SPI0_PDMA_INIT), +#endif +#if defined(BSP_USING_SPI1) + DEFINE_NU_SPI(1, SPI1_PDMA_INIT), +#endif +#if defined(BSP_USING_SPI2) + DEFINE_NU_SPI(2, SPI2_PDMA_INIT), +#endif +}; /* spi nu_spi */ + +/* Functions Implementation --------------------------------------------------*/ +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); +void nu_spi_drain_rxfifo(SPI_T *spi_base); +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) + { + struct nu_spi *spi_bus; + uint32_t u32SPIMode; + uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + void *pvUserData; + + RT_ASSERT(device); + RT_ASSERT(configuration); + + spi_bus = (struct nu_spi *) device->bus; + pvUserData = device->parent.user_data; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_spi_bus_configure; + } + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_spi_bus_configure; + } + u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + LOG_I("%s clock max frequency is %dHz ( != %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(*configuration)) != 0) + { + rt_memcpy(&spi_bus->configuration, configuration, sizeof(*configuration)); + + SPI_Open(spi_bus->spi_base, + (configuration->mode & RT_SPI_SLAVE) ? SPI_SLAVE : SPI_MASTER, + u32SPIMode, + configuration->data_width, + configuration->max_hz); + + /* Disable Auto-selection function. */ + SPI_DisableAutoSS(spi_bus->spi_base); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + if (pvUserData != RT_NULL) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + } + else + { + /* Set CS pin to HIGH */ + if (pvUserData != RT_NULL) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_spi_bus_configure: + + return -(ret); +} +#if defined(BSP_USING_SPI_PDMA) +static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter) +{ + rt_err_t result; + struct nu_spi *spi_bus = (struct nu_spi *)pvUserData; + + RT_ASSERT(spi_bus); + + result = rt_sem_release(spi_bus->m_psSemBus); + RT_ASSERT(result == RT_EOK); +} + +static void nu_pdma_spi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + SPI_T *spi_base = (SPI_T *)pvUserData; + + /* Trigger TX/RX PDMA transfer. */ + SPI_TRIGGER_TX_RX_PDMA(spi_base); +} + +static void nu_pdma_spi_rx_cb_disable(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + SPI_T *spi_base = (SPI_T *)pvUserData; + + /* Stop TX/RX DMA transfer. */ + SPI_DISABLE_TX_RX_PDMA(spi_base); +} + +static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result; + rt_uint8_t *dst_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_rx_chid = spi_bus->pdma_chanid_rx; + + nu_pdma_filtering_set(spi_pdma_rx_chid, NU_PDMA_EVENT_TRANSFER_DONE); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_event; + sChnCB.m_pvUserData = (void *)spi_bus; + + result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + sChnCB.m_eCBType = eCBType_Disable; + sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_disable; + sChnCB.m_pvUserData = (void *)spi_base; + result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + if (pu8Buf == RT_NULL) + { + memctrl = eMemCtl_SrcFix_DstFix; + dst_addr = (rt_uint8_t *) &spi_bus->dummy[0]; + } + else + { + memctrl = eMemCtl_SrcFix_DstInc; + dst_addr = pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_rx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + result = nu_pdma_transfer(spi_pdma_rx_chid, + bytes_per_word * 8, + (uint32_t)&spi_base->RX, + (uint32_t)dst_addr, + i32RcvLen / bytes_per_word, + 0); + +exit_nu_pdma_spi_rx_config: + + return result; +} + +static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result; + rt_uint8_t *src_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx; + + if (pu8Buf == RT_NULL) + { + spi_bus->dummy[0] = 0; + memctrl = eMemCtl_SrcFix_DstFix; + src_addr = (rt_uint8_t *)&spi_bus->dummy[0]; + } + else + { + memctrl = eMemCtl_SrcInc_DstFix; + src_addr = (rt_uint8_t *)pu8Buf; + } + sChnCB.m_eCBType = eCBType_Trigger; + sChnCB.m_pfnCBHandler = nu_pdma_spi_tx_cb_trigger; + sChnCB.m_pvUserData = (void *)spi_base; + result = nu_pdma_callback_register(spi_pdma_tx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_tx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + result = nu_pdma_transfer(spi_pdma_tx_chid, + bytes_per_word * 8, + (uint32_t)src_addr, + (uint32_t)&spi_base->TX, + i32SndLen / bytes_per_word, + 0); +exit_nu_pdma_spi_tx_config: + + return result; +} + +/** + * SPI PDMA transfer + */ +static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + + result = nu_pdma_spi_rx_config(spi_bus, recv_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + /* Wait RX-PDMA transfer done */ + result = rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + return length; +} + +rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus) +{ + /* Allocate SPI_TX nu_dma channel */ + if ((spi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(spi_bus->pdma_perp_tx)) < 0) + { + goto exit_nu_hw_spi_pdma_allocate; + } + else if ((spi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(spi_bus->pdma_perp_rx)) < 0) + { + nu_pdma_channel_free(spi_bus->pdma_chanid_tx); + goto exit_nu_hw_spi_pdma_allocate; + } + + spi_bus->m_psSemBus = rt_sem_create("spibus_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(spi_bus->m_psSemBus != RT_NULL); + + return RT_EOK; + +exit_nu_hw_spi_pdma_allocate: + + return -(RT_ERROR); +} +#endif /* +#if defined(BSP_USING_SPI_PDMA) */ + +void nu_spi_drain_rxfifo(SPI_T *spi_base) +{ + while (SPI_IS_BUSY(spi_base)); + + // Drain SPI RX FIFO, make sure RX FIFO is empty + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + SPI_ClearRxFIFO(spi_base); + } +} + +static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word) +{ + int size = 0; + + // Read RX data + if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + uint32_t val; + // Read data from SPI RX FIFO + switch (bytes_per_word) + { + case 4: + val = SPI_READ_RX(spi_base); + nu_set32_le(recv_addr, val); + break; + case 3: + val = SPI_READ_RX(spi_base); + nu_set24_le(recv_addr, val); + break; + case 2: + val = SPI_READ_RX(spi_base); + nu_set16_le(recv_addr, val); + break; + case 1: + *recv_addr = SPI_READ_RX(spi_base); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + size = bytes_per_word; + } + return size; +} + +static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes_per_word) +{ + // Wait SPI TX send data + while (SPI_GET_TX_FIFO_FULL_FLAG(spi_base)); + + // Input data to SPI TX + switch (bytes_per_word) + { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(send_addr)); + break; + case 3: + SPI_WRITE_TX(spi_base, nu_get24_le(send_addr)); + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(send_addr)); + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr)); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + + return bytes_per_word; +} + +/** + * @brief SPI bus polling + * @param dev : The pointer of the specified SPI module. + * @param send_addr : Source address + * @param recv_addr : Destination address + * @param length : Data length + */ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) + { + SPI_T *spi_base = spi_bus->spi_base; + + // Write-only + if ((send_addr != RT_NULL) && (recv_addr == RT_NULL)) + { + while (length > 0) + { + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + } + } + else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL)) + { + spi_bus->dummy[0] = 0; + while (length > 0) + { + /* Input data to SPI TX FIFO */ + length -= nu_spi_write(spi_base, (const uint8_t *)&spi_bus->dummy[0], bytes_per_word); + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + else + { + while (length > 0) + { + /* Input data to SPI TX FIFO */ + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + if (recv_addr) + { + // Wait SPI transmission done + while (SPI_IS_BUSY(spi_base)) + { + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + else + { + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_base); + } +} + +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word) +{ + RT_ASSERT(spi_bus != RT_NULL); +#if defined(BSP_USING_SPI_PDMA) + /* Slave role, always use PDMA to get higher performance. */ + if ((spi_bus->pdma_chanid_rx >= 0) && + !((uint32_t)tx % bytes_per_word) && + !((uint32_t)rx % bytes_per_word) && + (bytes_per_word != 3) && + ((spi_bus->spi_base->CTL & SPI_CTL_SLAVE_Msk) || (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD))) + /* DMA transfer constrains */ + nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word); + else +#endif + { + if (spi_bus->spi_base->CTL & SPI_CTL_SLAVE_Msk) + { + /* Slave role */ + /* please use PDMA to get higher performance. */ + RT_ASSERT(0); + } + + nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word); + } +} + +static rt_ssize_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *spi_bus; + struct rt_spi_configuration *configuration; + uint8_t bytes_per_word; + void *pvUserData; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + configuration = (struct rt_spi_configuration *)&spi_bus->configuration; + bytes_per_word = configuration->data_width / 8; + pvUserData = device->parent.user_data; + + if ((message->length % bytes_per_word) != 0) + { + /* Say bye. */ + LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word); + return 0; + } + + if (message->length > 0) + { + if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS)) + { + + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + else + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + } + } + + nu_spi_transfer(spi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word); + + if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS)) + { + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + } + } + + } + + return message->length; +} + +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name) +{ + return rt_spi_bus_register(&spi_bus->dev, name, &nu_spi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_spi_init(void) +{ + int i; + + for (i = (SPI_START + 1); i < SPI_CNT; i++) + { + SYS_ResetModule(nu_spi_arr[i].rstidx); +#if defined(BSP_USING_SPI_PDMA) + nu_spi_arr[i].pdma_chanid_tx = -1; + nu_spi_arr[i].pdma_chanid_rx = -1; + + if ((nu_spi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_spi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK) + { + LOG_I("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name); + } + } + + nu_spi_arr[i].dummy = rt_malloc_align(RT_ALIGN_SIZE, RT_ALIGN_SIZE); + RT_ASSERT(nu_spi_arr[i].dummy); +#endif + nu_spi_register_bus(&nu_spi_arr[i], nu_spi_arr[i].name); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_spi_init); +#endif //#if defined(BSP_USING_SPI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h new file mode 100644 index 00000000000..615f74f7e06 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h @@ -0,0 +1,48 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ +#include "rtconfig.h" + +#include "rtdevice.h" +#include "NuMicro.h" +#include "nu_bitutil.h" +#if defined(BSP_USING_SPI_PDMA) + +#include "drv_pdma.h" +#endif +#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD + +#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) +#endif + +struct nu_spi +{ + struct rt_spi_bus dev; + char *name; + SPI_T *spi_base; + uint32_t rstidx; + uint32_t* dummy; +#if defined(BSP_USING_SPI_PDMA) + int32_t pdma_perp_tx; + int32_t pdma_chanid_tx; + int32_t pdma_perp_rx; + int32_t pdma_chanid_rx; + rt_sem_t m_psSemBus; +#endif + struct rt_qspi_configuration configuration; +}; + +typedef struct nu_spi *nu_spi_t; + +void nu_spi_drain_rxfifo(SPI_T *spi_base); +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); +#if defined(BSP_USING_SPI_PDMA) + rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); +#endif + +#endif /* __DRV_SPI_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spii2s.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spii2s.c new file mode 100644 index 00000000000..e03239cd248 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spii2s.c @@ -0,0 +1,609 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_SPII2S) + +#include "drv_i2s.h" +#include "drv_pdma.h" +#include "rtdbg.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.spii2s" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "spii2s" +#define DBG_COLOR + +#define DEFINE_NU_SPII2S(_idx) \ + { \ + .name = "spii2s" #_idx, \ + .i2s_base = (void *)SPI##_idx, \ + .i2s_rst = SPI##_idx##_RST, \ + .i2s_dais = { \ + [NU_I2S_DAI_PLAYBACK] = { \ + .pdma_perp = PDMA_SPI##_idx##_TX, \ + }, \ + [NU_I2S_DAI_CAPTURE] = { \ + .pdma_perp = PDMA_SPI##_idx##_RX, \ + } \ + } \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + SPII2S_START = -1, +#if defined(BSP_USING_SPII2S0) + SPII2S0_IDX, +#endif +#if defined(BSP_USING_SPII2S1) + SPII2S1_IDX, +#endif +#if defined(BSP_USING_SPII2S2) + SPII2S2_IDX, +#endif +#if defined(BSP_USING_SPII2S3) + SPII2S3_IDX, +#endif + SPII2S_CNT +}; +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio); +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream); +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); +static int rt_hw_spii2s_init(void); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_i2s g_nu_spii2s_arr [] = +{ +#if defined(BSP_USING_SPII2S0) + DEFINE_NU_SPII2S(0), +#endif +#if defined(BSP_USING_SPII2S1) + DEFINE_NU_SPII2S(1), +#endif +#if defined(BSP_USING_SPII2S2) + DEFINE_NU_SPII2S(2), +#endif +}; + +/* Functions Implementation --------------------------------------------------*/ +static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + // Report a buffer ready. + rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ; + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuSPII2s->audio); + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + SPI_T *spii2s_base; + nu_i2s_dai_t psNuSPII2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + struct nu_pdma_chn_cb sChnCB; + + RT_ASSERT(psNuSPII2s != RT_NULL); + + /* Get base address of spii2s register */ + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_spii2s_tx_cb; + u32Src = (uint32_t)&psNuSPII2sDai->fifo[0]; + u32Dst = (uint32_t)&spii2s_base->TX; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_spii2s_rx_cb; + u32Src = (uint32_t)&spii2s_base->RX; + u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = pfm_pdma_cb; + sChnCB.m_pvUserData = (void *)psNuSPII2s; + + nu_pdma_filtering_set(psNuSPII2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE); + result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid, &sChnCB); + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid, // Channel ID + psNuSPII2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor + 0); // Interrupt assert when every SG-table done. + RT_ASSERT(result == RT_EOK); + } + result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + /* case 24: PDMA constrain */ + case 32: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_spii2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps; + SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuSPII2s->AcodecOps; + + /* Open SPII2S */ + if (nu_spii2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + SPII2S_Open(spii2s_base, + (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos), + (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO, + SPII2S_FORMAT_I2S); + LOG_I("Open SPII2S."); + + /* Set MCLK and enable MCLK */ + /* The target MCLK is related to audio codec setting. */ + SPII2S_EnableMCLK(spii2s_base, 12000000); + + /* Set un-mute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_spii2s_dai_setup: + + return result; +} + +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_acodec_ops_t pNuACodecOps; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } + + } + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuSPII2s->config.channels; + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuSPII2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } + break; + + default: + result = -RT_ERROR; + break; + + } + + return result; +} + +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_acodec_ops_t pNuACodecOps; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control) + psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuSPII2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } + + if (bNeedReset) + { + return nu_spii2s_start(audio, stream); + } + } + break; + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(audio != RT_NULL); + + /* Reset this module */ + SYS_ResetModule(psNuSPII2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + SPI_T *spii2s_base; + + RT_ASSERT(audio != RT_NULL); + + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + /* Restart all: SPII2S and codec. */ + nu_spii2s_stop(audio, stream); + if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + SPII2S_ENABLE_TXDMA(spii2s_base); + + /* Enable I2S Tx function */ + SPII2S_ENABLE_TX(spii2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + SPII2S_ENABLE_RXDMA(spii2s_base); + + /* Enable I2S Rx function */ + SPII2S_ENABLE_RX(spii2s_base); + + LOG_I("Start record."); + } + break; + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_i2s_dai_t psNuSPII2sDai = RT_NULL; + SPI_T *spii2s_base; + + RT_ASSERT(audio != RT_NULL); + + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + SPII2S_DISABLE_TXDMA(spii2s_base); + SPII2S_DISABLE_TX(spii2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + SPII2S_DISABLE_RXDMA(spii2s_base); + SPII2S_DISABLE_RX(spii2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid); + + /* Close SPII2S */ + if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk))) + { + SPII2S_DisableMCLK(spii2s_base); + SPII2S_Close(spii2s_base); + LOG_I("Close SPII2S."); + } + rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ; + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + return; +} + +static struct rt_audio_ops nu_spii2s_audio_ops = +{ + .getcaps = nu_spii2s_getcaps, + .configure = nu_spii2s_configure, + + .init = nu_spii2s_init, + .start = nu_spii2s_start, + .stop = nu_spii2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_spii2s_buffer_info +}; + +static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0) + { + goto nu_hw_spii2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_spii2s_pdma_allocate: + + return -(RT_ERROR); +} + +static int rt_hw_spii2s_init(void) +{ + int j = 0; + nu_i2s_dai_t psNuSPII2sDai; + + for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++) + { + int i = 0; + SYS_ResetModule(g_nu_spii2s_arr[i].i2s_rst); + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i]; + psNuSPII2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL); + + psNuSPII2sDai->pdma_chanid = -1; + psNuSPII2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK); + RT_ASSERT(nu_pdma_sgtbls_allocate(psNuSPII2sDai->pdma_chanid, &psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + g_nu_spii2s_arr[j].audio.ops = &nu_spii2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]); + } + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_spii2s_init); + +#endif //#if defined(BSP_USING_SPII2S) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_sys.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sys.h new file mode 100644 index 00000000000..3fbfc67eb50 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sys.h @@ -0,0 +1,20 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SYS_H__ +#define __DRV_SYS_H__ +#include "rtthread.h" +#include "NuMicro.h" + +struct nu_module +{ + char *name; + void *m_pvBase; + uint32_t u32RstId; + IRQn_Type eIRQn; +} ; +typedef struct nu_module *nu_module_t; +#endif /* __DRV_SYS_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c new file mode 100644 index 00000000000..a0ebc34dcb2 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c @@ -0,0 +1,283 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) + +#include "NuMicro.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.timer" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define NU_TIMER_DEVICE(timer) (nu_timer_t)(timer) +#define DEFINE_NU_TIMER(_idx) \ + { \ + .name = "timer" #_idx, \ + .base = TIMER##_idx, \ + .irqn = TMR##_idx##_IRQn, \ + .rstidx = TMR##_idx##_RST, \ + .modid = TMR##_idx##_MODULE \ + } +#define DEFINE_TIMER_IRQ_HANDLER(_idx) \ +void TMR##_idx##_IRQHandler(void) \ +{ \ + rt_interrupt_enter(); \ + \ + nu_timer_isr((void *)&nu_timer_arr[TIMER##_idx##_IDX]); \ + \ + rt_interrupt_leave(); \ +} + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + TIMER_START = -1, +#if defined(BSP_USING_TIMER0) + TIMER0_IDX, +#endif +#if defined(BSP_USING_TIMER1) + TIMER1_IDX, +#endif +#if defined(BSP_USING_TIMER2) + TIMER2_IDX, +#endif +#if defined(BSP_USING_TIMER3) + TIMER3_IDX, +#endif + TIMER_CNT +}; + +struct nu_timer +{ + rt_hwtimer_t parent; + char *name; + TIMER_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint64_t modid; +}; +typedef struct nu_timer *nu_timer_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); +static void nu_timer_stop(rt_hwtimer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_timer nu_timer_arr [] = +{ +#if defined(BSP_USING_TIMER0) + DEFINE_NU_TIMER(0), +#endif +#if defined(BSP_USING_TIMER1) + DEFINE_NU_TIMER(1), +#endif +#if defined(BSP_USING_TIMER2) + DEFINE_NU_TIMER(2), +#endif +#if defined(BSP_USING_TIMER3) + DEFINE_NU_TIMER(3), +#endif +}; + +static struct rt_hwtimer_info nu_timer_info = +{ + 12000000, + 46875, + 0xFFFFFF, + HWTIMER_CNTMODE_UP, +}; + +static struct rt_hwtimer_ops nu_timer_ops = +{ + nu_timer_init, + nu_timer_start, + nu_timer_stop, + nu_timer_count_get, + nu_timer_control +}; + +/* Functions Implementation --------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + if (1 == state) + { + uint32_t timer_clk; + struct rt_hwtimer_info *info = &nu_timer_info; + + timer_clk = TIMER_GetModuleClock(psNuTmr->base); + info->maxfreq = timer_clk; + info->minfreq = timer_clk / 256; + TIMER_Open(psNuTmr->base, TIMER_ONESHOT_MODE, 1); + TIMER_EnableInt(psNuTmr->base); + NVIC_EnableIRQ(psNuTmr->irqn); + } + else + { + NVIC_DisableIRQ(psNuTmr->irqn); + TIMER_DisableInt(psNuTmr->base); + TIMER_Close(psNuTmr->base); + } +} + +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +{ + rt_err_t ret = RT_EINVAL; + rt_uint32_t u32OpMode; + + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + if (cnt <= 1 || cnt > 0xFFFFFF) + { + goto exit_nu_timer_start; + } + + switch (opmode) + { + case HWTIMER_MODE_PERIOD: + u32OpMode = TIMER_PERIODIC_MODE; + break; + + case HWTIMER_MODE_ONESHOT: + u32OpMode = TIMER_ONESHOT_MODE; + break; + + default: + goto exit_nu_timer_start; + } + + TIMER_SET_CMP_VALUE(psNuTmr->base, cnt); + TIMER_SET_OPMODE(psNuTmr->base, u32OpMode); + TIMER_EnableInt(psNuTmr->base); + NVIC_EnableIRQ(psNuTmr->irqn); + + TIMER_Start(psNuTmr->base); + + ret = RT_EOK; + +exit_nu_timer_start: + + return -(ret); +} + +static void nu_timer_stop(rt_hwtimer_t *timer) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + NVIC_DisableIRQ(psNuTmr->irqn); + TIMER_DisableInt(psNuTmr->base); + TIMER_Stop(psNuTmr->base); + TIMER_ResetCounter(psNuTmr->base); +} + +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + return TIMER_GetCounter(psNuTmr->base); +} + +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t ret = RT_EOK; + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + uint32_t clk; + uint32_t pre; + + clk = TIMER_GetModuleClock(psNuTmr->base); + pre = clk / *((uint32_t *)args) - 1; + TIMER_SET_PRESCALE_VALUE(psNuTmr->base, pre); + *((uint32_t *)args) = clk / (pre + 1) ; + } + break; + + case HWTIMER_CTRL_STOP: + TIMER_Stop(psNuTmr->base); + break; + + default: + ret = RT_EINVAL; + break; + } + + return -(ret); +} + +/** + * All UART interrupt service routine + */ +static void nu_timer_isr(nu_timer_t psNuTmr) +{ + RT_ASSERT(psNuTmr != RT_NULL); + + if (TIMER_GetIntFlag(psNuTmr->base)) + { + TIMER_ClearIntFlag(psNuTmr->base); + rt_device_hwtimer_isr(&psNuTmr->parent); + } +} + +static int rt_hw_timer_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + for (i = (TIMER_START + 1); i < TIMER_CNT; i++) + { + CLK_EnableModuleClock(nu_timer_arr[i].modid); + + SYS_ResetModule(nu_timer_arr[i].rstidx); + + /* Register Timer information. */ + nu_timer_arr[i].parent.info = &nu_timer_info; + + /* Register Timer operation. */ + nu_timer_arr[i].parent.ops = &nu_timer_ops; + + /* Register RT hwtimer device. */ + ret = rt_device_hwtimer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + return 0; +} + +INIT_BOARD_EXPORT(rt_hw_timer_init); +#if defined(BSP_USING_TIMER0) +DEFINE_TIMER_IRQ_HANDLER(0) +#endif + +#if defined(BSP_USING_TIMER1) +DEFINE_TIMER_IRQ_HANDLER(1) +#endif + +#if defined(BSP_USING_TIMER2) +DEFINE_TIMER_IRQ_HANDLER(2) +#endif + +#if defined(BSP_USING_TIMER3) +DEFINE_TIMER_IRQ_HANDLER(3) +#endif + +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_tpwm.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_tpwm.c new file mode 100644 index 00000000000..e99b0de8a00 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_tpwm.c @@ -0,0 +1,232 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_TPWM) + +#include "NuMicro.h" +#include "rtdbg.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.tpwm" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define TPWM_CHANNEL_NUM 1 +#define NU_TPWM_DEVICE(tpwm) (nu_tpwm_t)(tpwm) +#define DEFINE_NU_TPWM(_idx) \ + { \ + .name = "tpwm" #_idx, \ + .base = TIMER##_idx, \ + .rstidx = TMR##_idx##_RST, \ + .modid = TMR##_idx##_MODULE \ + } + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + TPWM_START = -1, +#if defined(BSP_USING_TPWM0) + TPWM0_IDX, +#endif +#if defined(BSP_USING_TPWM1) + TPWM1_IDX, +#endif +#if defined(BSP_USING_TPWM2) + TPWM2_IDX, +#endif +#if defined(BSP_USING_TPWM3) + TPWM3_IDX, +#endif + TPWM_CNT +}; + +struct nu_tpwm +{ + struct rt_device_pwm tpwm_dev; + char *name; + TIMER_T *base; + uint32_t rstidx; + uint32_t modid; + rt_uint32_t channel_mask; +} ; + +typedef struct nu_tpwm *nu_tpwm_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable); +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_tpwm nu_tpwm_arr [] = +{ +#if defined(BSP_USING_TPWM0) + DEFINE_NU_TPWM(0), +#endif +#if defined(BSP_USING_TPWM1) + DEFINE_NU_TPWM(1), +#endif +#if defined(BSP_USING_TPWM2) + DEFINE_NU_TPWM(2), +#endif +#if defined(BSP_USING_TPWM3) + DEFINE_NU_TPWM(3), +#endif +}; + +static struct rt_pwm_ops nu_tpwm_ops = +{ + nu_tpwm_control +}; + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + rt_uint32_t tpwm_channel = tpwm_config->channel; + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + if (enable == RT_TRUE) + { + if (psNuTPWM->channel_mask == 0) + { + TPWM_START_COUNTER(psNuTPWM->base); + } + psNuTPWM->channel_mask |= (1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(psNuTPWM->base, psNuTPWM->channel_mask); + } + else + { + psNuTPWM->channel_mask &= ~(1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(psNuTPWM->base, psNuTPWM->channel_mask); + if (psNuTPWM->channel_mask == 0) + { + TPWM_STOP_COUNTER(psNuTPWM->base); + } + } + + return result; +} + +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + if (tpwm_config->period <= 0) + return -(RT_ERROR); + + rt_uint32_t tpwm_freq, tpwm_dutycycle ; + rt_uint32_t tpwm_period = tpwm_config->period; + rt_uint32_t tpwm_pulse = tpwm_config->pulse; + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + rt_uint32_t pre_tpwm_prescaler = TPWM_GET_PRESCALER(psNuTPWM->base); + + tpwm_freq = 1000000000 / tpwm_period; + tpwm_dutycycle = (tpwm_pulse * 100) / tpwm_period; + + LOG_I("[%s, %s] Period: %d", __func__, psNuTPWM->name, tpwm_config->period); + LOG_I("[%s, %s] Pulse: %d", __func__, psNuTPWM->name, tpwm_config->pulse); + + LOG_I("[%s, %s] Freq: %d", __func__, psNuTPWM->name, tpwm_freq); + LOG_I("[%s, %s] Duty: %d", __func__, psNuTPWM->name, tpwm_dutycycle); + + TPWM_ConfigOutputFreqAndDuty(psNuTPWM->base, tpwm_freq, tpwm_dutycycle) ; + + return RT_EOK; +} + +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + rt_uint32_t tpwm_real_period, tpwm_real_duty, time_tick, u32TPWMClockFreq ; + + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + rt_uint32_t tpwm_prescale = TPWM_GET_PRESCALER(psNuTPWM->base); + rt_uint32_t tpwm_period = TPWM_GET_PERIOD(psNuTPWM->base); + rt_uint32_t tpwm_pulse = TPWM_GET_CMPDAT(psNuTPWM->base); + + u32TPWMClockFreq = TIMER_GetModuleClock(psNuTPWM->base); + time_tick = (uint64_t)1000000000000 / u32TPWMClockFreq; + + LOG_I("[%s, %s] Prescale: %d", __func__, psNuTPWM->name, tpwm_prescale); + LOG_I("[%s, %s] Period: %d", __func__, psNuTPWM->name, tpwm_period); + LOG_I("[%s, %s] Pulse: %d", __func__, psNuTPWM->name, tpwm_pulse); + LOG_I("[%s, %s] ModuleFreq: %d", __func__, psNuTPWM->name, u32TPWMClockFreq); + LOG_I("[%s, %s] Tick: %d", __func__, psNuTPWM->name, time_tick); + + tpwm_real_period = (((tpwm_prescale + 1) * (tpwm_period + 1)) * time_tick) / 1000; + tpwm_real_duty = (((tpwm_prescale + 1) * tpwm_pulse * time_tick)) / 1000; + tpwm_config->period = tpwm_real_period; + tpwm_config->pulse = tpwm_real_duty; + + LOG_I("[%s, %s] Channel: %d", __func__, psNuTPWM->name, tpwm_config->channel); + LOG_I("[%s, %s] Period: %d", __func__, psNuTPWM->name, tpwm_config->period); + LOG_I("[%s, %s] Pulse: %d", __func__, psNuTPWM->name, tpwm_config->pulse); + + return RT_EOK; +} + +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg) +{ + struct rt_pwm_configuration *tpwm_config = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(tpwm_dev != RT_NULL); + RT_ASSERT(tpwm_config != RT_NULL); + + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + RT_ASSERT(psNuTPWM != RT_NULL); + RT_ASSERT(psNuTPWM->base != RT_NULL); + + if ((tpwm_config->channel + 1) > TPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_FALSE); + case PWM_CMD_SET: + return nu_tpwm_set(tpwm_dev, tpwm_config); + case PWM_CMD_GET: + return nu_tpwm_get(tpwm_dev, tpwm_config); + default: + break; + } + return -(RT_EINVAL); +} + +int rt_hw_tpwm_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + for (i = (TPWM_START + 1); i < TPWM_CNT; i++) + { + nu_tpwm_arr[i].channel_mask = 0; + + CLK_EnableModuleClock(nu_tpwm_arr[i].modid); + + SYS_ResetModule(nu_tpwm_arr[i].rstidx); + + TPWM_ENABLE_PWM_MODE(nu_tpwm_arr[i].base); + + /* Register RT PWM device. */ + ret = rt_device_pwm_register(&nu_tpwm_arr[i].tpwm_dev, nu_tpwm_arr[i].name, &nu_tpwm_ops, &nu_tpwm_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_tpwm_init); + +#endif //#if defined(BSP_USING_TPWM) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c new file mode 100644 index 00000000000..da61a899b9a --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c @@ -0,0 +1,882 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_UART) + +#include "NuMicro.h" +#include "drv_pdma.h" +#include "drv_uart.h" +#include "rtdbg.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.uart" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_INFO +#define DBG_COLOR +#define UART_BUS_IDLE_TIMEOUT_ENABLE(uart) (UART_ENABLE_INT(uart, UART_INTEN_TOCNTEN_Msk)) +#define UART_BUS_IDLE_TIMEOUT_DISABLE(uart) (UART_DISABLE_INT(uart, UART_INTEN_TOCNTEN_Msk)) +#define CONFIG_UART_USE_IDLE_TIMER + +#if defined(CONFIG_UART_USE_IDLE_TIMER) +#define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE) +#define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk) +#define CONFIG_UART_IDLE_TIMEOUT_VALUE (50) +#define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (0) +#else +#define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) +#define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk) +#define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (1000000 * 10 * (1 + psNuUart->dev.config.data_bits + (psNuUart->dev.config.stop_bits + 1)) / psNuUart->dev.config.baud_rate) +#endif +#define CONFIG_UART_USE_TXDMA_IT (UART_INTEN_TXPDMAEN_Msk) +#define MAKE_UART_NAME(x) #x +#define MAKE_PDMA_UART_TX(x) PDMA_UART##x##_TX +#define MAKE_PDMA_UART_RX(x) PDMA_UART##x##_RX + +#if defined(RT_SERIAL_USING_DMA) +#define MAKE_UART_INSTANCE(x, t, r) \ + { \ + .name = MAKE_UART_NAME(uart##x), \ + .base = UART##x, \ + .rst = UART##x##_RST, \ + .irqn = UART##x##_IRQn, \ + .pdma_perp_tx = t, \ + .pdma_perp_rx = r, \ + }, +#else +#define MAKE_UART_INSTANCE(x, t, r) \ + { \ + .name = MAKE_UART_NAME(uart##x), \ + .base = UART##x, \ + .rst = UART##x##_RST, \ + .irqn = UART##x##_IRQn, \ + }, +#endif + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + UART_START = -1, +#if defined(BSP_USING_UART0) + UART0_IDX, +#endif +#if defined(BSP_USING_UART1) + UART1_IDX, +#endif +#if defined(BSP_USING_UART2) + UART2_IDX, +#endif +#if defined(BSP_USING_UART3) + UART3_IDX, +#endif +#if defined(BSP_USING_UART4) + UART4_IDX, +#endif + UART_CNT +}; + +struct nu_rxbuf_ctx +{ + uint8_t *pu8RxBuf; + uint32_t bufsize; + uint32_t put_index; + uint32_t reserved; +}; +typedef struct nu_rxbuf_ctx *nu_rxbuf_ctx_t; +struct nu_uart +{ + rt_serial_t dev; + char *name; + UART_T *base; + uint32_t rst; + IRQn_Type irqn; +#if defined(RT_SERIAL_USING_DMA) + uint32_t dma_flag; + uint32_t pdma_perp_tx; + uint32_t pdma_chanid_tx; + + uint32_t pdma_perp_rx; + uint32_t pdma_chanid_rx; + + nu_pdma_desc_t pdma_rx_desc; + struct nu_rxbuf_ctx dmabuf; +#endif + +}; +typedef struct nu_uart *nu_uart_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_uart_send(struct rt_serial_device *serial, char c); +static int nu_uart_receive(struct rt_serial_device *serial); +static void nu_uart_isr(nu_uart_t serial); +#if defined(RT_SERIAL_USING_DMA) + static rt_ssize_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); + static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events); + static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events); +#endif + +/* Static Variables ----------------------------------------------------------*/ +static const struct rt_uart_ops nu_uart_ops = +{ + .configure = nu_uart_configure, + .control = nu_uart_control, + .putc = nu_uart_send, + .getc = nu_uart_receive, +#if defined(RT_SERIAL_USING_DMA) + .dma_transmit = nu_uart_dma_transmit +#else + .dma_transmit = RT_NULL +#endif +}; + +static const struct serial_configure nu_uart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_uart nu_uart_arr [] = +{ +#if defined(BSP_USING_UART0) + MAKE_UART_INSTANCE(0, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART0_TX_DMA) + MAKE_PDMA_UART_TX(0), +#else + NU_PDMA_UNUSED, +#endif +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART0_RX_DMA) + MAKE_PDMA_UART_RX(0) +#else + NU_PDMA_UNUSED +#endif + ) +#endif + +#if defined(BSP_USING_UART1) + MAKE_UART_INSTANCE(1, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART1_TX_DMA) + MAKE_PDMA_UART_TX(1), +#else + NU_PDMA_UNUSED, +#endif +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART1_RX_DMA) + MAKE_PDMA_UART_RX(1) +#else + NU_PDMA_UNUSED +#endif + ) +#endif + +#if defined(BSP_USING_UART2) + MAKE_UART_INSTANCE(2, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART2_TX_DMA) + MAKE_PDMA_UART_TX(2), +#else + NU_PDMA_UNUSED, +#endif +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART2_RX_DMA) + MAKE_PDMA_UART_RX(2) +#else + NU_PDMA_UNUSED +#endif + ) +#endif + +#if defined(BSP_USING_UART3) + MAKE_UART_INSTANCE(3, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART3_TX_DMA) + MAKE_PDMA_UART_TX(3), +#else + NU_PDMA_UNUSED, +#endif +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART3_RX_DMA) + MAKE_PDMA_UART_RX(3) +#else + NU_PDMA_UNUSED +#endif + ) +#endif + +#if defined(BSP_USING_UART4) + MAKE_UART_INSTANCE(4, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART4_TX_DMA) + MAKE_PDMA_UART_TX(4), +#else + NU_PDMA_UNUSED, +#endif +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_UART4_RX_DMA) + MAKE_PDMA_UART_RX(4) +#else + NU_PDMA_UNUSED +#endif + ) +#endif + {0} +}; + +/* Functions Implementation --------------------------------------------------*/ +#define MAKE_UART_ISR(x) \ + void UART##x##_IRQHandler(void) \ + { \ + rt_interrupt_enter(); \ + nu_uart_isr(&nu_uart_arr[UART##x##_IDX]); \ + rt_interrupt_leave(); \ + } +#if defined(BSP_USING_UART0) + MAKE_UART_ISR(0); +#endif + +#if defined(BSP_USING_UART1) + MAKE_UART_ISR(1); +#endif + +#if defined(BSP_USING_UART2) + MAKE_UART_ISR(2); +#endif + +#if defined(BSP_USING_UART3) + MAKE_UART_ISR(3); +#endif + +#if defined(BSP_USING_UART4) + MAKE_UART_ISR(4); +#endif + +/** + * All UART interrupt service routine + */ +static void nu_uart_isr(nu_uart_t psNuUart) +{ + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Get interrupt event */ + uint32_t u32IntSts = base->INTSTS; + uint32_t u32FIFOSts = base->FIFOSTS; +#if defined(RT_SERIAL_USING_DMA) + if (u32IntSts & UART_INTSTS_HWRLSIF_Msk) + { + /* Drain RX FIFO to remove remain FEF frames in FIFO. */ + base->FIFO |= UART_FIFO_RXRST_Msk; + base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk); + return; + } +#if defined(CONFIG_UART_USE_IDLE_TIMER) + if (u32IntSts & UART_INTSTS_HWTOIF_Msk) + { + /* In UART RX PDMA mode, bus idle timeout occurred. */ + nu_pdma_uart_rx_cb((void *)psNuUart, NU_PDMA_EVENT_TIMEOUT); + + /* clear int flag */ + base->INTSTS = u32IntSts; + return; + } +#endif + +#endif + + /* Handle RX event */ + if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) + { + rt_hw_serial_isr(&psNuUart->dev, RT_SERIAL_EVENT_RX_IND); + } + + base->INTSTS = u32IntSts; + base->FIFOSTS = u32FIFOSts; +} + +/** + * Set RS-485 AUD mode + */ +void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + UART_T *base; + RT_ASSERT(serial); + + /* Get base address of uart register */ + base = ((nu_uart_t)serial)->base; + + /* Set RTS as RS-485 phy direction controlling ping. */ + UART_SelectRS485Mode(base, UART_ALTCTL_RS485AUD_Msk, 0); + + if (bRTSActiveLowLevel) + { + /* Set direction pin as active-low. */ + base->MODEM |= UART_MODEM_RTSACTLV_Msk; + } + else + { + /* Set direction pin as active-high. */ + base->MODEM &= ~UART_MODEM_RTSACTLV_Msk; + } + + LOG_I("Set %s to RS-485 AUD function mode. ActiveLowLevel-%s", psNuUart->name, bRTSActiveLowLevel ? "YES" : "NO"); +} + +/** + * Configure uart port + */ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + rt_err_t ret = RT_EOK; + uint32_t uart_word_len, uart_stop_bit, uart_parity; + + RT_ASSERT(serial); + RT_ASSERT(cfg); + + /* Check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + uart_word_len = uart_stop_bit = uart_parity = 0; + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + + default: + LOG_E("Unsupported data length."); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + + default: + LOG_E("Unsupported stop bit."); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + switch (cfg->parity) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + + default: + LOG_E("Unsupported parity."); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + SYS_ResetModule(psNuUart->rst); + + /* Open Uart and set UART Baudrate */ + UART_Open(base, cfg->baud_rate); + + /* Set line configuration. */ + UART_SetLineConfig(base, 0, uart_word_len, uart_parity, uart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(psNuUart->irqn); + +exit_nu_uart_configure: + + if (ret != RT_EOK) + UART_Close(base); + + return -(ret); +} +#if defined(RT_SERIAL_USING_DMA) + +static void nu_pdma_uart_rxbuf_free(nu_uart_t psNuUart) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)psNuUart; + + if ((serial->config.bufsz > 0) && psNuUart->dmabuf.pu8RxBuf) + rt_free_align(psNuUart->dmabuf.pu8RxBuf); + + psNuUart->dmabuf.pu8RxBuf = RT_NULL; + psNuUart->dmabuf.bufsize = 0; + psNuUart->dmabuf.put_index = 0; +} + +static rt_err_t nu_pdma_uart_rx_config(nu_uart_t psNuUart, uint8_t *pu8Buf, int32_t i32TriggerLen) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)psNuUart; + + rt_err_t result = RT_EOK; + struct nu_pdma_chn_cb sChnCB; + + uint32_t u32IdleTimeoutInUs = 1500; + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uart_rx_cb; + sChnCB.m_pvUserData = (void *)psNuUart; + + nu_pdma_filtering_set(psNuUart->pdma_chanid_rx, CONFIG_PDMA_USE_IT); + result = nu_pdma_callback_register(psNuUart->pdma_chanid_rx, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } +#if defined(CONFIG_UART_USE_IDLE_TIMER) + LOG_I("[%s] Set UART bus idle time to %d bit time.", psNuUart->name, CONFIG_UART_IDLE_TIMEOUT_VALUE); +#else + LOG_I("[%s] Set PDMA idle time out %d us", psNuUart->name, CONFIG_PDMA_IDLE_TIMEOUT_VALUE); +#endif + + LOG_I("[%s] bufsz: %d B", psNuUart->name, serial->config.bufsz); + + if (serial->config.bufsz == 0) + { + psNuUart->dmabuf.bufsize = i32TriggerLen; + psNuUart->dmabuf.put_index = 0; + psNuUart->dmabuf.pu8RxBuf = pu8Buf; + + result = nu_pdma_transfer(psNuUart->pdma_chanid_rx, + 8, + (uint32_t)&base->DAT, + (uint32_t)pu8Buf, + i32TriggerLen, + CONFIG_PDMA_IDLE_TIMEOUT_VALUE); //Idle-timeout + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + } + else + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; +#if defined(RT_USING_CACHE) + /* Allocate aligned and align-up DMA buffer for cache coherence. */ + psNuUart->dmabuf.pu8RxBuf = rt_malloc_align(RT_ALIGN(i32TriggerLen, 32), 32); + psNuUart->dmabuf.bufsize = 0; + if (psNuUart->dmabuf.pu8RxBuf == RT_NULL) + { + LOG_E("Failed to allocate dma memory %d.", i32TriggerLen); + goto exit_nu_pdma_uart_rx_config; + } + rx_fifo->buffer = (rt_uint8_t *) psNuUart->dmabuf.pu8RxBuf; + rt_memset(rx_fifo->buffer, 0, i32TriggerLen); +#endif + psNuUart->dmabuf.bufsize = i32TriggerLen; + psNuUart->dmabuf.put_index = 0; + + /* For Serial RX FIFO - Single buffer recycle SG trigger */ + result = nu_pdma_desc_setup(psNuUart->pdma_chanid_rx, + psNuUart->pdma_rx_desc, + 8, + (uint32_t)&base->DAT, + (uint32_t)rx_fifo->buffer, + i32TriggerLen, + psNuUart->pdma_rx_desc, + 0); + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + result = nu_pdma_sg_transfer(psNuUart->pdma_chanid_rx, psNuUart->pdma_rx_desc, CONFIG_PDMA_IDLE_TIMEOUT_VALUE); + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + } +#if defined(CONFIG_UART_USE_IDLE_TIMER) + UART_SetTimeoutCnt(base, CONFIG_UART_IDLE_TIMEOUT_VALUE); + UART_BUS_IDLE_TIMEOUT_ENABLE(base); +#endif + + /* Enable Receive Line interrupt & Start DMA RX transfer. */ + UART_ENABLE_INT(base, CONFIG_UART_USE_RXDMA_IT); + +exit_nu_pdma_uart_rx_config: + + return result; +} + +static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uart_t psNuUart = (nu_uart_t)pvOwner; + struct rt_serial_device *serial = (struct rt_serial_device *)psNuUart; + rt_size_t recv_len = 0; + uint32_t dma_put_index = 0; + + RT_ASSERT(psNuUart); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + nu_rxbuf_ctx_t psNuRxBufCtx = &psNuUart->dmabuf; + + dma_put_index = nu_pdma_transferred_byte_get(psNuUart->pdma_chanid_rx, psNuRxBufCtx->bufsize); + if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)) + { + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + dma_put_index = psNuRxBufCtx->bufsize; + } + else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UART_GET_RX_EMPTY(base)) + { + return; + } + + recv_len = dma_put_index - psNuRxBufCtx->put_index; + + if (recv_len > 0) + { + psNuRxBufCtx->put_index = dma_put_index % psNuRxBufCtx->bufsize; + } + } + + if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)) + { + recv_len = psNuRxBufCtx->bufsize; + } + + if (recv_len > 0) + { + rt_hw_serial_isr(&psNuUart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static rt_err_t nu_pdma_uart_tx_config(nu_uart_t psNuUart) +{ + struct nu_pdma_chn_cb sChnCB; + RT_ASSERT(psNuUart); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uart_tx_cb; + sChnCB.m_pvUserData = (void *)psNuUart; + + nu_pdma_filtering_set(psNuUart->pdma_chanid_tx, NU_PDMA_EVENT_TRANSFER_DONE); + return nu_pdma_callback_register(psNuUart->pdma_chanid_tx, &sChnCB); +} + +static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uart_t psNuUart = (nu_uart_t)pvOwner; + RT_ASSERT(psNuUart); + + UART_DISABLE_INT(psNuUart->base, CONFIG_UART_USE_TXDMA_IT);// Stop DMA TX transfer + + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Waiting if TX-FIFO is empty. */ + while (!(UART_IS_TX_EMPTY(base))); + + rt_hw_serial_isr(&psNuUart->dev, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * Uart DMA transfer + */ +static rt_ssize_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + rt_err_t result = RT_EOK; + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + RT_ASSERT(buf); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + if (direction == RT_SERIAL_DMA_TX) + { + result = nu_pdma_transfer(psNuUart->pdma_chanid_tx, + 8, + (uint32_t)buf, + (uint32_t)base, + size, + 0); // wait-forever + // Start DMA TX transfer + UART_ENABLE_INT(base, CONFIG_UART_USE_TXDMA_IT); + } + else if (direction == RT_SERIAL_DMA_RX) + { + UART_DISABLE_INT(base, CONFIG_UART_USE_RXDMA_IT); + + // If config.bufsz = 0, serial will trigger once. + result = nu_pdma_uart_rx_config(psNuUart, buf, size); + } + else + { + result = RT_ERROR; + } + + return result; +} + +static int nu_hw_uart_dma_allocate(nu_uart_t psNuUart) +{ + RT_ASSERT(psNuUart); + + /* Allocate UART_TX nu_dma channel */ + if (psNuUart->pdma_perp_tx != NU_PDMA_UNUSED) + { + psNuUart->pdma_chanid_tx = nu_pdma_channel_allocate(psNuUart->pdma_perp_tx); + if (psNuUart->pdma_chanid_tx >= 0) + { + psNuUart->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + } + } + if (psNuUart->pdma_perp_rx != NU_PDMA_UNUSED) + { + psNuUart->pdma_chanid_rx = nu_pdma_channel_allocate(psNuUart->pdma_perp_rx); + if (psNuUart->pdma_chanid_rx >= 0) + { + rt_err_t ret = RT_EOK; + psNuUart->dma_flag |= RT_DEVICE_FLAG_DMA_RX; + ret = nu_pdma_sgtbls_allocate(psNuUart->pdma_chanid_rx, &psNuUart->pdma_rx_desc, 1); + RT_ASSERT(ret == RT_EOK); + } + } + + return RT_EOK; +} + +int8_t nu_uart_get_rx_pdma_chnid(struct rt_serial_device *serial) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + return psNuUart->pdma_chanid_rx; +} + +struct nu_rxbuf_ctx *nu_uart_get_rx_pdma_bufaddr(struct rt_serial_device *serial) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + return &psNuUart->dmabuf; +} + +int8_t nu_uart_get_tx_pdma_chnid(struct rt_serial_device *serial) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + return psNuUart->pdma_chanid_tx; +} +#endif + +/** + * Uart interrupt control + */ +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + rt_err_t result = RT_EOK; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + UART_DISABLE_INT(base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + /* Disable Receive Line interrupt & Stop DMA RX transfer. */ +#if defined(RT_SERIAL_USING_DMA) + if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx); + nu_pdma_uart_rxbuf_free(psNuUart); + } + UART_DISABLE_INT(base, CONFIG_UART_USE_RXDMA_IT); +#if defined(CONFIG_UART_USE_IDLE_TIMER) + UART_BUS_IDLE_TIMEOUT_DISABLE(base); +#endif + +#endif + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + UART_ENABLE_INT(base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + break; +#if defined(RT_SERIAL_USING_DMA) + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */ + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + result = nu_pdma_uart_rx_config(psNuUart, rx_fifo->buffer, serial->config.bufsz); // Config & trigger + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */ + { + result = nu_pdma_uart_tx_config(psNuUart); + } + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(psNuUart->irqn); +#if defined(RT_SERIAL_USING_DMA) + +#if defined(CONFIG_UART_USE_IDLE_TIMER) + UART_BUS_IDLE_TIMEOUT_DISABLE(base); +#endif + + UART_DISABLE_INT(base, CONFIG_UART_USE_RXDMA_IT); + UART_DISABLE_INT(base, CONFIG_UART_USE_TXDMA_IT); + + if (psNuUart->dma_flag != 0) + { + nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx); + nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx); + nu_pdma_uart_rxbuf_free(psNuUart); + } +#endif + + /* Close UART port */ + UART_Close(base); + + break; + + default: + /* Flush TX FIFO */ + UART_WAIT_TX_EMPTY(base); + result = -RT_EINVAL; + break; + + } + return result; +} + +/** + * Uart put char + */ +static int nu_uart_send(struct rt_serial_device *serial, char c) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Waiting if TX-FIFO is full. */ + while (UART_IS_TX_FULL(base)); + + /* Put char into TX-FIFO */ + UART_WRITE(base, c); + + return 1; +} + +/** + * Uart get char + */ +static int nu_uart_receive(struct rt_serial_device *serial) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + /* Return failure if RX-FIFO is empty. */ + if (UART_GET_RX_EMPTY(base)) + { + return -1; + } + return UART_READ(base); +} + +void nu_uart_set_loopback(struct rt_serial_device *serial, rt_bool_t bOn) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *base = psNuUart->base; + + bOn ? (base->MODEM |= 0x10) : (base->MODEM &= ~0x10); +} + +/** + * Hardware UART Initialization + */ +rt_err_t rt_hw_uart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (UART_START + 1); i < UART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_uart_arr[i].dev.ops = &nu_uart_ops; + nu_uart_arr[i].dev.config = nu_uart_default_config; +#if defined(RT_SERIAL_USING_DMA) + nu_uart_arr[i].dma_flag = 0; + nu_hw_uart_dma_allocate(&nu_uart_arr[i]); + flag |= nu_uart_arr[i].dma_flag; + rt_memset(&nu_uart_arr[i].dmabuf, 0, sizeof(struct nu_rxbuf_ctx)); +#endif + + ret = rt_hw_serial_register(&nu_uart_arr[i].dev, nu_uart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + + } + + return ret; +} +#endif //#if defined(BSP_USING_UART) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.h new file mode 100644 index 00000000000..dbd9e1d8b0a --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.h @@ -0,0 +1,15 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ +#include "rtdevice.h" + +rt_err_t rt_hw_uart_init(void); + +void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel); + +#endif /* __DRV_UART_H__ */ \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c new file mode 100644 index 00000000000..dd9b105babb --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c @@ -0,0 +1,387 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_UI2C) && defined(RT_USING_I2C) + +#include "NuMicro.h" +#include "rtdevice.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.ui2c" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#define SLV_10BIT_ADDR (0x1E << 2) +#define DEFINE_NU_UI2C(_idx, _rst) \ + { \ + .base = UI2C##_idx, \ + .name = "ui2c" #_idx, \ + .rst = _rst, \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + UI2C_START = -1, +#if defined(BSP_USING_UI2C0) + UI2C0_IDX, +#endif +#if defined(BSP_USING_UI2C1) + UI2C1_IDX, +#endif + UI2C_CNT +}; + +struct nu_ui2c +{ + struct rt_i2c_bus_device parent; + char *name; + UI2C_T *base; + uint32_t rst; + struct rt_i2c_msg *msg; +}; +typedef struct nu_ui2c *nu_ui2c_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); +static rt_err_t nu_ui2c_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value); + +/* Static Variables ----------------------------------------------------------*/ +static struct nu_ui2c nu_ui2c_arr [ ] = +{ +#if defined(BSP_USING_UI2C0) + DEFINE_NU_UI2C(0, USCI0_RST), +#endif +#if defined(BSP_USING_UI2C1) + DEFINE_NU_UI2C(1, USCI1_RST), +#endif +}; + +static const struct rt_i2c_bus_device_ops nu_ui2c_ops = +{ + .master_xfer = nu_ui2c_mst_xfer, + .slave_xfer = NULL, + .i2c_bus_control = nu_ui2c_control, +}; + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_ui2c_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value) +{ + nu_ui2c_t psNuUi2c = (nu_ui2c_t) bus; + RT_ASSERT(bus); + + switch (u32Cmd) + { + case RT_I2C_DEV_CTRL_CLK: + UI2C_SetBusClockFreq(psNuUi2c->base, u32Value); + break; + default: + return -RT_EIO; + } + + return RT_EOK; +} + +static rt_err_t nu_ui2c_wait_ready_with_timeout(nu_ui2c_t psNuUi2c) +{ + rt_tick_t start = rt_tick_get(); + uint32_t u32ProtSts; + while ((u32ProtSts = UI2C_GET_PROT_STATUS(psNuUi2c->base) & + (UI2C_PROTSTS_STARIF_Msk | + UI2C_PROTSTS_ACKIF_Msk | + UI2C_PROTSTS_NACKIF_Msk | + UI2C_PROTSTS_STORIF_Msk)) == 0) + { + if ((rt_tick_get() - start) > psNuUi2c->parent.timeout) + { + LOG_E("timeout! (%d - %d > %d) ProtSts=0x%08x", rt_tick_get(), start, psNuUi2c->parent.timeout, u32ProtSts); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static rt_err_t nu_ui2c_send_data(nu_ui2c_t psNuUi2c, rt_uint8_t data) +{ + UI2C_SET_DATA(psNuUi2c->base, data); + UI2C_SET_CONTROL_REG(psNuUi2c->base, UI2C_CTL_PTRG); + + return nu_ui2c_wait_ready_with_timeout(psNuUi2c); +} + +static rt_err_t nu_ui2c_send_address(nu_ui2c_t psNuUi2c, + struct rt_i2c_msg *msg) + { + rt_uint16_t flags = msg->flags; + rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + rt_uint8_t addr1, addr2; + rt_err_t ret; + + if (flags & RT_I2C_ADDR_10BIT) + { + UI2C_ENABLE_10BIT_ADDR_MODE(psNuUi2c->base); + /* Init Send 10-bit Addr */ + addr1 = ((msg->addr >> 8) | SLV_10BIT_ADDR) << 1; + addr2 = msg->addr & 0xff; + + LOG_D("addr1: %d, addr2: %d\n", addr1, addr2); + + ret = nu_ui2c_send_data(psNuUi2c, addr1); + if (ret != RT_EOK) //for timeout condition + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending first addr\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + + ret = nu_ui2c_send_data(psNuUi2c, addr2); + if (ret != RT_EOK) //for timeout condition + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending second addr\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + + if (flags & RT_I2C_RD) + { + LOG_D("send repeated start condition\n"); + + UI2C_SET_CONTROL_REG(psNuUi2c->base, (UI2C_CTL_PTRG | UI2C_CTL_STA)); + ret = nu_ui2c_wait_ready_with_timeout(psNuUi2c); + if (ret != RT_EOK) //for timeout condition + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk) && !ignore_nack) + { + LOG_E("sending repeated START fail\n"); + + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_STARIF_Msk); + + addr1 |= RT_I2C_RD; + + ret = nu_ui2c_send_data(psNuUi2c, addr1); + if (ret != RT_EOK) //for timeout condition + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) + { + LOG_E("NACK: sending repeated addr\n"); + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + } + } + else + { + /* 7-bit addr */ + addr1 = msg->addr << 1; + if (flags & RT_I2C_RD) + addr1 |= RT_I2C_RD; + + /* Send device address */ + ret = nu_ui2c_send_data(psNuUi2c, addr1); /* Send Address */ + if (ret != RT_EOK) //for timeout condition + return -RT_EIO; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) + && !ignore_nack) + { + LOG_E("sending addr fail\n"); + return -RT_EIO; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + } + + return RT_EOK; +} + +static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) + { + struct rt_i2c_msg *msg; + rt_size_t i = 0; + rt_uint32_t cnt_data; + rt_uint16_t ignore_nack; + rt_err_t ret; + nu_ui2c_t psNuUi2c = (nu_ui2c_t) bus; + + RT_ASSERT(bus); + + /* Clear status */ + (psNuUi2c->base)->PROTSTS = (psNuUi2c->base)->PROTSTS; + + UI2C_SET_CONTROL_REG(psNuUi2c->base, UI2C_CTL_STA); + ret = nu_ui2c_wait_ready_with_timeout(psNuUi2c); + if (ret != RT_EOK) //for timeout condition + { + rt_set_errno(-RT_ETIMEOUT); + goto fail_nu_ui2c_mst_xfer; + } + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) + { + LOG_E("Send START Fail"); + goto fail_nu_ui2c_mst_xfer; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_STARIF_Msk); + + psNuUi2c->msg = msgs; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + + if (!(msg->flags & RT_I2C_NO_START)) + { + if (i > 0) + { + UI2C_SET_CONTROL_REG(psNuUi2c->base, (UI2C_CTL_PTRG | UI2C_CTL_STA));/* Send repeat START */ + ret = nu_ui2c_wait_ready_with_timeout(psNuUi2c); + if (ret != RT_EOK) //for timeout condition + break; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send repeat START */ + { + i = 0; + LOG_E("Send repeat START Fail"); + break; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_STARIF_Msk); + } + + if ((RT_EOK != nu_ui2c_send_address(psNuUi2c, msg)) + && !ignore_nack) + { + i = 0; + //LOG_E("Send Address Fail"); + break; + } + } + + if (psNuUi2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */ + { + rt_uint32_t do_rd_nack = (i == (num - 1)); + for (cnt_data = 0 ; cnt_data < (psNuUi2c->msg[i].len) ; cnt_data++) + { + /* NACK after last byte for hardware setting */ + do_rd_nack += (cnt_data == (psNuUi2c->msg[i].len - 1)); + if (do_rd_nack == 2) + { + UI2C_SET_CONTROL_REG(psNuUi2c->base, UI2C_CTL_PTRG); + } + else + { + UI2C_SET_CONTROL_REG(psNuUi2c->base, (UI2C_CTL_PTRG | UI2C_CTL_AA)); + } + ret = nu_ui2c_wait_ready_with_timeout(psNuUi2c); + if (ret != RT_EOK) + break; + + if (psNuUi2c->base->PROTCTL & UI2C_CTL_AA) + { + /*Master Receive Data ACK*/ + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk)) + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + } + else + { + /*Master Receive Data NACK*/ + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_NACKIF_Msk) != UI2C_PROTSTS_NACKIF_Msk)) + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_NACKIF_Msk); + } + + psNuUi2c->msg[i].buf[cnt_data] = psNuUi2c->base->RXDAT; + } + } + else /* Send Bytes */ + { + for (cnt_data = 0 ; cnt_data < (psNuUi2c->msg[i].len) ; cnt_data++) + { + /* Send register number and MSB of data */ + ret = nu_ui2c_send_data(psNuUi2c, (uint8_t)(psNuUi2c->msg[i].buf[cnt_data])); + if (ret != RT_EOK) //for timeout condition + break; + + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) + && !ignore_nack + ) /* Send data and get Ack */ + { + i = 0; + break; + } + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_ACKIF_Msk); + } + } + } + UI2C_SET_CONTROL_REG(psNuUi2c->base, (UI2C_CTL_PTRG | UI2C_CTL_STO)); + ret = nu_ui2c_wait_ready_with_timeout(psNuUi2c); + if (ret != RT_EOK) //for timeout condition + { + rt_set_errno(-RT_ETIMEOUT); + goto fail_nu_ui2c_mst_xfer; + } + if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_STORIF_Msk) != UI2C_PROTSTS_STORIF_Msk)) + { + i = 0; + LOG_E("Send STOP Fail"); + } + + UI2C_CLR_PROT_INT_FLAG(psNuUi2c->base, UI2C_PROTSTS_STORIF_Msk); + UI2C_SET_CONTROL_REG(psNuUi2c->base, UI2C_CTL_PTRG); + UI2C_DISABLE_10BIT_ADDR_MODE(psNuUi2c->base); /*clear all sub modes like 10 bit mode*/ + psNuUi2c->msg = RT_NULL; + + return i; + +fail_nu_ui2c_mst_xfer: + + return 0; +} +int rt_hw_ui2c_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (UI2C_START + 1); i < UI2C_CNT; i++) + { + /* Reset and initial IP engine. */ + SYS_ResetModule(nu_ui2c_arr[i].rst); + UI2C_Close(nu_ui2c_arr[i].base); + UI2C_Open(nu_ui2c_arr[i].base, 100000); + nu_ui2c_arr[i].parent.ops = &nu_ui2c_ops; + + ret = rt_i2c_bus_device_register(&nu_ui2c_arr[i].parent, nu_ui2c_arr[i].name); + RT_ASSERT(RT_EOK == ret); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_ui2c_init); +#endif //#if defined(BSP_USING_UI2C) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c new file mode 100644 index 00000000000..792839b36f8 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c @@ -0,0 +1,672 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_USPI) + +#include "NuMicro.h" +#include "drv_pdma.h" +#include "nu_bitutil.h" +#include "rtdef.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.uspi" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD +#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) +#endif + +#if defined(BSP_USING_USPI_PDMA) +#if defined(BSP_USING_USPI0_PDMA) +#define USPI0_PDMA_INIT \ + .pdma_perp_tx = PDMA_USCI0_TX, \ + .pdma_perp_rx = PDMA_USCI0_RX, +#else +#define USPI0_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif + +#if defined(BSP_USING_USPI1_PDMA) +#define USPI1_PDMA_INIT \ + .pdma_perp_tx = PDMA_USCI1_TX, \ + .pdma_perp_rx = PDMA_USCI1_RX, +#else +#define USPI1_PDMA_INIT \ + .pdma_perp_tx = NU_PDMA_UNUSED, \ + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#else +#define USPI0_PDMA_INIT +#define USPI1_PDMA_INIT +#endif + +#define DEFINE_NU_USPI(_idx, _pdma_init) \ + { \ + .name = "uspi" #_idx, \ + .uspi_base = USPI##_idx, \ + _pdma_init \ + } + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + USPI_START = -1, +#if defined(BSP_USING_USPI0) + USPI0_IDX, +#endif +#if defined(BSP_USING_USPI1) + USPI1_IDX, +#endif + USPI_CNT +}; +struct nu_uspi +{ + struct rt_spi_bus dev; + char *name; + USPI_T *uspi_base; + struct rt_spi_configuration configuration; + uint32_t dummy; +#if defined(BSP_USING_USPI_PDMA) + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + rt_sem_t m_psSemBus; +#endif +}; +typedef struct nu_uspi *uspi_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_ssize_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name); +static void nu_uspi_drain_rxfifo(USPI_T *uspi_base); +#if defined(BSP_USING_USPI_PDMA) + static void nu_pdma_uspi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter); + static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); + static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); + static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); + static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus); +#endif + +/* Static Variables ----------------------------------------------------------*/ +static struct rt_spi_ops nu_uspi_poll_ops = +{ + .configure = nu_uspi_bus_configure, + .xfer = nu_uspi_bus_xfer, +}; + +static struct nu_uspi nu_uspi_arr [] = +{ +#if defined(BSP_USING_USPI0) + DEFINE_NU_USPI(0, USPI0_PDMA_INIT), +#endif +#if defined(BSP_USING_USPI1) + DEFINE_NU_USPI(1, USPI1_PDMA_INIT), +#endif +}; /* uspi nu_uspi */ + +/* Functions Implementation --------------------------------------------------*/ +static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) + { + struct nu_uspi *uspi_bus; + uint32_t u32SPIMode; + uint32_t u32BusClock; + rt_err_t ret = RT_EOK; + void *pvUserData; + + RT_ASSERT(device); + RT_ASSERT(configuration); + + uspi_bus = (struct nu_uspi *) device->bus; + pvUserData = device->parent.user_data; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = USPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = USPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = USPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = USPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_uspi_bus_configure; + } + if (!(configuration->data_width == 8 || + configuration->data_width == 16)) + { + ret = RT_EINVAL; + goto exit_nu_uspi_bus_configure; + } + u32BusClock = USPI_SetBusClock(uspi_bus->uspi_base, configuration->max_hz); + if (configuration->max_hz > u32BusClock) + { + LOG_W("%s clock max frequency is %dHz ( != %dHz)\n", uspi_bus->name, u32BusClock, configuration->max_hz); + configuration->max_hz = u32BusClock; + } + if (rt_memcmp(configuration, &uspi_bus->configuration, sizeof(*configuration)) != 0) + { + rt_memcpy(&uspi_bus->configuration, configuration, sizeof(*configuration)); + + USPI_Open(uspi_bus->uspi_base, USPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + if (pvUserData != RT_NULL) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + } + else + { + /* Set CS pin to HIGH */ + if (pvUserData != RT_NULL) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + /* Set CS pin to HIGH */ + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + USPI_SET_MSB_FIRST(uspi_bus->uspi_base); + } + else + { + /* Set sequence to LSB first */ + USPI_SET_LSB_FIRST(uspi_bus->uspi_base); + } + } + nu_uspi_drain_rxfifo(uspi_bus->uspi_base); + +exit_nu_uspi_bus_configure: + + return -(ret); +} + +#if defined(BSP_USING_USPI_PDMA) +static void nu_pdma_uspi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter) +{ + rt_err_t result; + struct nu_uspi *uspi_bus = (struct nu_uspi *)pvUserData; + + RT_ASSERT(uspi_bus); + + result = rt_sem_release(uspi_bus->m_psSemBus); + RT_ASSERT(result == RT_EOK); +} + +static void nu_pdma_uspi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + USPI_T *uspi_base = (USPI_T *)pvUserData; + + /* Trigger TX/RX PDMA transfer. */ + USPI_TRIGGER_TX_RX_PDMA(uspi_base); +} + +static void nu_pdma_uspi_rx_cb_disable(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + USPI_T *uspi_base = (USPI_T *)pvUserData; + + /* Stop TX/RX DMA transfer. */ + USPI_DISABLE_TX_RX_PDMA(uspi_base); +} + +static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result; + rt_uint8_t *dst_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + rt_uint8_t uspi_pdma_rx_chid = uspi_bus->pdma_chanid_rx; + + nu_pdma_filtering_set(uspi_pdma_rx_chid, NU_PDMA_EVENT_TRANSFER_DONE); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uspi_rx_cb_event; + sChnCB.m_pvUserData = (void *)uspi_bus; + result = nu_pdma_callback_register(uspi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_rx_config; + } + sChnCB.m_eCBType = eCBType_Disable; + sChnCB.m_pfnCBHandler = nu_pdma_uspi_rx_cb_disable; + sChnCB.m_pvUserData = (void *)uspi_base; + result = nu_pdma_callback_register(uspi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_rx_config; + } + + if (pu8Buf == RT_NULL) + { + memctrl = eMemCtl_SrcFix_DstFix; + dst_addr = (rt_uint8_t *) &uspi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcFix_DstInc; + dst_addr = pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(uspi_pdma_rx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_rx_config; + } + + result = nu_pdma_transfer(uspi_pdma_rx_chid, + bytes_per_word * 8, + (uint32_t)&uspi_base->RXDAT, + (uint32_t)dst_addr, + i32RcvLen / bytes_per_word, + 0); +exit_nu_pdma_uspi_rx_config: + + return result; +} + +static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result; + rt_uint8_t *src_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of uspi register */ + USPI_T *uspi_base = uspi_bus->uspi_base; + + rt_uint8_t uspi_pdma_tx_chid = uspi_bus->pdma_chanid_tx; + + if (pu8Buf == RT_NULL) + { + uspi_bus->dummy = 0; + memctrl = eMemCtl_SrcFix_DstFix; + src_addr = (rt_uint8_t *)&uspi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcInc_DstFix; + src_addr = (rt_uint8_t *)pu8Buf; + } + sChnCB.m_eCBType = eCBType_Trigger; + sChnCB.m_pfnCBHandler = nu_pdma_uspi_tx_cb_trigger; + sChnCB.m_pvUserData = (void *)uspi_base; + result = nu_pdma_callback_register(uspi_pdma_tx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_tx_config; + } + result = nu_pdma_channel_memctrl_set(uspi_pdma_tx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_uspi_tx_config; + } + + result = nu_pdma_transfer(uspi_pdma_tx_chid, + bytes_per_word * 8, + (uint32_t)src_addr, + (uint32_t)&uspi_base->TXDAT, + i32SndLen / bytes_per_word, + 0); +exit_nu_pdma_uspi_tx_config: + + return result; +} + +/** + * USPI PDMA transfer + **/ +static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + + result = nu_pdma_uspi_rx_config(uspi_bus, recv_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + result = nu_pdma_uspi_tx_config(uspi_bus, send_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + /* Wait RX-PDMA transfer done */ + result = rt_sem_take(uspi_bus->m_psSemBus, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + return length; +} + +static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus) +{ + /* Allocate USPI_TX nu_dma channel */ + if ((uspi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_tx)) < 0) + { + goto exit_nu_hw_uspi_pdma_allocate; + } + else if ((uspi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_rx)) < 0) + { + nu_pdma_channel_free(uspi_bus->pdma_chanid_tx); + goto exit_nu_hw_uspi_pdma_allocate; + } + + uspi_bus->m_psSemBus = rt_sem_create("uspibus_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(uspi_bus->m_psSemBus != RT_NULL); + + return RT_EOK; + +exit_nu_hw_uspi_pdma_allocate: + + return -(RT_ERROR); +} +#endif + +static void nu_uspi_drain_rxfifo(USPI_T *uspi_base) +{ + while (USPI_IS_BUSY(uspi_base)); + + // Drain USPI RX FIFO, make sure RX FIFO is empty + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + USPI_ClearRxBuf(uspi_base); + } +} + +static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per_word) +{ + int size = 0; + + // Read RX data + if (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + uint32_t val; + // Read data from USPI RX FIFO + switch (bytes_per_word) + { + case 2: + val = USPI_READ_RX(uspi_base); + nu_set16_le(recv_addr, val); + break; + case 1: + *recv_addr = USPI_READ_RX(uspi_base); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + size = bytes_per_word; + } + return size; +} + +static int nu_uspi_write(USPI_T *uspi_base, const uint8_t *send_addr, uint8_t bytes_per_word) +{ + // Wait USPI TX send data + while (USPI_GET_TX_FULL_FLAG(uspi_base)); + + // Input data to USPI TX + switch (bytes_per_word) + { + case 2: + USPI_WRITE_TX(uspi_base, nu_get16_le(send_addr)); + break; + case 1: + USPI_WRITE_TX(uspi_base, *((uint8_t *)send_addr)); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + + return bytes_per_word; +} + +/** + * @brief USPI bus polling + * @param dev : The pointer of the specified USPI module. + * @param send_addr : Source address + * @param recv_addr : Destination address + * @param length : Data length + */ +static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + USPI_T *uspi_base = uspi_bus->uspi_base; + + // Write-only + if ((send_addr != RT_NULL) && (recv_addr == RT_NULL)) + { + while (length > 0) + { + send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + } + } + else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL)) + { + uspi_bus->dummy = 0; + while (length > 0) + { + /* Input data to USPI TX FIFO */ + length -= nu_uspi_write(uspi_base, (const uint8_t *)&uspi_bus->dummy, bytes_per_word); + + /* Read data from USPI RX FIFO */ + while (USPI_GET_RX_EMPTY_FLAG(uspi_base)); + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + else + { + while (length > 0) + { + /* Input data to USPI TX FIFO */ + send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + + /* Read data from USPI RX FIFO */ + while (USPI_GET_RX_EMPTY_FLAG(uspi_base)); + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + if (recv_addr) + { + // Wait USPI transmission done + while (USPI_IS_BUSY(uspi_base)) + { + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + + while (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) + { + recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); + } + } + else + { + /* Clear USPI RX FIFO */ + nu_uspi_drain_rxfifo(uspi_base); + } +} + +static void nu_uspi_transfer(struct nu_uspi *uspi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word) +{ + RT_ASSERT(uspi_bus != RT_NULL); +#if defined(BSP_USING_USPI_PDMA) + /* PDMA transfer constrains */ + if ((uspi_bus->pdma_chanid_rx >= 0) && + !((uint32_t)tx % bytes_per_word) && + !((uint32_t)rx % bytes_per_word) && + (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD)) + nu_uspi_pdma_transmit(uspi_bus, tx, rx, length, bytes_per_word); + else + nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word); +#else + nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word); +#endif +} + +static rt_ssize_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_uspi *uspi_bus; + struct rt_spi_configuration *configuration; + uint8_t bytes_per_word; + void *pvUserData; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + uspi_bus = (struct nu_uspi *) device->bus; + configuration = (struct rt_spi_configuration *)&uspi_bus->configuration; + bytes_per_word = configuration->data_width / 8; + pvUserData = device->parent.user_data; + + if ((message->length % bytes_per_word) != 0) + { + /* Say bye. */ + LOG_E("%s: error payload length(%d%%%d != 0).\n", uspi_bus->name, message->length, bytes_per_word); + return 0; + } + + if (message->length > 0) + { + if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS)) + { + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + else + { + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + } + } + + nu_uspi_transfer(uspi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word); + + if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS)) + { + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + USPI_SET_SS_LOW(uspi_bus->uspi_base); + } + else + { + USPI_SET_SS_HIGH(uspi_bus->uspi_base); + } + } + } + + } + + return message->length; +} + +static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name) +{ + return rt_spi_bus_register(&uspi_bus->dev, name, &nu_uspi_poll_ops); +} + +/** + * Hardware USPI Initial + */ +static int rt_hw_uspi_init(void) +{ + int i; + + for (i = (USPI_START + 1); i < USPI_CNT; i++) + { + nu_uspi_register_bus(&nu_uspi_arr[i], nu_uspi_arr[i].name); +#if defined(BSP_USING_USPI_PDMA) + nu_uspi_arr[i].pdma_chanid_tx = -1; + nu_uspi_arr[i].pdma_chanid_rx = -1; + if ((nu_uspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_uspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_uspi_pdma_allocate(&nu_uspi_arr[i]) != RT_EOK) + { + LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_uspi_arr[i].name); + } + } +#endif + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_uspi_init); + +#endif //#if defined(BSP_USING_USPI) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c new file mode 100644 index 00000000000..623e2f4b38f --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c @@ -0,0 +1,639 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_UUART) + +#include "NuMicro.h" +#include "drv_pdma.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.uuart" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UUART0_TX_DMA) +#define UUART0_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI0_TX, +#else +#define UUART0_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UUART0_RX_DMA) +#define UUART0_DMA_RX_INIT .pdma_perp_rx = PDMA_USCI0_RX, \ + .rx_write_offset = 0, +#else +#define UUART0_DMA_RX_INIT .pdma_perp_rx = NU_PDMA_UNUSED, +#endif + +#if defined(BSP_USING_UUART1_TX_DMA) +#define UUART1_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI1_TX, +#else +#define UUART1_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UUART1_RX_DMA) +#define UUART1_DMA_RX_INIT .pdma_perp_rx = PDMA_USCI1_RX, \ + .rx_write_offset = 0, +#else +#define UUART1_DMA_RX_INIT .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + +#define DEFINE_NU_UUART(_idx, _rst, _irqn, _tx_init, _rx_init) \ + { \ + .name = "uuart" #_idx, \ + .uuart_base = UUART##_idx, \ + .uuart_rst = _rst, \ + .uuart_irq_n = _irqn, \ + _tx_init \ + _rx_init \ + } + +#define DEFINE_UUART_IRQ_HANDLER(_idx) \ +void USCI##_idx##_IRQHandler(void) \ +{ \ + rt_interrupt_enter(); \ + \ + nu_uuart_isr(&nu_uuart_arr[UUART##_idx##_IDX]); \ + \ + rt_interrupt_leave(); \ +} + + +/* Types / Structures ---------------------------------------------------------*/ +enum +{ + UUART_START = -1, +#if defined(BSP_USING_UUART0) + UUART0_IDX, +#endif +#if defined(BSP_USING_UUART1) + UUART1_IDX, +#endif + UUART_CNT +}; +struct nu_uuart +{ + rt_serial_t dev; + char *name; + UUART_T *uuart_base; + uint32_t uuart_rst; + IRQn_Type uuart_irq_n; +#if defined(RT_SERIAL_USING_DMA) + uint32_t dma_flag; + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + int32_t rx_write_offset; + int32_t rxdma_trigger_len; + + nu_pdma_desc_t pdma_rx_desc; +#endif +}; +typedef struct nu_uuart *nu_uuart_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_uuart_send(struct rt_serial_device *serial, char c); +static int nu_uuart_receive(struct rt_serial_device *serial); +static void nu_uuart_isr(nu_uuart_t serial); +#if defined(RT_SERIAL_USING_DMA) + static rt_ssize_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); + static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events); + static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events); +#endif + +/* Static Variables ----------------------------------------------------------*/ +static const struct rt_uart_ops nu_uuart_ops = +{ + .configure = nu_uuart_configure, + .control = nu_uuart_control, + .putc = nu_uuart_send, + .getc = nu_uuart_receive, +#if defined(RT_SERIAL_USING_DMA) + .dma_transmit = nu_uuart_dma_transmit +#else + .dma_transmit = RT_NULL +#endif +}; + +static const struct serial_configure nu_uuart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_uuart nu_uuart_arr [] = +{ +#if defined(BSP_USING_UUART0) + DEFINE_NU_UUART(0, USCI0_RST, USCI0_IRQn, +#if defined(RT_SERIAL_USING_DMA) + UUART0_DMA_TX_INIT, + UUART0_DMA_RX_INIT +#else + , +#endif + ), +#endif + +#if defined(BSP_USING_UUART1) + DEFINE_NU_UUART(1, USCI1_RST, USCI1_IRQn, +#if defined(RT_SERIAL_USING_DMA) + UUART1_DMA_TX_INIT, + UUART1_DMA_RX_INIT +#else + , +#endif + ), +#endif +}; /* uuart nu_uuart */ + +/* Functions Implementation --------------------------------------------------*/ +#if defined(BSP_USING_UUART0) +DEFINE_UUART_IRQ_HANDLER(0) +#endif + +#if defined(BSP_USING_UUART1) +DEFINE_UUART_IRQ_HANDLER(1) +#endif + +/** + * All UUART interrupt service routine + */ +static void nu_uuart_isr(nu_uuart_t serial) +{ + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Get interrupt event */ + uint32_t u32IntSts = uuart_base->PROTSTS; + uint32_t u32FIFOSts = uuart_base->BUFSTS; + + if (u32IntSts & (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk)) + { + uuart_base->PROTSTS |= (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk); + return; + } + if (u32IntSts & UUART_PROTSTS_RXENDIF_Msk) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + uuart_base->PROTSTS = u32IntSts; + uuart_base->BUFSTS = u32FIFOSts; +} + +/** + * Configure uuart port + */ +static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t uuart_word_len = 0; + uint32_t uuart_stop_bit = 0; + uint32_t uuart_parity = 0; + RT_ASSERT(serial); + RT_ASSERT(cfg); + + /* Check baud rate */ + RT_ASSERT(cfg->baud_rate); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + rt_kprintf("Unsupported data length"); + goto exit_nu_uuart_configure; + + case DATA_BITS_6: + uuart_word_len = UUART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uuart_word_len = UUART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uuart_word_len = UUART_WORD_LEN_8; + break; + + default: + rt_kprintf("Unsupported data length"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uuart_stop_bit = UUART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uuart_stop_bit = UUART_STOP_BIT_2; + break; + + default: + rt_kprintf("Unsupported stop bit\n"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + switch (cfg->parity) + { + case PARITY_NONE: + uuart_parity = UUART_PARITY_NONE; + break; + + case PARITY_ODD: + uuart_parity = UUART_PARITY_ODD; + break; + + case PARITY_EVEN: + uuart_parity = UUART_PARITY_EVEN; + break; + + default: + rt_kprintf("Unsupported parity\n"); + ret = RT_EINVAL; + goto exit_nu_uuart_configure; + } + SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst); + + /* Open UUart and set UUART baud rate */ + UUART_Open(uuart_base, cfg->baud_rate); + + /* Set line configuration. */ + UUART_SetLine_Config(uuart_base, 0, uuart_word_len, uuart_parity, uuart_stop_bit); + + /* Enable NVIC interrupt. */ + NVIC_EnableIRQ(((nu_uuart_t)serial)->uuart_irq_n); + +exit_nu_uuart_configure: + + if (ret != RT_EOK) + UUART_Close(uuart_base); + + return -(ret); +} +#if defined(RT_SERIAL_USING_DMA) +static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen) +{ + rt_err_t result = RT_EOK; + struct nu_pdma_chn_cb sChnCB; + nu_uuart_t psNuUUart = (nu_uuart_t)serial; + + /* Get base address of uart register */ + UUART_T *uuart_base = psNuUUart->uuart_base; + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uuart_rx_cb; + sChnCB.m_pvUserData = (void *)serial; + + nu_pdma_filtering_set(psNuUUart->pdma_chanid_rx, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + result = nu_pdma_callback_register(psNuUUart->pdma_chanid_rx, &sChnCB); + + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } + + if (serial->config.bufsz == 0) + { + result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_rx, + 8, + (uint32_t)&uuart_base->RXDAT, + (uint32_t)pu8Buf, + i32TriggerLen, + 1000); //Idle-timeout, 1ms + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } + } + else + { + /* For Serial RX FIFO - Single buffer recycle SG trigger */ + /* Link to next */ + nu_pdma_desc_t next = psNuUUart->pdma_rx_desc; + + result = nu_pdma_desc_setup(psNuUUart->pdma_chanid_rx, + psNuUUart->pdma_rx_desc, + 8, + (uint32_t)&uuart_base->RXDAT, + (uint32_t)pu8Buf, + i32TriggerLen, + next, + 0); + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } + result = nu_pdma_sg_transfer(psNuUUart->pdma_chanid_rx, psNuUUart->pdma_rx_desc, 1000); + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } + } + UUART_EnableInt(uuart_base, UUART_RLS_INT_MASK); + UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + +exit_nu_pdma_uuart_rx_config: + + return result; +} + +static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events) +{ + rt_size_t recv_len = 0; + rt_size_t transferred_rxbyte = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner; + nu_uuart_t puuart = (nu_uuart_t)serial; + RT_ASSERT(serial); + + /* Get base address of uuart register */ + UUART_T *uuart_base = puuart->uuart_base; + + transferred_rxbyte = nu_pdma_transferred_byte_get(puuart->pdma_chanid_rx, puuart->rxdma_trigger_len); + + if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)) + { + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + transferred_rxbyte = puuart->rxdma_trigger_len; + } + else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UUART_GET_RX_EMPTY(uuart_base)) + { + return; + } + + recv_len = transferred_rxbyte - puuart->rx_write_offset; + + puuart->rx_write_offset = transferred_rxbyte % puuart->rxdma_trigger_len; + } + + if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)) + { + recv_len = puuart->rxdma_trigger_len; + } + + if (recv_len) + { + rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static rt_err_t nu_pdma_uuart_tx_config(struct rt_serial_device *serial) +{ + struct nu_pdma_chn_cb sChnCB; + RT_ASSERT(serial); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uuart_tx_cb; + sChnCB.m_pvUserData = (void *)serial; + + nu_pdma_filtering_set(((nu_uuart_t)serial)->pdma_chanid_tx, NU_PDMA_EVENT_TRANSFER_DONE); + return nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_tx, &sChnCB); +} + +static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uuart_t puuart = (nu_uuart_t)pvOwner; + + RT_ASSERT(puuart); + + // Stop DMA TX transfer + UUART_PDMA_DISABLE(puuart->uuart_base, UUART_PDMACTL_TXPDMAEN_Msk); + + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * UUart DMA transfer + */ +static rt_ssize_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + rt_err_t result = RT_EOK; + nu_uuart_t psNuUUart = (nu_uuart_t)serial; + + RT_ASSERT(serial); + RT_ASSERT(buf); + + /* Get base address of uuart register */ + UUART_T *uuart_base = psNuUUart->uuart_base; + if (direction == RT_SERIAL_DMA_TX) + { + result = nu_pdma_transfer(psNuUUart->pdma_chanid_tx, + 8, + (uint32_t)buf, + (uint32_t)&uuart_base->TXDAT, + size, + 0); // wait-forever + // Start DMA TX transfer + UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_TXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + } + else if (direction == RT_SERIAL_DMA_RX) + { + UUART_DisableInt(uuart_base, UUART_RLS_INT_MASK); + UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + // If config.bufsz = 0, serial will trigger once. + psNuUUart->rxdma_trigger_len = size; + psNuUUart->rx_write_offset = 0; + result = nu_pdma_uuart_rx_config(serial, buf, size); + } + else + { + result = RT_ERROR; + } + + return result; +} + +static int nu_hw_uuart_dma_allocate(nu_uuart_t puuart) +{ + RT_ASSERT(puuart); + + /* Allocate UUART_TX nu_dma channel */ + if (puuart->pdma_perp_tx != NU_PDMA_UNUSED) + { + puuart->pdma_chanid_tx = nu_pdma_channel_allocate(puuart->pdma_perp_tx); + if (puuart->pdma_chanid_tx >= 0) + { + puuart->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + } + } + if (puuart->pdma_perp_rx != NU_PDMA_UNUSED) + { + puuart->pdma_chanid_rx = nu_pdma_channel_allocate(puuart->pdma_perp_rx); + if (puuart->pdma_chanid_rx >= 0) + { + rt_err_t ret = RT_EOK; + puuart->dma_flag |= RT_DEVICE_FLAG_DMA_RX; + ret = nu_pdma_sgtbls_allocate(puuart->pdma_chanid_rx, &puuart->pdma_rx_desc, 1); + RT_ASSERT(ret == RT_EOK); + } + } + + return RT_EOK; +} +#endif + +/** + * UUart interrupt control + */ +static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + nu_uuart_t psNuUUart = (nu_uuart_t)serial; + rt_err_t result = RT_EOK; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial); + + /* Get base address of uuart register */ + UUART_T *uuart_base = psNuUUart->uuart_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + UUART_DisableInt(uuart_base, UUART_RXEND_INT_MASK); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + /* Disable Receive Line interrupt & Stop DMA RX transfer. */ +#if defined(RT_SERIAL_USING_DMA) + nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx); + UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk); + UUART_DisableInt(uuart_base, UUART_RLS_INT_MASK); +#endif + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + UUART_EnableInt(uuart_base, UUART_RXEND_INT_MASK); + } + break; +#if defined(RT_SERIAL_USING_DMA) + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */ + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + psNuUUart->rxdma_trigger_len = serial->config.bufsz; + psNuUUart->rx_write_offset = 0; + result = nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], psNuUUart->rxdma_trigger_len); // Config & trigger + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */ + { + result = nu_pdma_uuart_tx_config(serial); + } + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(psNuUUart->uuart_irq_n); +#if defined(RT_SERIAL_USING_DMA) + UUART_DisableInt(uuart_base, UUART_RXEND_INT_MASK | UUART_RLS_INT_MASK); + UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_TXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); + + nu_pdma_channel_terminate(psNuUUart->pdma_chanid_tx); + nu_pdma_channel_terminate(psNuUUart->pdma_chanid_rx); +#endif + + /* Reset this module */ + SYS_ResetModule(psNuUUart->uuart_rst); + + /* Close UUART port */ + UUART_Close(uuart_base); + + break; + + default: + result = -RT_EINVAL; + break; + + } + return result; +} + +/** + * UUart put char + */ +static int nu_uuart_send(struct rt_serial_device *serial, char c) +{ + RT_ASSERT(serial); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Waiting if TX-FIFO is full. */ + while (UUART_IS_TX_FULL(uuart_base)); + + /* Put char into TX-FIFO */ + UUART_WRITE(uuart_base, c); + + return 1; +} + +/** + * UUart get char + */ +static int nu_uuart_receive(struct rt_serial_device *serial) +{ + RT_ASSERT(serial); + + /* Get base address of uuart register */ + UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; + + /* Return failure if RX-FIFO is empty. */ + if (UUART_GET_RX_EMPTY(uuart_base)) + { + return -1; + } + return UUART_READ(uuart_base); +} + +/** + * Hardware UUART Initialization + */ +static int rt_hw_uuart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (UUART_START + 1); i < UUART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_uuart_arr[i].dev.ops = &nu_uuart_ops; + nu_uuart_arr[i].dev.config = nu_uuart_default_config; +#if defined(RT_SERIAL_USING_DMA) + nu_uuart_arr[i].dma_flag = 0; + nu_hw_uuart_dma_allocate(&nu_uuart_arr[i]); + flag |= nu_uuart_arr[i].dma_flag; +#endif + + ret = rt_hw_serial_register(&nu_uuart_arr[i].dev, nu_uuart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return (int)ret; +} + +INIT_DEVICE_EXPORT(rt_hw_uuart_init); +#endif //#if defined(BSP_USING_UUART) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_wdt.c new file mode 100644 index 00000000000..b4e8130c1f7 --- /dev/null +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_wdt.c @@ -0,0 +1,421 @@ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtconfig.h" +#if defined(BSP_USING_WDT) + +#include "NuMicro.h" +#include "rtdbg.h" +#include "rtdevice.h" +#include "rthw.h" + +/* Defines / Macros ----------------------------------------------------------*/ +#undef LOG_TAG +#define LOG_TAG "drv.wdt" +#define DBG_TAG LOG_TAG +#include "drv_log.h" + + +/* Types / Structures ---------------------------------------------------------*/ +/* Static Function Prototypes ------------------------------------------------*/ +/* Static Variables ----------------------------------------------------------*/ + +/* Functions Implementation --------------------------------------------------*/ +/* watchdog timer timeout look up table */ +/* clock = LIRC 32000Hz. */ +/* */ +/* working hz toutsel exp cycles timeout (s) */ +/* 32000 0 4 16 0.0005 */ +/* 1 6 64 0.0020 */ +/* 2 8 256 0.0080 */ +/* 3 10 1024 0.0320 */ +/* 4 12 4096 0.1280 */ +/* 5 14 16384 0.5120 */ +/* 6 16 65536 2.0480 */ +/* 7 18 262144 8.1920 */ +/* 8 20 1048576 32.7680 */ +/* clock = LXT 32768Hz. */ +/* */ +/* working hz toutsel exp cycles timeout (s) */ +/* 32768 0 4 16 0.0005 */ +/* 1 6 64 0.0020 */ +/* 2 8 256 0.0078 */ +/* 3 10 1024 0.0313 */ +/* 4 12 4096 0.1250 */ +/* 5 14 16384 0.5000 */ +/* 6 16 65536 2.0000 */ +/* 7 18 262144 8.0000 */ +/* 8 20 1048576 32.000 */ +/* Pick a suitable wdt timeout interval, it is a trade-off between the + consideration of timeout accuracy and the system performance. The MIN_CYCLES + parameter is a numerical value of the toutsel setting, and it must be set to + a correct one which matches to the literal meaning of MIN_TOUTSEL. */ +#define MIN_TOUTSEL (WDT_TIMEOUT_2POW10) +#define MIN_CYCLES (1024) + +/* Macros to convert the value between the timeout interval and the soft time iterations. */ +#define ROUND_TO_INTEGER(value) ((int)(((value) * 10 + 5) / 10)) +#define CONV_SEC_TO_IT(hz, secs) (ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)(MIN_CYCLES))) +#define CONV_IT_TO_SEC(hz, iterations) (ROUND_TO_INTEGER((float)((iterations) * (MIN_CYCLES)) / (float)(hz))) + +/* Types / Structures ---------------------------------------------------------*/ +struct soft_time_handle +{ + int clock_hz; + int wanted_sec; + int report_sec; + int left_iterations; + int full_iterations; + rt_bool_t expired; + rt_bool_t feed_dog; +}; + +typedef volatile struct soft_time_handle soft_time_handle_t; + +/* Static Function Prototypes ------------------------------------------------*/ +static rt_err_t wdt_init(rt_watchdog_t *dev); +static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args); +static uint32_t wdt_get_module_clock(void); +static uint32_t wdt_get_working_hz(void); +static void soft_time_init(soft_time_handle_t *const soft_time); +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time); +static void soft_time_feed_dog(soft_time_handle_t *const soft_time); +#if defined(RT_USING_PM) + static rt_err_t wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode); + static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode); + static rt_err_t wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode); + static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time); +#endif + +/* Static Variables ----------------------------------------------------------*/ +static struct soft_time_handle soft_time; +static struct rt_watchdog_device device_wdt; +static struct rt_watchdog_ops ops_wdt = +{ + .init = wdt_init, + .control = wdt_control, +}; +#if defined(RT_USING_PM) + +static struct rt_device_pm_ops device_pm_ops = +{ + .suspend = wdt_pm_suspend, + .resume = wdt_pm_resume, + .frequency_change = wdt_pm_frequency_change +}; +#endif + +/* Functions Implementation --------------------------------------------------*/ + +#if defined(RT_USING_PM) + +/* device pm suspend() entry. */ +static rt_err_t wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + case PM_SLEEP_MODE_STANDBY: + case PM_SLEEP_MODE_SHUTDOWN: + break; + + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + WDT->CTL &= ~WDT_CTL_WDTEN_Msk; + + break; + + default: + break; + } + + return (int)RT_EOK; +} +static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + case PM_SLEEP_MODE_IDLE: + case PM_SLEEP_MODE_STANDBY: + case PM_SLEEP_MODE_SHUTDOWN: + break; + + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + WDT->CTL |= WDT_CTL_WDTEN_Msk; + break; + + default: + break; + } +} +static rt_err_t wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode) +{ + uint32_t clk, new_hz; + + new_hz = wdt_get_working_hz(); + clk = wdt_get_module_clock(); + + if (clk == CLK_CLKSEL1_WDT0SEL_HCLK_DIV2048) + { + if (new_hz == soft_time.clock_hz) + return (int)(RT_EOK); + + /* frequency change occurs in critical section */ + soft_time_freqeucy_change(new_hz, &soft_time); + } + + return (int)(RT_EOK); +} + +static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time) +{ + rt_base_t level; + soft_time_handle_t new_time; + rt_bool_t corner_case = RT_FALSE; + + level = rt_hw_interrupt_disable(); + + new_time.clock_hz = new_hz; + new_time.feed_dog = soft_time->feed_dog; + new_time.expired = soft_time->expired; + new_time.wanted_sec = soft_time->wanted_sec; + new_time.full_iterations = CONV_SEC_TO_IT(new_hz, soft_time->wanted_sec); + new_time.report_sec = CONV_IT_TO_SEC(new_hz, new_time.full_iterations); + + new_time.left_iterations = ROUND_TO_INTEGER((float)soft_time->left_iterations * + (float)new_hz / (float)soft_time->clock_hz); + + if ((new_time.left_iterations == 0) && (soft_time->left_iterations > 0)) + { + new_time.left_iterations++;; + corner_case = RT_TRUE; + } + + *soft_time = new_time; + rt_hw_interrupt_enable(level); + + if (corner_case) + { + LOG_W("pm frequency change cause wdt internal left iterations convert to 0.\n\r \ + wdt driver will add another 1 iteration for this corner case."); + } +} +#endif + +static void hw_wdt_init(void) +{ + if (WDT_GET_RESET_FLAG(WDT)) + { + LOG_W("System re-boots from watchdog timer reset.\n"); + WDT_CLEAR_RESET_FLAG(WDT); + } + + NVIC_EnableIRQ(WDT0_IRQn); +} +int rt_hw_wdt_init(void) +{ + rt_err_t ret; + + hw_wdt_init(); + + device_wdt.ops = &ops_wdt; + ret = rt_hw_watchdog_register(&device_wdt, "wdt", RT_DEVICE_FLAG_RDWR, RT_NULL); +#if defined(RT_USING_PM) + + rt_pm_device_register((struct rt_device *)&device_wdt, &device_pm_ops); +#endif + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +/* Register rt-thread device.init() entry. */ +static rt_err_t wdt_init(rt_watchdog_t *dev) +{ + soft_time_init(&soft_time); + hw_wdt_init(); + + return RT_EOK; +} + +static uint32_t wdt_get_module_clock(void) +{ + return (CLK_GetModuleClockSource(WDT0_MODULE) << CLK_CLKSEL1_WDT0SEL_Pos); +} + +static uint32_t wdt_get_working_hz(void) +{ + uint32_t clk, hz = 0; + + clk = wdt_get_module_clock(); + + switch (clk) + { + + case CLK_CLKSEL1_WDT0SEL_LIRC: + hz = __LIRC; + break; + + case CLK_CLKSEL1_WDT0SEL_LXT: + hz = __LXT; + break; + + case CLK_CLKSEL1_WDT0SEL_HCLK_DIV2048: + hz = CLK_GetHCLKFreq() / 2048; + break; + + default: + break; + } + + return hz; +} + +static void soft_time_init(soft_time_handle_t *const soft_time) +{ + rt_memset((void *)soft_time, 0, sizeof(struct soft_time_handle)); +} + +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + soft_time->expired = RT_FALSE; + soft_time->feed_dog = RT_FALSE; + soft_time->wanted_sec = wanted_sec; + soft_time->full_iterations = CONV_SEC_TO_IT(hz, wanted_sec); + soft_time->left_iterations = soft_time->full_iterations; + soft_time->report_sec = CONV_IT_TO_SEC(hz, soft_time->full_iterations); + soft_time->clock_hz = hz; + + rt_hw_interrupt_enable(level); +} + +static void soft_time_feed_dog(soft_time_handle_t *const soft_time) +{ + soft_time->feed_dog = RT_TRUE; +} +static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args) +{ + uint32_t wanted_sec, hz; + uint32_t *buf; + rt_err_t ret = RT_EOK; + + if (dev == NULL) + return -(RT_EINVAL); + + hz = wdt_get_working_hz(); + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + buf = (uint32_t *)args; + *buf = soft_time.report_sec; + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + + wanted_sec = *((uint32_t *)args); + + if (wanted_sec == 0) + { + ret = RT_EINVAL; + break; + } + + soft_time_setup(wanted_sec, hz, &soft_time); + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + buf = (uint32_t *)args; + *buf = CONV_IT_TO_SEC(hz, soft_time.left_iterations); + break; + + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + + /* Make a mark that the application has fed the watchdog. */ + soft_time_feed_dog(&soft_time); + break; + + case RT_DEVICE_CTRL_WDT_START: + + WDT_RESET_COUNTER(WDT); + WDT_Open(WDT, MIN_TOUTSEL, WDT_RESET_DELAY_1026CLK, TRUE, TRUE); + WDT_EnableInt(WDT); + break; + + case RT_DEVICE_CTRL_WDT_STOP: + + WDT_Close(WDT); + break; + + default: + ret = RT_ERROR; + } + + return -(ret); +} +void WDT0_IRQHandler(void) +{ + rt_interrupt_enter(); + + /* Clear wdt interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG(WDT)) + { + WDT_CLEAR_TIMEOUT_INT_FLAG(WDT); + } + if (WDT_GET_TIMEOUT_WAKEUP_FLAG(WDT)) + { + WDT_CLEAR_TIMEOUT_WAKEUP_FLAG(WDT); + } + + /* The soft time has not reached the configured timeout yet. Clear the wdt counter + any way to prevent the system from hardware wdt reset. */ + if (soft_time.left_iterations-- > 0) + { + WDT_RESET_COUNTER(WDT); + } + + /* The soft time reaches the configured timeout boundary. Clear the wdt + counter if he application has fed the dog at least once until now. */ + else + { + if ((soft_time.feed_dog) && (!soft_time.expired)) + { + WDT_RESET_COUNTER(WDT); + soft_time.feed_dog = RT_FALSE; + soft_time.left_iterations = soft_time.full_iterations; + } + else + { + /* Application does not feed the dog in time. */ + soft_time.expired = RT_TRUE; + } + } + + rt_interrupt_leave(); +} +#endif /* BSP_USING_WDT */ diff --git a/bsp/nuvoton/libraries/m460/rtt_port/Kconfig b/bsp/nuvoton/libraries/m460/rtt_port/Kconfig index e4a2ec8b7d0..0fc1c94907c 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m460/rtt_port/Kconfig @@ -17,14 +17,14 @@ config SOC_SERIES_M460 if BSP_USING_PDMA config NU_PDMA_MEMFUN_ACTOR_MAX - int "Specify maximum mem actor for memfun" - range 1 4 - default 2 + int "Specify maximum mem actor for memfun" + range 1 4 + default 2 config NU_PDMA_SGTBL_POOL_SIZE - int "Specify maximum scatter-gather pool size" - range 1 64 - default 32 + int "Specify maximum scatter-gather pool size" + range 1 64 + default 32 endif config BSP_USING_FMC @@ -94,135 +94,101 @@ config SOC_SERIES_M460 bool "Enable Timer Controller(TIMER)" if BSP_USING_TMR + config BSP_USING_TIMER + bool - config BSP_USING_TIMER - bool - - config BSP_USING_TPWM - bool + config BSP_USING_TPWM + bool - config BSP_USING_TIMER_CAPTURE - bool + config BSP_USING_TIMER_CAPTURE + bool config BSP_USING_TMR0 bool "Enable TIMER0" if BSP_USING_TMR0 - choice - prompt "Select TIMER0 function mode" - - config BSP_USING_TIMER0 - select BSP_USING_TIMER - select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. - - config BSP_USING_TPWM0 - select BSP_USING_TPWM - select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. - - config BSP_USING_TIMER0_CAPTURE - select BSP_USING_TIMER_CAPTURE - select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - - endchoice + config BSP_USING_TIMER0 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_CLOCK_TIME + depends on !BSP_USING_TPWM0 && !BSP_USING_TIMER0_CAPTURE + + config BSP_USING_TPWM0 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + depends on !BSP_USING_TIMER0_CAPTURE + + config BSP_USING_TIMER0_CAPTURE + bool "TIMER CAPTURE" + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE endif config BSP_USING_TMR1 bool "Enable TIMER1" if BSP_USING_TMR1 - choice - prompt "Select TIMER1 function mode" - - config BSP_USING_TIMER1 - select BSP_USING_TIMER - select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. - - config BSP_USING_TPWM1 - select BSP_USING_TPWM - select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. - - config BSP_USING_TIMER1_CAPTURE - select BSP_USING_TIMER_CAPTURE - select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice - endif + config BSP_USING_TIMER1 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_CLOCK_TIME + depends on !BSP_USING_TPWM1 && !BSP_USING_TIMER1_CAPTURE + + config BSP_USING_TPWM1 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + depends on !BSP_USING_TIMER1_CAPTURE + + config BSP_USING_TIMER1_CAPTURE + bool "TIMER CAPTURE" + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE + endif config BSP_USING_TMR2 bool "Enable TIMER2" - if BSP_USING_TMR2 - choice - prompt "Select TIMER2 function mode" - - config BSP_USING_TIMER2 - select BSP_USING_TIMER - select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. - - config BSP_USING_TPWM2 - select BSP_USING_TPWM - select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. - - config BSP_USING_TIMER2_CAPTURE - select BSP_USING_TIMER_CAPTURE - select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice + if BSP_USING_TMR2 + config BSP_USING_TIMER2 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_CLOCK_TIME + depends on !BSP_USING_TPWM2 && !BSP_USING_TIMER2_CAPTURE + + config BSP_USING_TPWM2 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + depends on !BSP_USING_TIMER2_CAPTURE + + config BSP_USING_TIMER2_CAPTURE + bool "TIMER CAPTURE" + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE endif config BSP_USING_TMR3 bool "Enable TIMER3" if BSP_USING_TMR3 - choice - prompt "Select TIMER3 function mode" - - config BSP_USING_TIMER3 - select BSP_USING_TIMER - select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. - - config BSP_USING_TPWM3 - select BSP_USING_TPWM - select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. - - config BSP_USING_TIMER3_CAPTURE - select BSP_USING_TIMER_CAPTURE - select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice + config BSP_USING_TIMER3 + bool "TIMER" + select BSP_USING_TIMER + select RT_USING_CLOCK_TIME + depends on !BSP_USING_TPWM3 && !BSP_USING_TIMER3_CAPTURE + + config BSP_USING_TPWM3 + bool "TIMER PWM" + select BSP_USING_TPWM + select RT_USING_PWM + depends on !BSP_USING_TIMER3_CAPTURE + + config BSP_USING_TIMER3_CAPTURE + bool "TIMER CAPTURE" + select BSP_USING_TIMER_CAPTURE + select RT_USING_INPUT_CAPTURE endif endif @@ -340,7 +306,6 @@ config SOC_SERIES_M460 config BSP_USING_UART9_RX_DMA bool "Enable UART9 RX DMA" depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA - endif menuconfig BSP_USING_I2C @@ -362,71 +327,60 @@ config SOC_SERIES_M460 config BSP_USING_I2C4 bool "Enable I2C4" - endif menuconfig BSP_USING_USCI bool "Enable Universal Serial Control Interface Controller(USCI)" - if BSP_USING_USCI - - config BSP_USING_UUART - bool - - config BSP_USING_USPI - bool + if BSP_USING_USCI + config BSP_USING_UUART + bool - config BSP_USING_USPI_PDMA - bool - default n + config BSP_USING_USPI + bool - config BSP_USING_UI2C - bool + config BSP_USING_USPI_PDMA + bool + default n - config BSP_USING_USCI0 - bool "Enable USCI0" + config BSP_USING_UI2C + bool - if BSP_USING_USCI0 - choice - prompt "Select USCI0 function mode" + config BSP_USING_USCI0 + bool "Enable USCI0" + if BSP_USING_USCI0 config BSP_USING_UUART0 + bool "UUART0" select RT_USING_SERIAL select BSP_USING_UUART - bool "UUART0" - help - Choose this option if you need UART function mode. config BSP_USING_UI2C0 + bool "UI2C0" select RT_USING_I2C select BSP_USING_UI2C - bool "UI2C0" - help - Choose this option if you need I2C function mode. + depends on !BSP_USING_UUART0 config BSP_USING_USPI0 + bool "USPI0" select RT_USING_SPI select BSP_USING_USPI - bool "USPI0" - help - Choose this option if you need SPI function mode. - endchoice - - config BSP_USING_UUART0_TX_DMA - bool "Enable UUART0 TX DMA" - depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA - - config BSP_USING_UUART0_RX_DMA - bool "Enable UUART0 RX DMA" - depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA - - config BSP_USING_USPI0_PDMA - bool "Use PDMA for data transferring" - select BSP_USING_USPI_PDMA - depends on BSP_USING_USPI0 - endif + depends on !BSP_USING_UUART0 && !BSP_USING_UI2C0 - endif + config BSP_USING_UUART0_TX_DMA + bool "Enable UUART0 TX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UUART0_RX_DMA + bool "Enable UUART0 RX DMA" + depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA + + config BSP_USING_USPI0_PDMA + bool "Use PDMA for data transferring" + select BSP_USING_USPI_PDMA + depends on BSP_USING_USPI0 + endif + endif menuconfig BSP_USING_SDH bool "Enable Secure Digital Host Controller(SDH)" @@ -464,440 +418,247 @@ config SOC_SERIES_M460 select RT_USING_PWM if BSP_USING_BPWM - config BSP_USING_BPWM_CAPTURE bool - choice - prompt "Select BPWM0 function mode" - config BSP_USING_BPWM0_NONE - bool "Disable BPWM0" - help - Choose this option if you need not any function mode. + config BSP_USING_BPWM0 + bool "Enable BPWM0" + select RT_USING_PWM + depends on !BSP_USING_BPWM0_CAPTURE - config BSP_USING_BPWM0 - select RT_USING_PWM - bool "Enable BPWM0" - help - Choose this option if you need PWM function mode. - - config BSP_USING_BPWM0_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_BPWM_CAPTURE - bool "Enable BPWM0_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - choice - prompt "Select BPWM1 function mode" - config BSP_USING_BPWM1_NONE - bool "Disable BPWM1" - help - Choose this option if you need not any function mode. - - config BSP_USING_BPWM1 - select RT_USING_PWM - bool "Enable BPWM1" - help - Choose this option if you need PWM function mode. + config BSP_USING_BPWM0_CAPTURE + bool "Enable BPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE - config BSP_USING_BPWM1_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_BPWM_CAPTURE - bool "Enable BPWM1_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice + config BSP_USING_BPWM1 + bool "Enable BPWM1" + select RT_USING_PWM + depends on !BSP_USING_BPWM1_CAPTURE + config BSP_USING_BPWM1_CAPTURE + bool "Enable BPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE endif menuconfig BSP_USING_EPWM bool "Enable EPWM Generator and Capture Timer(EPWM)" if BSP_USING_EPWM - config BSP_USING_EPWM_CAPTURE bool - choice - prompt "Select EPWM0 function mode" - config BSP_USING_EPWM0_NONE - bool "Disable EPWM0" - help - Choose this option if you need not any function mode. + config BSP_USING_EPWM0 + bool "Enable EPWM0" + select RT_USING_PWM + depends on !BSP_USING_EPWM0_CAPTURE - config BSP_USING_EPWM0 - select RT_USING_PWM - bool "Enable EPWM0" - help - Choose this option if you need PWM function mode. - - config BSP_USING_EPWM0_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_EPWM_CAPTURE - bool "Enable EPWM0_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - choice - prompt "Select EPWM1 function mode" - config BSP_USING_EPWM1_NONE - bool "Disable EPWM1" - help - Choose this option if you need not any function mode. - - config BSP_USING_EPWM1 - select RT_USING_PWM - bool "Enable EPWM1" - help - Choose this option if you need PWM function mode. + config BSP_USING_EPWM0_CAPTURE + bool "Enable EPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE - config BSP_USING_EPWM1_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_EPWM_CAPTURE - bool "Enable EPWM1_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice + config BSP_USING_EPWM1 + bool "Enable EPWM1" + select RT_USING_PWM + depends on !BSP_USING_EPWM1_CAPTURE + config BSP_USING_EPWM1_CAPTURE + bool "Enable EPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE endif menuconfig BSP_USING_SPI - bool "Enable Serial Peripheral Interface(SPI)" - select RT_USING_SPI + bool "Enable Serial Peripheral Interface(SPI)" + select RT_USING_SPI - if BSP_USING_SPI + if BSP_USING_SPI config BSP_USING_SPI_PDMA - bool - default n + bool + default n config BSP_USING_SPII2S - bool - default n - - choice - prompt "Select SPI0 function mode" - config BSP_USING_SPI0_NONE - bool "NONE" - help - Choose this option if you need not SPI0. + bool + default n - config BSP_USING_SPI0 + config BSP_USING_SPI0 bool "Enable SPI0" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S0 - config BSP_USING_SPII2S0 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S0" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S0 + bool "Enable SPII2S0" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI0 config BSP_USING_SPI0_PDMA bool "Enable PDMA for SPI0" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI0 endif - choice - prompt "Select SPI1 function mode" - config BSP_USING_SPI1_NONE - bool "NONE" - help - Choose this option if you need not SPI1. - - config BSP_USING_SPI1 + config BSP_USING_SPI1 bool "Enable SPI1" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S1 - config BSP_USING_SPII2S1 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S1" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S1 + bool "Enable SPII2S1" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI1 config BSP_USING_SPI1_PDMA bool "Enable PDMA for SPI1" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI1 endif - choice - prompt "Select SPI2 function mode" - config BSP_USING_SPI2_NONE - bool "NONE" - help - Choose this option if you need not SPI2. - - config BSP_USING_SPI2 + config BSP_USING_SPI2 bool "Enable SPI2" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S2 - config BSP_USING_SPII2S2 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S2" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S2 + bool "Enable SPII2S2" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI2 config BSP_USING_SPI2_PDMA bool "Enable PDMA for SPI2" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI2 endif - choice - prompt "Select SPI3 function mode" - config BSP_USING_SPI3_NONE - bool "NONE" - help - Choose this option if you need not SPI3. - - config BSP_USING_SPI3 + config BSP_USING_SPI3 bool "Enable SPI3" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S3 - config BSP_USING_SPII2S3 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S3" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S3 + bool "Enable SPII2S3" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI3 config BSP_USING_SPI3_PDMA bool "Enable PDMA for SPI3" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI3 endif - choice - prompt "Select SPI4 function mode" - config BSP_USING_SPI4_NONE - bool "NONE" - help - Choose this option if you need not SPI4. - - config BSP_USING_SPI4 + config BSP_USING_SPI4 bool "Enable SPI4" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S4 - config BSP_USING_SPII2S4 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S4" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S4 + bool "Enable SPII2S4" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI4 config BSP_USING_SPI4_PDMA bool "Enable PDMA for SPI4" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI4 endif - choice - prompt "Select SPI5 function mode" - config BSP_USING_SPI5_NONE - bool "NONE" - help - Choose this option if you need not SPI5. - - config BSP_USING_SPI5 + config BSP_USING_SPI5 bool "Enable SPI5" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S5 - config BSP_USING_SPII2S5 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S5" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S5 + bool "Enable SPII2S5" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI5 config BSP_USING_SPI5_PDMA bool "Enable PDMA for SPI5" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI5 endif - choice - prompt "Select SPI6 function mode" - config BSP_USING_SPI6_NONE - bool "NONE" - help - Choose this option if you need not SPI6. - - config BSP_USING_SPI6 + config BSP_USING_SPI6 bool "Enable SPI6" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S6 - config BSP_USING_SPII2S6 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S6" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S6 + bool "Enable SPII2S6" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI6 config BSP_USING_SPI6_PDMA bool "Enable PDMA for SPI6" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI6 endif - choice - prompt "Select SPI7 function mode" - config BSP_USING_SPI7_NONE - bool "NONE" - help - Choose this option if you need not SPI7. - - config BSP_USING_SPI7 + config BSP_USING_SPI7 bool "Enable SPI7" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S7 - config BSP_USING_SPII2S7 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S7" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S7 + bool "Enable SPII2S7" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI7 config BSP_USING_SPI7_PDMA bool "Enable PDMA for SPI7" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI7 endif - choice - prompt "Select SPI8 function mode" - config BSP_USING_SPI8_NONE - bool "NONE" - help - Choose this option if you need not SPI8. - - config BSP_USING_SPI8 + config BSP_USING_SPI8 bool "Enable SPI8" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S8 - config BSP_USING_SPII2S8 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S8" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S8 + bool "Enable SPII2S8" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI8 config BSP_USING_SPI8_PDMA bool "Enable PDMA for SPI8" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI8 endif - - choice - prompt "Select SPI9 function mode" - config BSP_USING_SPI9_NONE - bool "NONE" - help - Choose this option if you need not SPI9. - - config BSP_USING_SPI9 + config BSP_USING_SPI9 bool "Enable SPI9" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S9 - config BSP_USING_SPII2S9 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S9" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S9 + bool "Enable SPII2S9" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI9 config BSP_USING_SPI9_PDMA bool "Enable PDMA for SPI9" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI9 endif - choice - prompt "Select SPI10 function mode" - config BSP_USING_SPI10_NONE - bool "NONE" - help - Choose this option if you need not SPI10. - - config BSP_USING_SPI10 + config BSP_USING_SPI10 bool "Enable SPI10" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S10 - config BSP_USING_SPII2S10 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S10" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S10 + bool "Enable SPII2S10" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI10 config BSP_USING_SPI10_PDMA bool "Enable PDMA for SPI10" select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI10 endif - endif - menuconfig BSP_USING_I2S + config BSP_USING_I2S bool "Enable I2S Controller(I2S)" select RT_USING_AUDIO select BSP_USING_PDMA - if BSP_USING_I2S - - config BSP_USING_I2S0 - bool "Enable I2S0" - - config BSP_USING_I2S1 - bool "Enable I2S1" - - endif - - if BSP_USING_I2S || BSP_USING_SPII2S config NU_I2S_DMA_FIFO_SIZE - int "DMA Buffer size of capture and playback" - range 2048 4096 - default 2048 + int "DMA Buffer size of capture and playback" + range 2048 4096 + default 2048 endif menuconfig BSP_USING_QSPI @@ -907,18 +668,18 @@ config SOC_SERIES_M460 select BSP_USING_SPI if BSP_USING_QSPI - config BSP_USING_QSPI0 - bool "Enable QSPI0" + config BSP_USING_QSPI0 + bool "Enable QSPI0" - config BSP_USING_QSPI0_PDMA + config BSP_USING_QSPI0_PDMA bool "Enable PDMA for QSPI0" select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI0 - config BSP_USING_QSPI1 + config BSP_USING_QSPI1 bool "Enable QSPI1" - config BSP_USING_QSPI1_PDMA + config BSP_USING_QSPI1_PDMA bool "Enable PDMA for QSPI1" select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI1 @@ -927,68 +688,57 @@ config SOC_SERIES_M460 menuconfig BSP_USING_SCUART bool "Enable Smart Card Host Interface - UART(SCUART)" - if BSP_USING_SCUART - config BSP_USING_SCUART0 - bool "Enable SCUART0" + if BSP_USING_SCUART + config BSP_USING_SCUART0 + bool "Enable SCUART0" - config BSP_USING_SCUART1 - bool "Enable SCUART1" + config BSP_USING_SCUART1 + bool "Enable SCUART1" - config BSP_USING_SCUART2 - bool "Enable SCUART2" + config BSP_USING_SCUART2 + bool "Enable SCUART2" endif menuconfig BSP_USING_ECAP bool "Enable Enhanced Input Capture Timer(ECAP)" if BSP_USING_ECAP - config BSP_USING_ECAP0 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP0" - help - Choose this option if you need ECAP0. + select RT_USING_INPUT_CAPTURE config BSP_USING_ECAP1 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP1" - help - Choose this option if you need ECAP1. + select RT_USING_INPUT_CAPTURE config BSP_USING_ECAP2 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP2" - help - Choose this option if you need ECAP2. + select RT_USING_INPUT_CAPTURE config BSP_USING_ECAP3 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP3" - help - Choose this option if you need ECAP3. - + select RT_USING_INPUT_CAPTURE endif menuconfig BSP_USING_EQEI - bool "Enable Adve Quadrature Encoder Interface(EQEI)" + bool "Enable Advanced Quadrature Encoder Interface(EQEI)" if BSP_USING_EQEI config BSP_USING_EQEI0 - bool "Enable EQEI0" - select RT_USING_PULSE_ENCODER + bool "Enable EQEI0" + select RT_USING_PULSE_ENCODER config BSP_USING_EQEI1 - bool "Enable EQEI1" - select RT_USING_PULSE_ENCODER + bool "Enable EQEI1" + select RT_USING_PULSE_ENCODER config BSP_USING_EQEI2 - bool "Enable EQEI2" - select RT_USING_PULSE_ENCODER + bool "Enable EQEI2" + select RT_USING_PULSE_ENCODER config BSP_USING_EQEI3 - bool "Enable EQEI3" - select RT_USING_PULSE_ENCODER - + bool "Enable EQEI3" + select RT_USING_PULSE_ENCODER endif menuconfig BSP_USING_CRYPTO @@ -999,7 +749,6 @@ config SOC_SERIES_M460 select RT_HWCRYPTO_USING_AES_CBC select RT_HWCRYPTO_USING_AES_CFB select RT_HWCRYPTO_USING_AES_CTR - select RT_HWCRYPTO_USING_AES_CFB select RT_HWCRYPTO_USING_AES_OFB select RT_HWCRYPTO_USING_DES select RT_HWCRYPTO_USING_DES_ECB @@ -1018,8 +767,6 @@ config SOC_SERIES_M460 if BSP_USING_CRYPTO config NU_PRNG_USE_SEED bool "Use specified seed value." - help - Specify the seed value to PRNG. if NU_PRNG_USE_SEED config NU_PRNG_SEED_VALUE @@ -1029,68 +776,67 @@ config SOC_SERIES_M460 endif endif - config BSP_USING_TRNG - bool "Enable True Random Number Generator(TRNG)" - select BSP_USING_CRYPTO - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_RNG - - menuconfig BSP_USING_CRC - bool "Enable Cyclic Redundancy Check Generator(CRC)" - select BSP_USING_CRYPTO - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_CRC - select RT_HWCRYPTO_USING_CRC_07 - select RT_HWCRYPTO_USING_CRC_8005 - select RT_HWCRYPTO_USING_CRC_1021 - select RT_HWCRYPTO_USING_CRC_04C11DB7 - - if BSP_USING_CRC - config NU_CRC_USE_PDMA + config BSP_USING_TRNG + bool "Enable True Random Number Generator(TRNG)" + select BSP_USING_CRYPTO + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_RNG + + menuconfig BSP_USING_CRC + bool "Enable Cyclic Redundancy Check Generator(CRC)" + select BSP_USING_CRYPTO + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + select RT_HWCRYPTO_USING_CRC_07 + select RT_HWCRYPTO_USING_CRC_8005 + select RT_HWCRYPTO_USING_CRC_1021 + select RT_HWCRYPTO_USING_CRC_04C11DB7 + + if BSP_USING_CRC + config NU_CRC_USE_PDMA bool "Use PDMA for data transferring." select BSP_USING_PDMA default y - endif - + endif menuconfig BSP_USING_SOFT_I2C bool "Enable SOFT I2C" if BSP_USING_SOFT_I2C config BSP_USING_SOFT_I2C0 - bool "Enable SOFT I2C0" - select RT_USING_I2C - select RT_USING_I2C_BITOPS - default n + bool "Enable SOFT I2C0" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n if BSP_USING_SOFT_I2C0 config BSP_SOFT_I2C0_SCL_PIN - hex "Specify the pin index of SCL of SOFT I2C0" - range 0 0x7F - default 0x18 + hex "Specify the pin index of SCL of SOFT I2C0" + range 0 0x7F + default 0x18 config BSP_SOFT_I2C0_SDA_PIN - hex "Specify the pin index of SDA of SOFT I2C0" - range 0 0x7F - default 0x17 + hex "Specify the pin index of SDA of SOFT I2C0" + range 0 0x7F + default 0x17 endif config BSP_USING_SOFT_I2C1 - bool "Enable SOFT I2C1" - select RT_USING_I2C - select RT_USING_I2C_BITOPS - default n + bool "Enable SOFT I2C1" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n if BSP_USING_SOFT_I2C1 config BSP_SOFT_I2C1_SCL_PIN - hex "Specify the pin index of SCL of SOFT I2C1" - range 0 0x7F - default 0x0B + hex "Specify the pin index of SCL of SOFT I2C1" + range 0 0x7F + default 0x0B config BSP_SOFT_I2C1_SDA_PIN - hex "Specify the pin index of SDA of SOFT I2C1" - range 0 0x7F - default 0x0A + hex "Specify the pin index of SDA of SOFT I2C1" + range 0 0x7F + default 0x0A endif endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig index 87a82cf98b5..481dcedb31e 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig @@ -17,14 +17,14 @@ config SOC_SERIES_M480 if BSP_USING_PDMA config NU_PDMA_MEMFUN_ACTOR_MAX - int "Specify maximum mem actor for memfun" - range 1 4 - default 4 + int "Specify maximum mem actor for memfun" + range 1 4 + default 4 config NU_PDMA_SGTBL_POOL_SIZE - int "Specify maximum scatter-gather pool size" - range 1 32 - default 16 + int "Specify maximum scatter-gather pool size" + range 1 32 + default 16 endif config BSP_USING_FMC @@ -48,8 +48,8 @@ config SOC_SERIES_M480 if BSP_USING_CLK config NU_CLK_INVOKE_WKTMR - bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)" - default y + bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)" + default y endif menuconfig BSP_USING_EMAC @@ -96,138 +96,104 @@ config SOC_SERIES_M480 menuconfig BSP_USING_TMR bool "Enable Timer Controller(TIMER)" - config BSP_USING_TIMER - bool - - config BSP_USING_TPWM - bool + if BSP_USING_TMR + config BSP_USING_TIMER + bool - config BSP_USING_TIMER_CAPTURE - bool + config BSP_USING_TPWM + bool - config BSP_USING_TMR0 - bool "Enable TIMER0" - depends on BSP_USING_TMR + config BSP_USING_TIMER_CAPTURE + bool - if BSP_USING_TMR0 - choice - prompt "Select TIMER0 function mode" + config BSP_USING_TMR0 + bool "Enable TIMER0" + if BSP_USING_TMR0 config BSP_USING_TIMER0 + bool "TIMER" select BSP_USING_TIMER select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. + depends on !BSP_USING_TPWM0 && !BSP_USING_TIMER0_CAPTURE config BSP_USING_TPWM0 + bool "TIMER PWM" select BSP_USING_TPWM select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. + depends on !BSP_USING_TIMER0_CAPTURE config BSP_USING_TIMER0_CAPTURE + bool "TIMER CAPTURE" select BSP_USING_TIMER_CAPTURE select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - - endchoice - endif - - config BSP_USING_TMR1 - bool "Enable TIMER1" - depends on BSP_USING_TMR + endif - if BSP_USING_TMR1 - choice - prompt "Select TIMER1 function mode" + config BSP_USING_TMR1 + bool "Enable TIMER1" + if BSP_USING_TMR1 config BSP_USING_TIMER1 + bool "TIMER" select BSP_USING_TIMER select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. + depends on !BSP_USING_TPWM1 && !BSP_USING_TIMER1_CAPTURE config BSP_USING_TPWM1 + bool "TIMER PWM" select BSP_USING_TPWM select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. + depends on !BSP_USING_TIMER1_CAPTURE config BSP_USING_TIMER1_CAPTURE + bool "TIMER CAPTURE" select BSP_USING_TIMER_CAPTURE select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice - endif - - config BSP_USING_TMR2 - bool "Enable TIMER2" - depends on BSP_USING_TMR + endif - if BSP_USING_TMR2 - choice - prompt "Select TIMER2 function mode" + config BSP_USING_TMR2 + bool "Enable TIMER2" + if BSP_USING_TMR2 config BSP_USING_TIMER2 + bool "TIMER" select BSP_USING_TIMER select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. + depends on !BSP_USING_TPWM2 && !BSP_USING_TIMER2_CAPTURE config BSP_USING_TPWM2 + bool "TIMER PWM" select BSP_USING_TPWM select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. + depends on !BSP_USING_TIMER2_CAPTURE config BSP_USING_TIMER2_CAPTURE + bool "TIMER CAPTURE" select BSP_USING_TIMER_CAPTURE select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice - endif - - config BSP_USING_TMR3 - bool "Enable TIMER3" - depends on BSP_USING_TMR && !BSP_USING_CLK + endif - if BSP_USING_TMR3 - choice - prompt "Select TIMER3 function mode" + config BSP_USING_TMR3 + bool "Enable TIMER3" + depends on !BSP_USING_CLK + if BSP_USING_TMR3 config BSP_USING_TIMER3 + bool "TIMER" select BSP_USING_TIMER select RT_USING_CLOCK_TIME - bool "TIMER" - help - Choose this option if you need TIMER function mode. + depends on !BSP_USING_TPWM3 && !BSP_USING_TIMER3_CAPTURE config BSP_USING_TPWM3 + bool "TIMER PWM" select BSP_USING_TPWM select RT_USING_PWM - bool "TIMER PWM" - help - Choose this option if you need PWM function mode. + depends on !BSP_USING_TIMER3_CAPTURE config BSP_USING_TIMER3_CAPTURE + bool "TIMER CAPTURE" select BSP_USING_TIMER_CAPTURE select RT_USING_INPUT_CAPTURE - bool "TIMER CAPTURE" - help - Choose this option if you need CAPTURE function mode. - endchoice + endif endif menuconfig BSP_USING_UART @@ -343,7 +309,6 @@ config SOC_SERIES_M480 bool "Enable Universal Serial Control Interface Controller(USCI)" if BSP_USING_USCI - config BSP_USING_UUART bool @@ -361,30 +326,22 @@ config SOC_SERIES_M480 bool "Enable USCI0" if BSP_USING_USCI0 - choice - prompt "Select USCI0 function mode" - - config BSP_USING_UUART0 - select RT_USING_SERIAL - select BSP_USING_UUART - bool "UUART0" - help - Choose this option if you need UART function mode. - - config BSP_USING_UI2C0 - select RT_USING_I2C - select BSP_USING_UI2C - bool "UI2C0" - help - Choose this option if you need I2C function mode. - - config BSP_USING_USPI0 - select RT_USING_SPI - select BSP_USING_USPI - bool "USPI0" - help - Choose this option if you need SPI function mode. - endchoice + config BSP_USING_UUART0 + bool "UUART0" + select RT_USING_SERIAL + select BSP_USING_UUART + + config BSP_USING_UI2C0 + bool "UI2C0" + select RT_USING_I2C + select BSP_USING_UI2C + depends on !BSP_USING_UUART0 + + config BSP_USING_USPI0 + bool "USPI0" + select RT_USING_SPI + select BSP_USING_USPI + depends on !BSP_USING_UUART0 && !BSP_USING_UI2C0 config BSP_USING_UUART0_TX_DMA bool "Enable UUART0 TX DMA" @@ -404,30 +361,22 @@ config SOC_SERIES_M480 bool "Enable USCI1" if BSP_USING_USCI1 - choice - prompt "Select USCI1 function mode" - - config BSP_USING_UUART1 - select RT_USING_SERIAL - select BSP_USING_UUART - bool "UUART1" - help - Choose this option if you need UART function mode. - - config BSP_USING_UI2C1 - select RT_USING_I2C - select BSP_USING_UI2C - bool "UI2C1" - help - Choose this option if you need I2C function mode. - - config BSP_USING_USPI1 - select RT_USING_SPI - select BSP_USING_USPI - bool "USPI1" - help - Choose this option if you need SPI function mode. - endchoice + config BSP_USING_UUART1 + bool "UUART1" + select RT_USING_SERIAL + select BSP_USING_UUART + + config BSP_USING_UI2C1 + bool "UI2C1" + select RT_USING_I2C + select BSP_USING_UI2C + depends on !BSP_USING_UUART1 + + config BSP_USING_USPI1 + bool "USPI1" + select RT_USING_SPI + select BSP_USING_USPI + depends on !BSP_USING_UUART1 && !BSP_USING_UI2C1 config BSP_USING_UUART1_TX_DMA bool "Enable UUART1 TX DMA" @@ -442,7 +391,6 @@ config SOC_SERIES_M480 select BSP_USING_USPI_PDMA depends on BSP_USING_USPI1 endif - endif menuconfig BSP_USING_SDH @@ -475,235 +423,130 @@ config SOC_SERIES_M480 select RT_USING_PWM if BSP_USING_BPWM - config BSP_USING_BPWM_CAPTURE bool - choice - prompt "Select BPWM0 function mode" - config BSP_USING_BPWM0 - select RT_USING_PWM - bool "Enable BPWM0" - help - Choose this option if you need PWM function mode. - - config BSP_USING_BPWM0_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_BPWM_CAPTURE - bool "Enable BPWM0_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - if BSP_USING_BPWM0_CAPTURE - config BSP_USING_BPWM0_CAPTURE_CHMSK - hex "Specify channel mask for BPWM0_CAP channel." - range 0 0x3F - default 0 - endif + config BSP_USING_BPWM0 + bool "Enable BPWM0" + select RT_USING_PWM + depends on !BSP_USING_BPWM0_CAPTURE - choice - prompt "Select BPWM1 function mode" - config BSP_USING_BPWM1 - select RT_USING_PWM - bool "Enable BPWM1" - help - Choose this option if you need PWM function mode. + config BSP_USING_BPWM0_CAPTURE + bool "Enable BPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE - config BSP_USING_BPWM1_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_BPWM_CAPTURE - bool "Enable BPWM1_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - if BSP_USING_BPWM1_CAPTURE - config BSP_USING_BPWM1_CAPTURE_CHMSK - hex "Specify channel mask for BPWM1_CAP channel." - range 0 0x3F - default 0 - endif + config BSP_USING_BPWM1 + bool "Enable BPWM1" + select RT_USING_PWM + depends on !BSP_USING_BPWM1_CAPTURE + config BSP_USING_BPWM1_CAPTURE + bool "Enable BPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_BPWM_CAPTURE endif menuconfig BSP_USING_EPWM bool "Enable EPWM Generator and Capture Timer(EPWM)" if BSP_USING_EPWM - config BSP_USING_EPWM_CAPTURE bool - choice - prompt "Select EPWM0 function mode" - config BSP_USING_EPWM0 - select RT_USING_PWM - bool "Enable EPWM0" - help - Choose this option if you need PWM function mode. + config BSP_USING_EPWM0 + bool "Enable EPWM0" + select RT_USING_PWM + depends on !BSP_USING_EPWM0_CAPTURE - config BSP_USING_EPWM0_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_EPWM_CAPTURE - bool "Enable EPWM0_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - if BSP_USING_EPWM0_CAPTURE - config BSP_USING_EPWM0_CAPTURE_CHMSK - hex "Specify channel mask for EPWM0_CAP channel." - range 0 0x3F - default 0 - endif - - choice - prompt "Select EPWM1 function mode" - config BSP_USING_EPWM1 - select RT_USING_PWM - bool "Enable EPWM1" - help - Choose this option if you need PWM function mode. + config BSP_USING_EPWM0_CAPTURE + bool "Enable EPWM0_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE - config BSP_USING_EPWM1_CAPTURE - select RT_USING_INPUT_CAPTURE - select BSP_USING_EPWM_CAPTURE - bool "Enable EPWM1_CAPTURE" - help - Choose this option if you need PWM capture function mode. - endchoice - - if BSP_USING_EPWM1_CAPTURE - config BSP_USING_EPWM1_CAPTURE_CHMSK - hex "Specify channel mask for EPWM1_CAP channel." - range 0 0x3F - default 0 - endif + config BSP_USING_EPWM1 + bool "Enable EPWM1" + select RT_USING_PWM + depends on !BSP_USING_EPWM1_CAPTURE + config BSP_USING_EPWM1_CAPTURE + bool "Enable EPWM1_CAPTURE" + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE endif menuconfig BSP_USING_SPI - bool "Enable Serial Peripheral Interface(SPI)" - select RT_USING_SPI + bool "Enable Serial Peripheral Interface(SPI)" + select RT_USING_SPI - if BSP_USING_SPI + if BSP_USING_SPI config BSP_USING_SPI_PDMA - bool - default n + bool + default n config BSP_USING_SPII2S - bool - default n - - choice - prompt "Select SPI0 function mode" - config BSP_USING_SPI0_NONE - bool "NONE" - help - Choose this option if you need not SPI0. + bool + default n - config BSP_USING_SPI0 + config BSP_USING_SPI0 bool "Enable SPI0" - help - Choose this option if you need SPI function mode. + depends on !BSP_USING_SPII2S0 - config BSP_USING_SPII2S0 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S0" - help - Choose this option if you need SPII2S function mode. - endchoice + config BSP_USING_SPII2S0 + bool "Enable SPII2S0" + select RT_USING_AUDIO + select BSP_USING_SPII2S if BSP_USING_SPI0 - config BSP_USING_SPI0_PDMA - bool "Enable PDMA for SPI0" - select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI0 + config BSP_USING_SPI0_PDMA + bool "Enable PDMA for SPI0" + select BSP_USING_SPI_PDMA endif - choice - prompt "Select SPI1 function mode" - config BSP_USING_SPI1_NONE - bool "NONE" - help - Choose this option if you need not SPI1. - - config BSP_USING_SPI1 + config BSP_USING_SPI1 bool "Enable SPI1" - help - Choose this option if you need SPI function mode. - - config BSP_USING_SPII2S1 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S1" - help - Choose this option if you need SPII2S function mode. - endchoice - - if BSP_USING_SPI1 - config BSP_USING_SPI1_PDMA - bool "Enable PDMA for SPI1" - select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI1 - endif - - choice - prompt "Select SPI2 function mode" - config BSP_USING_SPI2_NONE - bool "NONE" - help - Choose this option if you need not SPI2. - - config BSP_USING_SPI2 + depends on !BSP_USING_SPII2S1 + + config BSP_USING_SPII2S1 + bool "Enable SPII2S1" + select RT_USING_AUDIO + select BSP_USING_SPII2S + + if BSP_USING_SPI1 + config BSP_USING_SPI1_PDMA + bool "Enable PDMA for SPI1" + select BSP_USING_SPI_PDMA + endif + + config BSP_USING_SPI2 bool "Enable SPI2" - help - Choose this option if you need SPI function mode. - - config BSP_USING_SPII2S2 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S2" - help - Choose this option if you need SPII2S function mode. - endchoice - - if BSP_USING_SPI2 - config BSP_USING_SPI2_PDMA - bool "Enable PDMA for SPI2" - select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI2 - endif - - choice - prompt "Select SPI3 function mode" - config BSP_USING_SPI3_NONE - bool "NONE" - help - Choose this option if you need not SPI3. - - config BSP_USING_SPI3 + depends on !BSP_USING_SPII2S2 + + config BSP_USING_SPII2S2 + bool "Enable SPII2S2" + select RT_USING_AUDIO + select BSP_USING_SPII2S + + if BSP_USING_SPI2 + config BSP_USING_SPI2_PDMA + bool "Enable PDMA for SPI2" + select BSP_USING_SPI_PDMA + endif + + config BSP_USING_SPI3 bool "Enable SPI3" - help - Choose this option if you need SPI function mode. - - config BSP_USING_SPII2S3 - select RT_USING_AUDIO - select BSP_USING_SPII2S - bool "Enable SPII2S3" - help - Choose this option if you need SPII2S function mode. - endchoice - - if BSP_USING_SPI3 - config BSP_USING_SPI3_PDMA - bool "Enable PDMA for SPI3" - select BSP_USING_SPI_PDMA - depends on BSP_USING_SPI3 - endif + depends on !BSP_USING_SPII2S3 + + config BSP_USING_SPII2S3 + bool "Enable SPII2S3" + select RT_USING_AUDIO + select BSP_USING_SPII2S + if BSP_USING_SPI3 + config BSP_USING_SPI3_PDMA + bool "Enable PDMA for SPI3" + select BSP_USING_SPI_PDMA + endif endif config BSP_USING_I2S @@ -712,9 +555,9 @@ config SOC_SERIES_M480 if BSP_USING_I2S || BSP_USING_SPII2S config NU_I2S_DMA_FIFO_SIZE - int "DMA Buffer size of capture and playback" - range 2048 4096 - default 2048 + int "DMA Buffer size of capture and playback" + range 2048 4096 + default 2048 endif menuconfig BSP_USING_QSPI @@ -724,18 +567,18 @@ config SOC_SERIES_M480 select BSP_USING_SPI if BSP_USING_QSPI - config BSP_USING_QSPI0 - bool "Enable QSPI0" + config BSP_USING_QSPI0 + bool "Enable QSPI0" - config BSP_USING_QSPI0_PDMA + config BSP_USING_QSPI0_PDMA bool "Enable PDMA for QSPI0" select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI0 - config BSP_USING_QSPI1 + config BSP_USING_QSPI1 bool "Enable QSPI1" - config BSP_USING_QSPI1_PDMA + config BSP_USING_QSPI1_PDMA bool "Enable PDMA for QSPI1" select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI1 @@ -744,164 +587,41 @@ config SOC_SERIES_M480 menuconfig BSP_USING_SCUART bool "Enable Smart Card Host Interface - UART(SCUART)" - if BSP_USING_SCUART - config BSP_USING_SCUART0 - bool "Enable SCUART0" + if BSP_USING_SCUART + config BSP_USING_SCUART0 + bool "Enable SCUART0" - config BSP_USING_SCUART1 - bool "Enable SCUART1" + config BSP_USING_SCUART1 + bool "Enable SCUART1" - config BSP_USING_SCUART2 - bool "Enable SCUART2" + config BSP_USING_SCUART2 + bool "Enable SCUART2" endif menuconfig BSP_USING_ECAP bool "Enable Enhanced Input Capture Timer(ECAP)" - if BSP_USING_ECAP - + if BSP_USING_ECAP config BSP_USING_ECAP0 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP0" - help - Choose this option if you need ECAP0. - - if BSP_USING_ECAP0 - config BSP_USING_ECAP0_CHMSK - hex "Specify channel mask for ECAP0 channel." - range 0 0x7 - default 0 - endif + select RT_USING_INPUT_CAPTURE config BSP_USING_ECAP1 - select RT_USING_INPUT_CAPTURE bool "Enable ECAP1" - help - Choose this option if you need ECAP1. - - if BSP_USING_ECAP1 - config BSP_USING_ECAP1_CHMSK - hex "Specify channel mask for ECAP1 channel." - range 0 0x7 - default 0 - endif - - endif + select RT_USING_INPUT_CAPTURE + endif menuconfig BSP_USING_QEI bool "Enable Quadrature Encoder Interface(QEI)" if BSP_USING_QEI config BSP_USING_QEI0 - bool "Enable QEI0" - select RT_USING_PULSE_ENCODER + bool "Enable QEI0" + select RT_USING_PULSE_ENCODER config BSP_USING_QEI1 - bool "Enable QEI1" - select RT_USING_PULSE_ENCODER - endif - - menuconfig BSP_USING_CRYPTO - bool "Enable Cryptographic Accelerator(CRYPTO)" - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_AES - select RT_HWCRYPTO_USING_AES_ECB - select RT_HWCRYPTO_USING_AES_CBC - select RT_HWCRYPTO_USING_AES_CFB - select RT_HWCRYPTO_USING_AES_CTR - select RT_HWCRYPTO_USING_AES_CFB - select RT_HWCRYPTO_USING_AES_OFB - select RT_HWCRYPTO_USING_DES - select RT_HWCRYPTO_USING_DES_ECB - select RT_HWCRYPTO_USING_DES_CBC - select RT_HWCRYPTO_USING_3DES - select RT_HWCRYPTO_USING_3DES_ECB - select RT_HWCRYPTO_USING_3DES_CBC - select RT_HWCRYPTO_USING_SHA1 - select RT_HWCRYPTO_USING_SHA2 - select RT_HWCRYPTO_USING_SHA2_224 - select RT_HWCRYPTO_USING_SHA2_256 - select RT_HWCRYPTO_USING_SHA2_384 - select RT_HWCRYPTO_USING_SHA2_512 - select RT_HWCRYPTO_USING_RNG - - if BSP_USING_CRYPTO - config NU_PRNG_USE_SEED - bool "Use specified seed value." - help - Specify the seed value to PRNG. - - if NU_PRNG_USE_SEED - config NU_PRNG_SEED_VALUE - hex "Enter seed value" - range 0 0xFFFFFFFF - default 0 - endif - endif - - config BSP_USING_TRNG - bool "Enable True Random Number Generator(TRNG)" - select BSP_USING_CRYPTO - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_RNG - - menuconfig BSP_USING_CRC - bool "Enable Cyclic Redundancy Check Generator(CRC)" - select BSP_USING_CRYPTO - select RT_USING_HWCRYPTO - select RT_HWCRYPTO_USING_CRC - select RT_HWCRYPTO_USING_CRC_07 - select RT_HWCRYPTO_USING_CRC_8005 - select RT_HWCRYPTO_USING_CRC_1021 - select RT_HWCRYPTO_USING_CRC_04C11DB7 - - if BSP_USING_CRC - config NU_CRC_USE_PDMA - bool "Use PDMA for data transferring." - select BSP_USING_PDMA - default y - endif - - - menuconfig BSP_USING_SOFT_I2C - bool "Enable SOFT I2C" - - if BSP_USING_SOFT_I2C - config BSP_USING_SOFT_I2C0 - bool "Enable SOFT I2C0" - select RT_USING_I2C - select RT_USING_I2C_BITOPS - default n - - if BSP_USING_SOFT_I2C0 - config BSP_SOFT_I2C0_SCL_PIN - hex "Specify the pin index of SCL of SOFT I2C0" - range 0 0x7F - default 0x18 - - config BSP_SOFT_I2C0_SDA_PIN - hex "Specify the pin index of SDA of SOFT I2C0" - range 0 0x7F - default 0x17 - endif - - config BSP_USING_SOFT_I2C1 - bool "Enable SOFT I2C1" - select RT_USING_I2C - select RT_USING_I2C_BITOPS - default n - - if BSP_USING_SOFT_I2C1 - config BSP_SOFT_I2C1_SCL_PIN - hex "Specify the pin index of SCL of SOFT I2C1" - range 0 0x7F - default 0x0B - - config BSP_SOFT_I2C1_SDA_PIN - hex "Specify the pin index of SDA of SOFT I2C1" - range 0 0x7F - default 0x0A - endif + bool "Enable QEI1" + select RT_USING_PULSE_ENCODER endif config BSP_USING_WDT diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig index a05652a923e..1f8df1448ae 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig @@ -4,7 +4,7 @@ config SOC_SERIES_N9H30 select SOC_FAMILY_NUMICRO select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - select PKG_USING_NUVOTON_ARM926_LIB + select PKG_USING_NUVOTON_SERIES_DRIVER default y config BSP_USE_STDDRIVER_SOURCE diff --git a/bsp/nuvoton/libraries/nu_packages/Kconfig b/bsp/nuvoton/libraries/nu_packages/Kconfig index 2f4f387d91a..16dc56c057d 100644 --- a/bsp/nuvoton/libraries/nu_packages/Kconfig +++ b/bsp/nuvoton/libraries/nu_packages/Kconfig @@ -50,21 +50,18 @@ menu "Nuvoton Packages Config" if NU_PKG_USING_ILI9341 - choice - prompt "Select ili9341 interface" - - config NU_PKG_USING_ILI9341_SPI - select BSP_USING_SPI - bool "ILI9341_SPI" - help - Choose this option if you the ili9341 device is with SPI interface. - - config NU_PKG_USING_ILI9341_EBI - select BSP_USING_EBI - bool "ILI9341_EBI" - help - Choose this option if you the ili9341 device is with EBI interface. - endchoice + config NU_PKG_USING_ILI9341_SPI + select BSP_USING_SPI + bool "ILI9341_SPI" + help + Choose this option if you the ili9341 device is with SPI interface. + + config NU_PKG_USING_ILI9341_EBI + select BSP_USING_EBI + depends on !NU_PKG_USING_ILI9341_SPI + bool "ILI9341_EBI" + help + Choose this option if you the ili9341 device is with EBI interface. if NU_PKG_USING_ILI9341_SPI config NU_PKG_USING_ILI9341_SPI_CLK_FREQ @@ -110,15 +107,11 @@ menu "Nuvoton Packages Config" if NU_PKG_USING_SSD1963 - choice - prompt "Select SSD1963 interface" - - config NU_PKG_USING_SSD1963_EBI - select BSP_USING_EBI - bool "SSD1963_EBI" - help - Choose this option if you the SSD1963 device is with EBI interface. - endchoice + config NU_PKG_USING_SSD1963_EBI + select BSP_USING_EBI + bool "SSD1963_EBI" + help + Choose this option if you the SSD1963 device is with EBI interface. config NU_PKG_SSD1963_WITH_OFFSCREEN_FRAMEBUFFER bool "Create an offscreen framebuffer." @@ -152,15 +145,11 @@ menu "Nuvoton Packages Config" if NU_PKG_USING_FSA506 - choice - prompt "Select FSA506 interface" - - config NU_PKG_USING_FSA506_EBI - select BSP_USING_EBI - bool "FSA506_EBI" - help - Choose this option if you the FSA506 device is with EBI interface. - endchoice + config NU_PKG_USING_FSA506_EBI + select BSP_USING_EBI + bool "FSA506_EBI" + help + Choose this option if you the FSA506 device is with EBI interface. config NU_PKG_FSA506_WITH_OFFSCREEN_FRAMEBUFFER bool "Create an offscreen framebuffer." diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig index c4945642852..af7e441fced 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig @@ -4,7 +4,7 @@ config SOC_SERIES_NUC980 select SOC_FAMILY_NUMICRO select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - select PKG_USING_NUVOTON_ARM926_LIB + select PKG_USING_NUVOTON_SERIES_DRIVER default y config BSP_USE_STDDRIVER_SOURCE diff --git a/bsp/nuvoton/ma35-rtp/.config b/bsp/nuvoton/ma35-rtp/.config index b8cd18e9657..30f9ba760ea 100644 --- a/bsp/nuvoton/ma35-rtp/.config +++ b/bsp/nuvoton/ma35-rtp/.config @@ -107,7 +107,7 @@ CONFIG_USE_MA35D1_SUBM=y # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/ma35-rtp/rtconfig.h b/bsp/nuvoton/ma35-rtp/rtconfig.h index 71855cca48f..93955ae8004 100644 --- a/bsp/nuvoton/ma35-rtp/rtconfig.h +++ b/bsp/nuvoton/ma35-rtp/rtconfig.h @@ -63,7 +63,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/nk-980iot/.config b/bsp/nuvoton/nk-980iot/.config index ad12fea1c1c..fdaa7eadc51 100644 --- a/bsp/nuvoton/nk-980iot/.config +++ b/bsp/nuvoton/nk-980iot/.config @@ -180,7 +180,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -257,6 +258,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # end of elm-chan's FatFs, Generic FAT Filesystem Module CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_9PFS is not set # CONFIG_RT_USING_DFS_ISO9660 is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set @@ -292,8 +294,7 @@ CONFIG_RT_CANSND_BOX_NUM=1 CONFIG_RT_CANSND_MSG_TIMEOUT=100 CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 # CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set -CONFIG_RT_USING_CPUTIME=y -CONFIG_CPUTIME_TIMER_FREQ=0 +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y @@ -322,6 +323,8 @@ CONFIG_RT_ALARM_PRIORITY=10 # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_SPI_MSD is not set @@ -362,10 +365,10 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y # CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -541,11 +544,10 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Memory management # +# CONFIG_RT_PAGE_MPR_SIZE_DYNAMIC is not set CONFIG_RT_PAGE_AFFINITY_BLOCK_SIZE=0x1000 CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMBLOCK is not set @@ -590,6 +592,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -791,6 +794,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -816,6 +820,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -864,6 +871,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -958,6 +968,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -1103,8 +1116,14 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-cmsis" +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-series" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_VER="latest" CONFIG_PKG_USING_NUVOTON_ARM926_LIB=y CONFIG_PKG_NUVOTON_ARM926_LIB_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-arm926-lib" CONFIG_PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION=y @@ -1116,7 +1135,24 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -1162,9 +1198,11 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1193,6 +1231,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_P3T1755 is not set # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set # end of sensors drivers # @@ -1210,6 +1249,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1289,6 +1329,13 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1715,8 +1762,8 @@ CONFIG_BSP_USING_CRYPTO=y # CONFIG_BSP_USING_SOFT_I2C is not set CONFIG_BSP_USING_WDT=y # CONFIG_BSP_USING_EBI is not set -CONFIG_BSP_USING_USBD=y -CONFIG_BSP_USING_USBH=y +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set # end of On-chip Peripheral Drivers # @@ -1728,8 +1775,8 @@ CONFIG_BOARD_USING_NAU8822=y CONFIG_BOARD_USING_STORAGE_SDCARD=y # CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set CONFIG_BOARD_USING_STORAGE_SPINAND=y -CONFIG_BOARD_USING_USB0_DEVICE_HOST=y -CONFIG_BOARD_USING_USB1_HOST=y +# CONFIG_BOARD_USING_USB0_DEVICE_HOST is not set +# CONFIG_BOARD_USING_USB1_HOST is not set # end of On-board Peripheral Drivers # @@ -1744,7 +1791,7 @@ CONFIG_BOARD_USING_USB1_HOST=y # Nuvoton Packages Config # CONFIG_NU_PKG_USING_UTILS=y -CONFIG_NU_PKG_USING_DEMO=y +# CONFIG_NU_PKG_USING_DEMO is not set # CONFIG_NU_PKG_USING_BMX055 is not set # CONFIG_NU_PKG_USING_MAX31875 is not set # CONFIG_NU_PKG_USING_NCT7717U is not set diff --git a/bsp/nuvoton/nk-980iot/SConstruct b/bsp/nuvoton/nk-980iot/SConstruct index c86751ba07e..f1fd6e42b39 100644 --- a/bsp/nuvoton/nk-980iot/SConstruct +++ b/bsp/nuvoton/nk-980iot/SConstruct @@ -19,7 +19,7 @@ def bsp_pkg_check(): import subprocess check_paths = [ - os.path.join("packages", "nuvoton-arm926-lib-latest"), + os.path.join("packages", "nuvoton-series-latest"), ] need_update = not all(os.path.exists(p) for p in check_paths) diff --git a/bsp/nuvoton/nk-980iot/config_lvgl b/bsp/nuvoton/nk-980iot/config_lvgl deleted file mode 100644 index 87d581b3217..00000000000 --- a/bsp/nuvoton/nk-980iot/config_lvgl +++ /dev/null @@ -1,1317 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=16 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=2048 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -CONFIG_RT_USING_SIGNALS=y - -# -# Memory Management -# -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_MEMHEAP_FAST_MODE=y -# CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_MEMTRACE=y -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50000 -CONFIG_RT_USING_CACHE=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_MM_MMU=y -CONFIG_ARCH_ARM=y -CONFIG_ARCH_ARM_MMU=y -CONFIG_ARCH_ARM_ARM9=y - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=20 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=16 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=16 -CONFIG_DFS_FD_MAX=64 -CONFIG_RT_USING_DFS_MNTTABLE=y -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=8 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_NFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=2048 -CONFIG_RT_USING_CAN=y -CONFIG_RT_CAN_USING_HDR=y -# CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_CLOCK_TIME=y -CONFIG_CLOCK_TIMER_FREQ=0 -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -CONFIG_RT_USING_MTD_NAND=y -CONFIG_RT_MTD_NAND_DEBUG=y -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -CONFIG_RT_USING_RTC=y -CONFIG_RT_USING_ALARM=y -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -CONFIG_RT_USING_QSPI=y -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y -CONFIG_RT_USING_AUDIO=y -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 -CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 -# CONFIG_RT_USING_SENSOR is not set -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set -# CONFIG_RT_USING_LCD is not set -CONFIG_RT_USING_HWCRYPTO=y -CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" -CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 -CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 -# CONFIG_RT_HWCRYPTO_USING_GCM is not set -CONFIG_RT_HWCRYPTO_USING_AES=y -CONFIG_RT_HWCRYPTO_USING_AES_ECB=y -CONFIG_RT_HWCRYPTO_USING_AES_CBC=y -CONFIG_RT_HWCRYPTO_USING_AES_CFB=y -CONFIG_RT_HWCRYPTO_USING_AES_CTR=y -CONFIG_RT_HWCRYPTO_USING_AES_OFB=y -# CONFIG_RT_HWCRYPTO_USING_DES is not set -# CONFIG_RT_HWCRYPTO_USING_3DES is not set -# CONFIG_RT_HWCRYPTO_USING_RC4 is not set -# CONFIG_RT_HWCRYPTO_USING_MD5 is not set -CONFIG_RT_HWCRYPTO_USING_SHA1=y -CONFIG_RT_HWCRYPTO_USING_SHA2=y -CONFIG_RT_HWCRYPTO_USING_SHA2_224=y -CONFIG_RT_HWCRYPTO_USING_SHA2_256=y -CONFIG_RT_HWCRYPTO_USING_SHA2_384=y -CONFIG_RT_HWCRYPTO_USING_SHA2_512=y -CONFIG_RT_HWCRYPTO_USING_RNG=y -# CONFIG_RT_HWCRYPTO_USING_CRC is not set -# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set - -# -# Using USB -# -CONFIG_RT_USING_USB=y -CONFIG_RT_USING_USB_HOST=y -CONFIG_RT_USBH_MSTORAGE=y -CONFIG_UDISK_MOUNTPOINT="/mnt/udisk" -# CONFIG_RT_USBH_HID is not set -CONFIG_RT_USING_USB_DEVICE=y -CONFIG_RT_USBD_THREAD_STACK_SZ=4096 -CONFIG_USB_VENDOR_ID=0x0FFE -CONFIG_USB_PRODUCT_ID=0x0001 -CONFIG_RT_USB_DEVICE_COMPOSITE=y -CONFIG_RT_USB_DEVICE_CDC=y -CONFIG_RT_USB_DEVICE_NONE=y -CONFIG_RT_USB_DEVICE_MSTORAGE=y -# CONFIG_RT_USB_DEVICE_HID is not set -# CONFIG_RT_USB_DEVICE_RNDIS is not set -# CONFIG_RT_USB_DEVICE_ECM is not set -# CONFIG_RT_USB_DEVICE_WINUSB is not set -# CONFIG_RT_USB_DEVICE_AUDIO is not set -CONFIG_RT_VCOM_TASK_STK_SIZE=2048 -CONFIG_RT_CDC_RX_BUFSIZE=128 -# CONFIG_RT_VCOM_TX_USE_DMA is not set -CONFIG_RT_VCOM_SERNO="32021919830108" -CONFIG_RT_VCOM_SER_LEN=14 -CONFIG_RT_VCOM_TX_TIMEOUT=1000 -CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -# CONFIG_RT_USING_POSIX_DEVIO is not set -# CONFIG_RT_USING_POSIX_STDIO is not set -CONFIG_RT_USING_POSIX_POLL=y -CONFIG_RT_USING_POSIX_SELECT=y -CONFIG_RT_USING_POSIX_SOCKET=y -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -CONFIG_RT_USING_SAL=y -# CONFIG_SAL_INTERNET_CHECK is not set - -# -# Docking with protocol stacks -# -CONFIG_SAL_USING_LWIP=y -# CONFIG_SAL_USING_AT is not set -# CONFIG_SAL_USING_TLS is not set -CONFIG_SAL_USING_POSIX=y -CONFIG_RT_USING_NETDEV=y -CONFIG_NETDEV_USING_IFCONFIG=y -CONFIG_NETDEV_USING_PING=y -CONFIG_NETDEV_USING_NETSTAT=y -CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set -CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 -# CONFIG_NETDEV_IPV6_SCOPES is not set -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set -# CONFIG_RT_USING_LWIP141 is not set -# CONFIG_RT_USING_LWIP203 is not set -CONFIG_RT_USING_LWIP212=y -# CONFIG_RT_USING_LWIP_LATEST is not set -CONFIG_RT_USING_LWIP_VER_NUM=0x20102 -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_MEM_ALIGNMENT=4 -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.31.55" -CONFIG_RT_LWIP_GWADDR="192.168.31.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -CONFIG_RT_LWIP_RAW=y -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=16 -CONFIG_RT_LWIP_PBUF_NUM=256 -CONFIG_RT_LWIP_RAW_PCB_NUM=16 -CONFIG_RT_LWIP_UDP_PCB_NUM=16 -CONFIG_RT_LWIP_TCP_PCB_NUM=16 -CONFIG_RT_LWIP_TCP_SEG_NUM=64 -CONFIG_RT_LWIP_TCP_SND_BUF=16384 -CONFIG_RT_LWIP_TCP_WND=65535 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=21 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=256 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096 -# CONFIG_LWIP_NO_RX_THREAD is not set -CONFIG_LWIP_NO_TX_THREAD=y -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=22 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=4096 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=256 -CONFIG_RT_LWIP_REASSEMBLY_FRAG=y -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_LWIP_NETIF_LINK_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -CONFIG_LWIP_SO_LINGER=1 -CONFIG_RT_LWIP_NETIF_LOOPBACK=y -CONFIG_LWIP_NETIF_LOOPBACK=1 -CONFIG_RT_LWIP_STATS=y -# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set -CONFIG_RT_LWIP_USING_PING=y -# CONFIG_LWIP_USING_DHCPD is not set -# CONFIG_RT_LWIP_DEBUG is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_USING_LVGL_SQUARELINE is not set -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -CONFIG_PKG_LVGL_USING_V08034=y -# CONFIG_PKG_LVGL_USING_V08033 is not set -# CONFIG_PKG_LVGL_USING_V08032 is not set -# CONFIG_PKG_LVGL_USING_V08031 is not set -# CONFIG_PKG_LVGL_USING_V08030 is not set -# CONFIG_PKG_LVGL_USING_V08020 is not set -# CONFIG_PKG_LVGL_USING_V8_3_LATEST_VERSION is not set -# CONFIG_PKG_LVGL_USING_LATEST_VERSION is not set -CONFIG_PKG_LVGL_VER_NUM=0x08034 -CONFIG_PKG_LVGL_VER="v8.3.4" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -CONFIG_PKG_USING_WAVPLAYER=y -CONFIG_PKG_WAVPLAYER_PATH="/packages/multimedia/wavplayer" -CONFIG_PKG_WP_USING_PLAY=y -CONFIG_PKG_WP_PLAY_DEVICE="sound0" -CONFIG_PKG_WP_USING_RECORD=y -CONFIG_PKG_WP_RECORD_DEVICE="sound0" -# CONFIG_PKG_USING_WAVPLAYER_V020 is not set -CONFIG_PKG_USING_WAVPLAYER_LATEST_VERSION=y -CONFIG_PKG_WAVPLAYER_VER="latest" -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -CONFIG_PKG_USING_RAMDISK=y -CONFIG_PKG_RAMDISK_PATH="/packages/system/ramdisk" -# CONFIG_PKG_USING_RAMDISK_V010 is not set -CONFIG_PKG_USING_RAMDISK_LATEST_VERSION=y -CONFIG_PKG_RAMDISK_VER="latest" -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_FINGERPRINT is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_UKAL is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -CONFIG_PKG_USING_OPTPARSE=y -CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse" -CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION=y -CONFIG_PKG_OPTPARSE_VER="latest" -# CONFIG_OPTPARSE_USING_DEMO is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set -# CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects -# -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set - -# -# Other -# - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_NUC980=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_MMU=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_EMAC=y -CONFIG_BSP_USING_EMAC0=y -# CONFIG_BSP_USING_EMAC1 is not set -# CONFIG_NU_EMAC_PDMA_MEMCOPY is not set -CONFIG_BSP_USING_RTC=y -CONFIG_NU_RTC_SUPPORT_IO_RW=y -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y -CONFIG_BSP_USING_ADC=y -CONFIG_BSP_USING_ADC_TOUCH=y -CONFIG_BSP_USING_TMR=y -CONFIG_BSP_USING_TIMER=y -CONFIG_BSP_USING_TMR0=y -CONFIG_BSP_USING_TIMER0=y -# CONFIG_BSP_USING_TIMER0_CAPTURE is not set -CONFIG_BSP_USING_TMR1=y -CONFIG_BSP_USING_TIMER1=y -# CONFIG_BSP_USING_TIMER1_CAPTURE is not set -CONFIG_BSP_USING_TMR2=y -CONFIG_BSP_USING_TIMER2=y -# CONFIG_BSP_USING_TIMER2_CAPTURE is not set -CONFIG_BSP_USING_TMR3=y -CONFIG_BSP_USING_TIMER3=y -# CONFIG_BSP_USING_TIMER3_CAPTURE is not set -CONFIG_BSP_USING_TMR4=y -CONFIG_BSP_USING_TIMER4=y -# CONFIG_BSP_USING_TIMER4_CAPTURE is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -CONFIG_BSP_USING_UART1=y -CONFIG_BSP_USING_UART1_TX_DMA=y -CONFIG_BSP_USING_UART1_RX_DMA=y -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_UART6 is not set -# CONFIG_BSP_USING_UART7 is not set -# CONFIG_BSP_USING_UART8 is not set -# CONFIG_BSP_USING_UART9 is not set -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C0=y -# CONFIG_BSP_USING_I2C1 is not set -CONFIG_BSP_USING_I2C2=y -# CONFIG_BSP_USING_I2C3 is not set -CONFIG_BSP_USING_SDH=y -# CONFIG_BSP_USING_SDH0 is not set -CONFIG_BSP_USING_SDH1=y -CONFIG_NU_SDH_USING_PDMA=y -CONFIG_NU_SDH_HOTPLUG=y -# CONFIG_NU_SDH_MOUNT_ON_ROOT is not set -# CONFIG_BSP_USING_CAN is not set -CONFIG_BSP_USING_PWM=y -CONFIG_BSP_USING_PWM0=y -# CONFIG_BSP_USING_PWM1 is not set -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI_PDMA=y -# CONFIG_BSP_USING_SPI0_NONE is not set -CONFIG_BSP_USING_SPI0=y -CONFIG_BSP_USING_SPI0_PDMA=y -CONFIG_BSP_USING_SPI1_NONE=y -# CONFIG_BSP_USING_SPI1 is not set -CONFIG_BSP_USING_I2S=y -CONFIG_NU_I2S_DMA_FIFO_SIZE=4096 -CONFIG_BSP_USING_QSPI=y -CONFIG_BSP_USING_QSPI_PDMA=y -CONFIG_BSP_USING_QSPI0=y -CONFIG_BSP_USING_QSPI0_PDMA=y -# CONFIG_BSP_USING_SCUART is not set -CONFIG_BSP_USING_CRYPTO=y -# CONFIG_NU_PRNG_USE_SEED is not set -# CONFIG_BSP_USING_SOFT_I2C is not set -CONFIG_BSP_USING_WDT=y -# CONFIG_BSP_USING_EBI is not set -CONFIG_BSP_USING_USBD=y -CONFIG_BSP_USING_USBH=y - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_CONSOLE=y -CONFIG_BOARD_USING_IP101GR=y -CONFIG_BOARD_USING_NAU8822=y -CONFIG_BOARD_USING_STORAGE_SDCARD=y -# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set -CONFIG_BOARD_USING_STORAGE_SPINAND=y -CONFIG_BOARD_USING_USB0_DEVICE_HOST=y -CONFIG_BOARD_USING_USB1_HOST=y - -# -# Board extended module drivers -# -# CONFIG_BOARD_USING_MAX31875 is not set -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=103 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=90 -CONFIG_BOARD_USING_ILI9341_PIN_DC=89 -# CONFIG_BOARD_USING_ESP8266 is not set - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -CONFIG_NU_PKG_USING_DEMO=y -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -# CONFIG_NU_PKG_USING_NCT7717U is not set -# CONFIG_NU_PKG_USING_NAU88L25 is not set -CONFIG_NU_PKG_USING_NAU8822=y -# CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -CONFIG_NU_PKG_USING_ILI9341_SPI=y -# CONFIG_NU_PKG_USING_ILI9341_EBI is not set -CONFIG_NU_PKG_USING_ILI9341_SPI_CLK_FREQ=48000000 -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=240 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 -# CONFIG_NU_PKG_USING_SSD1963 is not set -# CONFIG_NU_PKG_USING_FSA506 is not set -# CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -# CONFIG_NU_PKG_USING_ADC_TOUCH_SW is not set -CONFIG_NU_PKG_USING_SPINAND=y diff --git a/bsp/nuvoton/nk-980iot/rtconfig.h b/bsp/nuvoton/nk-980iot/rtconfig.h index 6a36636aeae..2a6d1a81314 100644 --- a/bsp/nuvoton/nk-980iot/rtconfig.h +++ b/bsp/nuvoton/nk-980iot/rtconfig.h @@ -106,7 +106,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -182,8 +183,7 @@ #define RT_CANSND_BOX_NUM 1 #define RT_CANSND_MSG_TIMEOUT 100 #define RT_CAN_NB_TX_FIFO_SIZE 256 -#define RT_USING_CPUTIME -#define CPUTIME_TIMER_FREQ 0 +#define RT_USING_CLOCK_TIME #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_ADC @@ -196,6 +196,7 @@ #define RT_ALARM_TIMESLICE 5 #define RT_ALARM_PRIORITY 10 #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_QSPI #define RT_USING_WDT #define RT_USING_AUDIO @@ -220,7 +221,6 @@ #define RT_HWCRYPTO_USING_SHA2_512 #define RT_HWCRYPTO_USING_RNG #define RT_USING_PIN -#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -489,6 +489,10 @@ /* NUVOTON Drivers */ +#define PKG_USING_NUVOTON_CMSIS_DRIVER +#define PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NUVOTON_SERIES_DRIVER +#define PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION #define PKG_USING_NUVOTON_ARM926_LIB #define PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION /* end of NUVOTON Drivers */ @@ -496,6 +500,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -631,8 +643,6 @@ #define BSP_USING_QSPI0_PDMA #define BSP_USING_CRYPTO #define BSP_USING_WDT -#define BSP_USING_USBD -#define BSP_USING_USBH /* end of On-chip Peripheral Drivers */ /* On-board Peripheral Drivers */ @@ -642,8 +652,6 @@ #define BOARD_USING_NAU8822 #define BOARD_USING_STORAGE_SDCARD #define BOARD_USING_STORAGE_SPINAND -#define BOARD_USING_USB0_DEVICE_HOST -#define BOARD_USING_USB1_HOST /* end of On-board Peripheral Drivers */ /* Board extended module drivers */ @@ -653,7 +661,6 @@ /* Nuvoton Packages Config */ #define NU_PKG_USING_UTILS -#define NU_PKG_USING_DEMO #define NU_PKG_USING_NAU8822 #define NU_PKG_USING_SPINAND /* end of Nuvoton Packages Config */ diff --git a/bsp/nuvoton/nk-n9h30/.config b/bsp/nuvoton/nk-n9h30/.config index ab7adb268d7..4a897b83e5b 100644 --- a/bsp/nuvoton/nk-n9h30/.config +++ b/bsp/nuvoton/nk-n9h30/.config @@ -180,7 +180,8 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -257,6 +258,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # end of elm-chan's FatFs, Generic FAT Filesystem Module CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_9PFS is not set # CONFIG_RT_USING_DFS_ISO9660 is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set @@ -271,6 +273,8 @@ CONFIG_FAL_USING_DEBUG=y CONFIG_FAL_PART_HAS_TABLE_CFG=y CONFIG_FAL_USING_SFUD_PORT=y CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0" +CONFIG_FAL_DEV_NAME_MAX=24 +CONFIG_FAL_DEV_BLK_MAX=6 # # Device Drivers @@ -296,7 +300,7 @@ CONFIG_RT_CANSND_BOX_NUM=1 CONFIG_RT_CANSND_MSG_TIMEOUT=100 CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 # CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y @@ -326,6 +330,8 @@ CONFIG_RT_ALARM_PRIORITY=10 # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_SPI_MSD is not set @@ -349,10 +355,10 @@ CONFIG_RT_USING_TOUCH=y # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -528,11 +534,10 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Memory management # +# CONFIG_RT_PAGE_MPR_SIZE_DYNAMIC is not set CONFIG_RT_PAGE_AFFINITY_BLOCK_SIZE=0x1000 CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMBLOCK is not set @@ -577,6 +582,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -778,6 +784,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -803,6 +810,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -851,6 +861,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -945,6 +958,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -1090,12 +1106,15 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -CONFIG_PKG_USING_NUVOTON_ARM926_LIB=y -CONFIG_PKG_NUVOTON_ARM926_LIB_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-arm926-lib" -CONFIG_PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION=y -CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-cmsis" +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-series" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_VER="latest" +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -1103,7 +1122,24 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -1149,9 +1185,11 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1180,6 +1218,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_P3T1755 is not set # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set # end of sensors drivers # @@ -1197,6 +1236,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1276,6 +1316,13 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1705,8 +1752,8 @@ CONFIG_BSP_LCD_BPP=32 CONFIG_BSP_LCD_WIDTH=800 CONFIG_BSP_LCD_HEIGHT=480 CONFIG_BSP_USING_VPOST_OSD=y -CONFIG_BSP_USING_USBD=y -CONFIG_BSP_USING_USBH=y +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set # end of On-chip Peripheral Drivers # @@ -1718,8 +1765,8 @@ CONFIG_BOARD_USING_NAU8822=y CONFIG_BOARD_USING_STORAGE_SDCARD=y CONFIG_BOARD_USING_STORAGE_SPIFLASH=y CONFIG_BOARD_USING_BUZZER=y -CONFIG_BOARD_USING_USB0_DEVICE_HOST=y -CONFIG_BOARD_USING_USB1_HOST=y +# CONFIG_BOARD_USING_USB0_DEVICE_HOST is not set +# CONFIG_BOARD_USING_USB1_HOST is not set # end of On-board Peripheral Drivers # diff --git a/bsp/nuvoton/nk-n9h30/SConstruct b/bsp/nuvoton/nk-n9h30/SConstruct index e38eff8c9ec..f03cdc822ee 100644 --- a/bsp/nuvoton/nk-n9h30/SConstruct +++ b/bsp/nuvoton/nk-n9h30/SConstruct @@ -19,7 +19,7 @@ def bsp_pkg_check(): import subprocess check_paths = [ - os.path.join("packages", "nuvoton-arm926-lib-latest"), + os.path.join("packages", "nuvoton-series-latest"), ] need_update = not all(os.path.exists(p) for p in check_paths) diff --git a/bsp/nuvoton/nk-n9h30/rtconfig.h b/bsp/nuvoton/nk-n9h30/rtconfig.h index aaa88c8fea1..4828bd04f8c 100644 --- a/bsp/nuvoton/nk-n9h30/rtconfig.h +++ b/bsp/nuvoton/nk-n9h30/rtconfig.h @@ -107,7 +107,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -170,6 +171,8 @@ #define FAL_PART_HAS_TABLE_CFG #define FAL_USING_SFUD_PORT #define FAL_USING_NOR_FLASH_DEV_NAME "norflash0" +#define FAL_DEV_NAME_MAX 24 +#define FAL_DEV_BLK_MAX 6 /* Device Drivers */ @@ -186,6 +189,7 @@ #define RT_CANSND_BOX_NUM 1 #define RT_CANSND_MSG_TIMEOUT 100 #define RT_CAN_NB_TX_FIFO_SIZE 256 +#define RT_USING_CLOCK_TIME #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_ADC @@ -199,6 +203,7 @@ #define RT_ALARM_TIMESLICE 5 #define RT_ALARM_PRIORITY 10 #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_QSPI #define RT_USING_SFUD #define RT_SFUD_USING_SFDP @@ -212,7 +217,6 @@ #define RT_AUDIO_RECORD_PIPE_SIZE 2048 #define RT_USING_TOUCH #define RT_USING_PIN -#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -480,13 +484,23 @@ /* NUVOTON Drivers */ -#define PKG_USING_NUVOTON_ARM926_LIB -#define PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION +#define PKG_USING_NUVOTON_CMSIS_DRIVER +#define PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NUVOTON_SERIES_DRIVER +#define PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION /* end of NUVOTON Drivers */ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -623,8 +637,6 @@ #define BSP_LCD_WIDTH 800 #define BSP_LCD_HEIGHT 480 #define BSP_USING_VPOST_OSD -#define BSP_USING_USBD -#define BSP_USING_USBH /* end of On-chip Peripheral Drivers */ /* On-board Peripheral Drivers */ @@ -635,8 +647,6 @@ #define BOARD_USING_STORAGE_SDCARD #define BOARD_USING_STORAGE_SPIFLASH #define BOARD_USING_BUZZER -#define BOARD_USING_USB0_DEVICE_HOST -#define BOARD_USING_USB1_HOST /* end of On-board Peripheral Drivers */ /* Board extended module drivers */ diff --git a/bsp/nuvoton/nk-rtu980/.config b/bsp/nuvoton/nk-rtu980/.config index d2417bf8a9e..68e0d96faaa 100644 --- a/bsp/nuvoton/nk-rtu980/.config +++ b/bsp/nuvoton/nk-rtu980/.config @@ -180,7 +180,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -257,6 +258,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # end of elm-chan's FatFs, Generic FAT Filesystem Module CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_9PFS is not set # CONFIG_RT_USING_DFS_ISO9660 is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set @@ -271,6 +273,8 @@ CONFIG_FAL_USING_DEBUG=y CONFIG_FAL_PART_HAS_TABLE_CFG=y CONFIG_FAL_USING_SFUD_PORT=y CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0" +CONFIG_FAL_DEV_NAME_MAX=24 +CONFIG_FAL_DEV_BLK_MAX=6 # # Device Drivers @@ -296,8 +300,7 @@ CONFIG_RT_CANSND_BOX_NUM=1 CONFIG_RT_CANSND_MSG_TIMEOUT=100 CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 # CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set -CONFIG_RT_USING_CPUTIME=y -CONFIG_CPUTIME_TIMER_FREQ=0 +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y @@ -321,6 +324,8 @@ CONFIG_RT_USING_RTC=y CONFIG_RT_USING_SOFT_RTC=y # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_SPI_MSD is not set @@ -363,10 +368,10 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y # CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -542,11 +547,10 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Memory management # +# CONFIG_RT_PAGE_MPR_SIZE_DYNAMIC is not set CONFIG_RT_PAGE_AFFINITY_BLOCK_SIZE=0x1000 CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMBLOCK is not set @@ -591,6 +595,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -792,6 +797,7 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -817,6 +823,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -865,6 +874,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -959,6 +971,9 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -1104,8 +1119,14 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-cmsis" +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-series" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_VER="latest" CONFIG_PKG_USING_NUVOTON_ARM926_LIB=y CONFIG_PKG_NUVOTON_ARM926_LIB_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-arm926-lib" CONFIG_PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION=y @@ -1117,7 +1138,24 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -1163,9 +1201,11 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1194,6 +1234,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_P3T1755 is not set # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set # end of sensors drivers # @@ -1211,6 +1252,7 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1290,6 +1332,13 @@ CONFIG_PKG_NUVOTON_ARM926_LIB_VER="latest" # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1713,8 +1762,8 @@ CONFIG_BSP_USING_CRYPTO=y # CONFIG_BSP_USING_SOFT_I2C is not set CONFIG_BSP_USING_WDT=y # CONFIG_BSP_USING_EBI is not set -CONFIG_BSP_USING_USBD=y -CONFIG_BSP_USING_USBH=y +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set # end of On-chip Peripheral Drivers # @@ -1723,7 +1772,7 @@ CONFIG_BSP_USING_USBH=y CONFIG_BSP_USING_CONSOLE=y CONFIG_BOARD_USING_UART8_RS485=y CONFIG_BOARD_USING_STORAGE_SPIFLASH=y -CONFIG_BOARD_USING_USB0_DEVICE_HOST=y +# CONFIG_BOARD_USING_USB0_DEVICE_HOST is not set # end of On-board Peripheral Drivers # diff --git a/bsp/nuvoton/nk-rtu980/SConstruct b/bsp/nuvoton/nk-rtu980/SConstruct index d78faf48c36..09d6207621a 100644 --- a/bsp/nuvoton/nk-rtu980/SConstruct +++ b/bsp/nuvoton/nk-rtu980/SConstruct @@ -19,7 +19,7 @@ def bsp_pkg_check(): import subprocess check_paths = [ - os.path.join("packages", "nuvoton-arm926-lib-latest"), + os.path.join("packages", "nuvoton-series-latest"), ] need_update = not all(os.path.exists(p) for p in check_paths) diff --git a/bsp/nuvoton/nk-rtu980/rtconfig.h b/bsp/nuvoton/nk-rtu980/rtconfig.h index d05937f2780..c2134267db7 100644 --- a/bsp/nuvoton/nk-rtu980/rtconfig.h +++ b/bsp/nuvoton/nk-rtu980/rtconfig.h @@ -106,7 +106,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -169,6 +170,8 @@ #define FAL_PART_HAS_TABLE_CFG #define FAL_USING_SFUD_PORT #define FAL_USING_NOR_FLASH_DEV_NAME "norflash0" +#define FAL_DEV_NAME_MAX 24 +#define FAL_DEV_BLK_MAX 6 /* Device Drivers */ @@ -187,14 +190,14 @@ #define RT_CANSND_BOX_NUM 1 #define RT_CANSND_MSG_TIMEOUT 100 #define RT_CAN_NB_TX_FIFO_SIZE 256 -#define RT_USING_CPUTIME -#define CPUTIME_TIMER_FREQ 0 +#define RT_USING_CLOCK_TIME #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_ADC #define RT_USING_RTC #define RT_USING_SOFT_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_QSPI #define RT_USING_SFUD #define RT_SFUD_USING_SFDP @@ -220,7 +223,6 @@ #define RT_HWCRYPTO_USING_SHA2_512 #define RT_HWCRYPTO_USING_RNG #define RT_USING_PIN -#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -489,6 +491,10 @@ /* NUVOTON Drivers */ +#define PKG_USING_NUVOTON_CMSIS_DRIVER +#define PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NUVOTON_SERIES_DRIVER +#define PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION #define PKG_USING_NUVOTON_ARM926_LIB #define PKG_USING_NUVOTON_ARM926_LIB_LATEST_VERSION /* end of NUVOTON Drivers */ @@ -496,6 +502,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -626,8 +640,6 @@ #define BSP_USING_QSPI0_PDMA #define BSP_USING_CRYPTO #define BSP_USING_WDT -#define BSP_USING_USBD -#define BSP_USING_USBH /* end of On-chip Peripheral Drivers */ /* On-board Peripheral Drivers */ @@ -635,7 +647,6 @@ #define BSP_USING_CONSOLE #define BOARD_USING_UART8_RS485 #define BOARD_USING_STORAGE_SPIFLASH -#define BOARD_USING_USB0_DEVICE_HOST /* end of On-board Peripheral Drivers */ /* Board extended module drivers */ diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/.config b/bsp/nuvoton/numaker-hmi-ma35d1/.config index 63d16f1091d..b1312866fe9 100644 --- a/bsp/nuvoton/numaker-hmi-ma35d1/.config +++ b/bsp/nuvoton/numaker-hmi-ma35d1/.config @@ -107,7 +107,7 @@ CONFIG_USE_MA35D1_AARCH32=y # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.h b/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.h index 57c76d8eb31..32feb6b359d 100644 --- a/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.h +++ b/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.h @@ -63,7 +63,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-iot-m467/.config b/bsp/nuvoton/numaker-iot-m467/.config index 343fbc20221..b395f78b35d 100644 --- a/bsp/nuvoton/numaker-iot-m467/.config +++ b/bsp/nuvoton/numaker-iot-m467/.config @@ -116,7 +116,7 @@ CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-iot-m467/config_lvgl b/bsp/nuvoton/numaker-iot-m467/config_lvgl deleted file mode 100644 index dbe4cda107a..00000000000 --- a/bsp/nuvoton/numaker-iot-m467/config_lvgl +++ /dev/null @@ -1,1204 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=12 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -CONFIG_RT_USING_SIGNALS=y - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50000 -CONFIG_ARCH_ARM=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -CONFIG_RT_USING_LEGACY=y -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=8 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 -CONFIG_DFS_FD_MAX=32 -CONFIG_RT_USING_DFS_MNTTABLE=y -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=8 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_NFS is not set -CONFIG_RT_USING_FAL=y -CONFIG_FAL_DEBUG_CONFIG=y -CONFIG_FAL_DEBUG=1 -CONFIG_FAL_PART_HAS_TABLE_CFG=y -CONFIG_FAL_USING_SFUD_PORT=y -CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0" -# CONFIG_RT_USING_LWP is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=512 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -# CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_CLOCK_TIME=y -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -CONFIG_RT_USING_SDIO=y -CONFIG_RT_SDIO_STACK_SIZE=2048 -CONFIG_RT_SDIO_THREAD_PRIORITY=15 -CONFIG_RT_MMCSD_STACK_SIZE=2048 -CONFIG_RT_MMCSD_THREAD_PRIORITY=22 -CONFIG_RT_MMCSD_MAX_PARTITION=16 -CONFIG_RT_SDIO_DEBUG=y -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -CONFIG_RT_USING_QSPI=y -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -CONFIG_RT_SFUD_USING_SFDP=y -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -CONFIG_RT_SFUD_USING_QSPI=y -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y -CONFIG_RT_USING_AUDIO=y -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 -CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 -CONFIG_RT_USING_SENSOR=y -CONFIG_RT_USING_SENSOR_CMD=y -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set -CONFIG_RT_USING_HWCRYPTO=y -CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" -CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 -CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 -# CONFIG_RT_HWCRYPTO_USING_GCM is not set -CONFIG_RT_HWCRYPTO_USING_AES=y -CONFIG_RT_HWCRYPTO_USING_AES_ECB=y -CONFIG_RT_HWCRYPTO_USING_AES_CBC=y -CONFIG_RT_HWCRYPTO_USING_AES_CFB=y -CONFIG_RT_HWCRYPTO_USING_AES_CTR=y -CONFIG_RT_HWCRYPTO_USING_AES_OFB=y -CONFIG_RT_HWCRYPTO_USING_DES=y -CONFIG_RT_HWCRYPTO_USING_DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_DES_CBC=y -CONFIG_RT_HWCRYPTO_USING_3DES=y -CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y -# CONFIG_RT_HWCRYPTO_USING_RC4 is not set -# CONFIG_RT_HWCRYPTO_USING_MD5 is not set -CONFIG_RT_HWCRYPTO_USING_SHA1=y -CONFIG_RT_HWCRYPTO_USING_SHA2=y -CONFIG_RT_HWCRYPTO_USING_SHA2_224=y -CONFIG_RT_HWCRYPTO_USING_SHA2_256=y -CONFIG_RT_HWCRYPTO_USING_SHA2_384=y -CONFIG_RT_HWCRYPTO_USING_SHA2_512=y -CONFIG_RT_HWCRYPTO_USING_RNG=y -CONFIG_RT_HWCRYPTO_USING_CRC=y -CONFIG_RT_HWCRYPTO_USING_CRC_07=y -CONFIG_RT_HWCRYPTO_USING_CRC_8005=y -CONFIG_RT_HWCRYPTO_USING_CRC_1021=y -# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set -CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y -# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -CONFIG_RT_USING_INPUT_CAPTURE=y -CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100 -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -CONFIG_RT_USING_USB=y -CONFIG_RT_USING_USB_HOST=y -CONFIG_RT_USBH_MSTORAGE=y -CONFIG_UDISK_MOUNTPOINT="/mnt/udisk" -# CONFIG_RT_USBH_HID is not set -CONFIG_RT_USING_USB_DEVICE=y -CONFIG_RT_USBD_THREAD_STACK_SZ=4096 -CONFIG_USB_VENDOR_ID=0x0FFE -CONFIG_USB_PRODUCT_ID=0x0001 -# CONFIG_RT_USB_DEVICE_COMPOSITE is not set -# CONFIG__RT_USB_DEVICE_NONE is not set -# CONFIG__RT_USB_DEVICE_CDC is not set -CONFIG__RT_USB_DEVICE_MSTORAGE=y -# CONFIG__RT_USB_DEVICE_HID is not set -# CONFIG__RT_USB_DEVICE_RNDIS is not set -# CONFIG__RT_USB_DEVICE_ECM is not set -# CONFIG__RT_USB_DEVICE_WINUSB is not set -# CONFIG__RT_USB_DEVICE_AUDIO is not set -CONFIG_RT_USB_DEVICE_MSTORAGE=y -CONFIG_RT_USB_MSTORAGE_DISK_NAME="sd0" - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -# CONFIG_RT_USING_POSIX_STDIO is not set -CONFIG_RT_USING_POSIX_POLL=y -CONFIG_RT_USING_POSIX_SELECT=y -CONFIG_RT_USING_POSIX_SOCKET=y -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -CONFIG_RT_USING_SAL=y -CONFIG_SAL_INTERNET_CHECK=y - -# -# Docking with protocol stacks -# -CONFIG_SAL_USING_LWIP=y -CONFIG_SAL_USING_AT=y -# CONFIG_SAL_USING_TLS is not set -CONFIG_SAL_USING_POSIX=y -CONFIG_RT_USING_NETDEV=y -CONFIG_NETDEV_USING_IFCONFIG=y -CONFIG_NETDEV_USING_PING=y -CONFIG_NETDEV_USING_NETSTAT=y -CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set -CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 -# CONFIG_NETDEV_IPV6_SCOPES is not set -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set -# CONFIG_RT_USING_LWIP141 is not set -# CONFIG_RT_USING_LWIP203 is not set -CONFIG_RT_USING_LWIP212=y -# CONFIG_RT_USING_LWIP_LATEST is not set -CONFIG_RT_USING_LWIP_VER_NUM=0x20102 -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_MEM_ALIGNMENT=4 -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.31.55" -CONFIG_RT_LWIP_GWADDR="192.168.31.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -CONFIG_RT_LWIP_RAW=y -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=32 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=32 -CONFIG_RT_LWIP_TCP_SND_BUF=4096 -CONFIG_RT_LWIP_TCP_WND=10240 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=2048 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32 -CONFIG_RT_LWIP_REASSEMBLY_FRAG=y -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_LWIP_NETIF_LINK_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -CONFIG_LWIP_SO_LINGER=0 -CONFIG_RT_LWIP_NETIF_LOOPBACK=y -CONFIG_LWIP_NETIF_LOOPBACK=1 -CONFIG_RT_LWIP_STATS=y -# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set -CONFIG_RT_LWIP_USING_PING=y -# CONFIG_LWIP_USING_DHCPD is not set -# CONFIG_RT_LWIP_DEBUG is not set -CONFIG_RT_USING_AT=y -# CONFIG_AT_DEBUG is not set -# CONFIG_AT_USING_SERVER is not set -CONFIG_AT_USING_CLIENT=y -CONFIG_AT_CLIENT_NUM_MAX=1 -CONFIG_AT_USING_SOCKET=y -# CONFIG_AT_USING_SOCKET_SERVER is not set -CONFIG_AT_USING_CLI=y -# CONFIG_AT_PRINT_RAW_CMD is not set -CONFIG_AT_CMD_MAX_LEN=128 -CONFIG_AT_SW_VERSION_NUM=0x10301 - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -CONFIG_RT_USING_ULOG=y -# CONFIG_ULOG_OUTPUT_LVL_A is not set -# CONFIG_ULOG_OUTPUT_LVL_E is not set -# CONFIG_ULOG_OUTPUT_LVL_W is not set -# CONFIG_ULOG_OUTPUT_LVL_I is not set -CONFIG_ULOG_OUTPUT_LVL_D=y -CONFIG_ULOG_OUTPUT_LVL=7 -# CONFIG_ULOG_USING_ISR_LOG is not set -CONFIG_ULOG_ASSERT_ENABLE=y -CONFIG_ULOG_LINE_BUF_SIZE=128 -# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set - -# -# log format -# -# CONFIG_ULOG_OUTPUT_FLOAT is not set -CONFIG_ULOG_USING_COLOR=y -CONFIG_ULOG_OUTPUT_TIME=y -# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set -CONFIG_ULOG_OUTPUT_LEVEL=y -CONFIG_ULOG_OUTPUT_TAG=y -# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set -CONFIG_ULOG_BACKEND_USING_CONSOLE=y -# CONFIG_ULOG_BACKEND_USING_FILE is not set -# CONFIG_ULOG_USING_FILTER is not set -# CONFIG_ULOG_USING_SYSLOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -CONFIG_PKG_USING_AT_DEVICE=y -CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device" -# CONFIG_AT_DEVICE_USING_M26 is not set -# CONFIG_AT_DEVICE_USING_EC20 is not set -# CONFIG_AT_DEVICE_USING_ESP32 is not set -CONFIG_AT_DEVICE_USING_ESP8266=y -CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y -CONFIG_AT_DEVICE_ESP8266_SOCKET=y -CONFIG_AT_DEVICE_ESP8266_SAMPLE=y -# CONFIG_AT_DEVICE_ESP8266_SAMPLE_BSP_TAKEOVER is not set -CONFIG_ESP8266_SAMPLE_WIFI_SSID="NT_ZY_BUFFALO" -CONFIG_ESP8266_SAMPLE_WIFI_PASSWORD="12345678" -CONFIG_ESP8266_SAMPLE_CLIENT_NAME="uart2" -CONFIG_ESP8266_SAMPLE_RECV_BUFF_LEN=2048 -# CONFIG_AT_DEVICE_USING_RW007 is not set -# CONFIG_AT_DEVICE_USING_SIM800C is not set -# CONFIG_AT_DEVICE_USING_SIM76XX is not set -# CONFIG_AT_DEVICE_USING_MW31 is not set -# CONFIG_AT_DEVICE_USING_W60X is not set -# CONFIG_AT_DEVICE_USING_A9G is not set -# CONFIG_AT_DEVICE_USING_BC26 is not set -# CONFIG_AT_DEVICE_USING_AIR720 is not set -# CONFIG_AT_DEVICE_USING_ME3616 is not set -# CONFIG_AT_DEVICE_USING_M6315 is not set -# CONFIG_AT_DEVICE_USING_BC28 is not set -# CONFIG_AT_DEVICE_USING_EC200X is not set -# CONFIG_AT_DEVICE_USING_N21 is not set -# CONFIG_AT_DEVICE_USING_N58 is not set -# CONFIG_AT_DEVICE_USING_M5311 is not set -# CONFIG_AT_DEVICE_USING_L610 is not set -# CONFIG_AT_DEVICE_USING_N720 is not set -# CONFIG_PKG_USING_AT_DEVICE_V204 is not set -# CONFIG_PKG_USING_AT_DEVICE_V203 is not set -# CONFIG_PKG_USING_AT_DEVICE_V202 is not set -# CONFIG_PKG_USING_AT_DEVICE_V201 is not set -# CONFIG_PKG_USING_AT_DEVICE_V200 is not set -CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y -CONFIG_PKG_AT_DEVICE_VER="latest" -CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=5 -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -# CONFIG_PKG_LVGL_USING_V08020 is not set -# CONFIG_PKG_LVGL_USING_V08030 is not set -CONFIG_PKG_LVGL_USING_LATEST_VERSION=y -CONFIG_PKG_LVGL_VER_NUM=0x99999 -CONFIG_PKG_LVGL_VER="latest" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -CONFIG_PKG_USING_SENSORS_DRIVERS=y -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -CONFIG_PKG_USING_MPU6XXX=y -CONFIG_PKG_MPU6XXX_PATH="/packages/peripherals/sensors/mpu6xxx" -# CONFIG_PKG_USING_MPU6XXX_V001 is not set -# CONFIG_PKG_USING_MPU6XXX_V100 is not set -# CONFIG_PKG_USING_MPU6XXX_V110 is not set -CONFIG_PKG_USING_MPU6XXX_LATEST_VERSION=y -CONFIG_PKG_MPU6XXX_VER="latest" -CONFIG_PKG_USING_MPU6XXX_ACCE=y -CONFIG_PKG_USING_MPU6XXX_GYRO=y -CONFIG_PKG_USING_MPU6XXX_MAG=y -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_M460=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=32 -CONFIG_BSP_USING_FMC=y -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_EMAC=y -CONFIG_BSP_USING_RTC=y -# CONFIG_NU_RTC_SUPPORT_IO_RW is not set -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y -# CONFIG_BSP_USING_CCAP is not set -# CONFIG_BSP_USING_DAC is not set -CONFIG_BSP_USING_EADC=y -CONFIG_BSP_USING_EADC0=y -# CONFIG_BSP_USING_EADC1 is not set -# CONFIG_BSP_USING_EADC2 is not set -CONFIG_BSP_USING_TMR=y -CONFIG_BSP_USING_TIMER=y -CONFIG_BSP_USING_TPWM=y -CONFIG_BSP_USING_TIMER_CAPTURE=y -CONFIG_BSP_USING_TMR0=y -CONFIG_BSP_USING_TIMER0=y -# CONFIG_BSP_USING_TPWM0 is not set -# CONFIG_BSP_USING_TIMER0_CAPTURE is not set -CONFIG_BSP_USING_TMR1=y -# CONFIG_BSP_USING_TIMER1 is not set -CONFIG_BSP_USING_TPWM1=y -# CONFIG_BSP_USING_TIMER1_CAPTURE is not set -CONFIG_BSP_USING_TMR2=y -# CONFIG_BSP_USING_TIMER2 is not set -# CONFIG_BSP_USING_TPWM2 is not set -CONFIG_BSP_USING_TIMER2_CAPTURE=y -CONFIG_BSP_USING_TMR3=y -CONFIG_BSP_USING_TIMER3=y -# CONFIG_BSP_USING_TPWM3 is not set -# CONFIG_BSP_USING_TIMER3_CAPTURE is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -CONFIG_BSP_USING_UART1=y -CONFIG_BSP_USING_UART1_TX_DMA=y -CONFIG_BSP_USING_UART1_RX_DMA=y -CONFIG_BSP_USING_UART2=y -CONFIG_BSP_USING_UART2_TX_DMA=y -CONFIG_BSP_USING_UART2_RX_DMA=y -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_UART6 is not set -# CONFIG_BSP_USING_UART7 is not set -# CONFIG_BSP_USING_UART8 is not set -# CONFIG_BSP_USING_UART9 is not set -CONFIG_BSP_USING_I2C=y -# CONFIG_BSP_USING_I2C0 is not set -# CONFIG_BSP_USING_I2C1 is not set -CONFIG_BSP_USING_I2C2=y -# CONFIG_BSP_USING_I2C3 is not set -# CONFIG_BSP_USING_I2C4 is not set -# CONFIG_BSP_USING_USCI is not set -CONFIG_BSP_USING_SDH=y -CONFIG_BSP_USING_SDH0=y -# CONFIG_BSP_USING_SDH1 is not set -CONFIG_BSP_USING_CANFD=y -CONFIG_BSP_USING_CANFD0=y -# CONFIG_BSP_USING_CANFD1 is not set -# CONFIG_BSP_USING_CANFD2 is not set -# CONFIG_BSP_USING_CANFD3 is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_EPWM is not set -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI_PDMA=y -# CONFIG_BSP_USING_SPII2S is not set -CONFIG_BSP_USING_SPI0_NONE=y -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPII2S0 is not set -CONFIG_BSP_USING_SPI1_NONE=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPII2S1 is not set -# CONFIG_BSP_USING_SPI2_NONE is not set -CONFIG_BSP_USING_SPI2=y -# CONFIG_BSP_USING_SPII2S2 is not set -CONFIG_BSP_USING_SPI2_PDMA=y -CONFIG_BSP_USING_SPI3_NONE=y -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_USING_SPII2S3 is not set -CONFIG_BSP_USING_SPI4_NONE=y -# CONFIG_BSP_USING_SPI4 is not set -# CONFIG_BSP_USING_SPII2S4 is not set -CONFIG_BSP_USING_SPI5_NONE=y -# CONFIG_BSP_USING_SPI5 is not set -# CONFIG_BSP_USING_SPII2S5 is not set -CONFIG_BSP_USING_SPI6_NONE=y -# CONFIG_BSP_USING_SPI6 is not set -# CONFIG_BSP_USING_SPII2S6 is not set -CONFIG_BSP_USING_SPI7_NONE=y -# CONFIG_BSP_USING_SPI7 is not set -# CONFIG_BSP_USING_SPII2S7 is not set -CONFIG_BSP_USING_SPI8_NONE=y -# CONFIG_BSP_USING_SPI8 is not set -# CONFIG_BSP_USING_SPII2S8 is not set -CONFIG_BSP_USING_SPI9_NONE=y -# CONFIG_BSP_USING_SPI9 is not set -# CONFIG_BSP_USING_SPII2S9 is not set -CONFIG_BSP_USING_SPI10_NONE=y -# CONFIG_BSP_USING_SPI10 is not set -# CONFIG_BSP_USING_SPII2S10 is not set -# CONFIG_BSP_USING_I2S is not set -CONFIG_BSP_USING_QSPI=y -CONFIG_BSP_USING_QSPI0=y -# CONFIG_BSP_USING_QSPI0_PDMA is not set -# CONFIG_BSP_USING_QSPI1 is not set -# CONFIG_BSP_USING_SCUART is not set -# CONFIG_BSP_USING_ECAP is not set -# CONFIG_BSP_USING_EQEI is not set -CONFIG_BSP_USING_CRYPTO=y -# CONFIG_NU_PRNG_USE_SEED is not set -CONFIG_BSP_USING_TRNG=y -CONFIG_BSP_USING_CRC=y -CONFIG_NU_CRC_USE_PDMA=y -# CONFIG_BSP_USING_SOFT_I2C is not set -CONFIG_BSP_USING_WDT=y -# CONFIG_BSP_USING_EBI is not set -# CONFIG_BSP_USING_HBI is not set -CONFIG_BSP_USING_USBD=y -# CONFIG_BSP_USING_HSUSBD is not set -# CONFIG_BSP_USING_USBH is not set -CONFIG_BSP_USING_HSUSBH=y -CONFIG_NU_USBHOST_HUB_POLLING_INTERVAL=100 -# CONFIG_BSP_USING_HSOTG is not set - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_NULINKME=y -CONFIG_BOARD_USING_RTL8201FI=y -CONFIG_BOARD_USING_ESP8266=y -CONFIG_BOARD_USING_STORAGE_SDCARD=y -CONFIG_BOARD_USING_STORAGE_SPIFLASH=y -CONFIG_BOARD_USING_CANFD0=y -CONFIG_BOARD_USING_NCT7717U=y -CONFIG_BOARD_USING_MPU6500=y -CONFIG_BOARD_USING_USB_D_H=y -# CONFIG_BOARD_USING_HSUSBD is not set -# CONFIG_BOARD_USING_HSUSBD_USBH is not set -# CONFIG_BOARD_USING_HSUSBH is not set -CONFIG_BOARD_USING_HSUSBH_USBD=y -# CONFIG_BOARD_USING_HSOTG is not set - -# -# Board extended module drivers -# -# CONFIG_BOARD_USING_MAX31875 is not set -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=21 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=19 -CONFIG_BOARD_USING_ILI9341_PIN_DC=18 - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -CONFIG_NU_PKG_USING_DEMO=y -# CONFIG_NU_PKG_USING_LVGL is not set -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -CONFIG_NU_PKG_USING_NCT7717U=y -# CONFIG_NU_PKG_USING_NAU88L25 is not set -# CONFIG_NU_PKG_USING_NAU8822 is not set -# CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -CONFIG_NU_PKG_USING_ILI9341_SPI=y -# CONFIG_NU_PKG_USING_ILI9341_EBI is not set -CONFIG_NU_PKG_USING_ILI9341_SPI_CLK_FREQ=48000000 -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=120 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 -# CONFIG_NU_PKG_USING_SSD1963 is not set -# CONFIG_NU_PKG_USING_FSA506 is not set -# CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -CONFIG_NU_PKG_USING_ADC_TOUCH_SW=y -# CONFIG_NU_PKG_USING_SPINAND is not set -CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." -CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-iot-m467/rtconfig.h b/bsp/nuvoton/numaker-iot-m467/rtconfig.h index 6157c9e966c..b7a58f075be 100644 --- a/bsp/nuvoton/numaker-iot-m467/rtconfig.h +++ b/bsp/nuvoton/numaker-iot-m467/rtconfig.h @@ -72,7 +72,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-iot-m487/.config b/bsp/nuvoton/numaker-iot-m487/.config index 8cd8adfbbc9..ffc5c6ca27e 100644 --- a/bsp/nuvoton/numaker-iot-m487/.config +++ b/bsp/nuvoton/numaker-iot-m487/.config @@ -106,7 +106,7 @@ # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-iot-m487/config_lvgl b/bsp/nuvoton/numaker-iot-m487/config_lvgl deleted file mode 100644 index 02d41f87380..00000000000 --- a/bsp/nuvoton/numaker-iot-m487/config_lvgl +++ /dev/null @@ -1,924 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=12 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -CONFIG_RT_USING_SIGNALS=y - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=8 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_DFS_FD_MAX=32 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=8 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=2048 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_CLOCK_TIME=y -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -CONFIG_RT_USING_QSPI=y -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -CONFIG_RT_SFUD_USING_SFDP=y -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -# CONFIG_RT_SFUD_USING_QSPI is not set -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y -CONFIG_RT_USING_AUDIO=y -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 -CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 -CONFIG_RT_USING_SENSOR=y -CONFIG_RT_USING_SENSOR_CMD=y -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set -CONFIG_RT_USING_HWCRYPTO=y -CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" -CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 -CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 -# CONFIG_RT_HWCRYPTO_USING_GCM is not set -CONFIG_RT_HWCRYPTO_USING_AES=y -CONFIG_RT_HWCRYPTO_USING_AES_ECB=y -CONFIG_RT_HWCRYPTO_USING_AES_CBC=y -CONFIG_RT_HWCRYPTO_USING_AES_CFB=y -CONFIG_RT_HWCRYPTO_USING_AES_CTR=y -CONFIG_RT_HWCRYPTO_USING_AES_OFB=y -CONFIG_RT_HWCRYPTO_USING_DES=y -CONFIG_RT_HWCRYPTO_USING_DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_DES_CBC=y -CONFIG_RT_HWCRYPTO_USING_3DES=y -CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y -# CONFIG_RT_HWCRYPTO_USING_RC4 is not set -# CONFIG_RT_HWCRYPTO_USING_MD5 is not set -CONFIG_RT_HWCRYPTO_USING_SHA1=y -CONFIG_RT_HWCRYPTO_USING_SHA2=y -CONFIG_RT_HWCRYPTO_USING_SHA2_224=y -CONFIG_RT_HWCRYPTO_USING_SHA2_256=y -CONFIG_RT_HWCRYPTO_USING_SHA2_384=y -CONFIG_RT_HWCRYPTO_USING_SHA2_512=y -CONFIG_RT_HWCRYPTO_USING_RNG=y -CONFIG_RT_HWCRYPTO_USING_CRC=y -CONFIG_RT_HWCRYPTO_USING_CRC_07=y -CONFIG_RT_HWCRYPTO_USING_CRC_8005=y -CONFIG_RT_HWCRYPTO_USING_CRC_1021=y -# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set -CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y -# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -CONFIG_RT_USING_USB=y -CONFIG_RT_USING_USB_HOST=y -CONFIG_RT_USBH_MSTORAGE=y -CONFIG_UDISK_MOUNTPOINT="/mnt/udisk/" -# CONFIG_RT_USBH_HID is not set -CONFIG_RT_USING_USB_DEVICE=y -CONFIG_RT_USBD_THREAD_STACK_SZ=4096 -CONFIG_USB_VENDOR_ID=0x0FFE -CONFIG_USB_PRODUCT_ID=0x0001 -# CONFIG_RT_USB_DEVICE_COMPOSITE is not set -# CONFIG__RT_USB_DEVICE_NONE is not set -# CONFIG__RT_USB_DEVICE_CDC is not set -# CONFIG__RT_USB_DEVICE_MSTORAGE is not set -CONFIG__RT_USB_DEVICE_HID=y -# CONFIG__RT_USB_DEVICE_WINUSB is not set -# CONFIG__RT_USB_DEVICE_AUDIO is not set -CONFIG_RT_USB_DEVICE_HID=y -# CONFIG_RT_USB_DEVICE_HID_KEYBOARD is not set -CONFIG_RT_USB_DEVICE_HID_MOUSE=y -# CONFIG_RT_USB_DEVICE_HID_GENERAL is not set -# CONFIG_RT_USB_DEVICE_HID_MEDIA is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -# CONFIG_RT_USING_POSIX_STDIO is not set -CONFIG_RT_USING_POSIX_POLL=y -CONFIG_RT_USING_POSIX_SELECT=y -# CONFIG_RT_USING_POSIX_SOCKET is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -CONFIG_PKG_LVGL_VER_NUM=0x99999 -CONFIG_PKG_LVGL_VER="latest" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# POSIX extension functions -# -# CONFIG_PKG_USING_POSIX_GETLINE is not set -# CONFIG_PKG_USING_POSIX_WCWIDTH is not set -# CONFIG_PKG_USING_POSIX_ITOA is not set -# CONFIG_PKG_USING_POSIX_STRINGS is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_M480=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 -# CONFIG_BSP_USING_FMC is not set -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_CLK=y -CONFIG_NU_CLK_INVOKE_WKTMR=y -# CONFIG_BSP_USING_EMAC is not set -CONFIG_BSP_USING_RTC=y -# CONFIG_NU_RTC_SUPPORT_IO_RW is not set -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y -CONFIG_BSP_USING_EADC=y -CONFIG_BSP_USING_EADC0=y -# CONFIG_BSP_USING_EADC1 is not set -CONFIG_BSP_USING_TMR=y -# CONFIG_BSP_USING_TMR0 is not set -# CONFIG_BSP_USING_TMR1 is not set -# CONFIG_BSP_USING_TMR2 is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_UART6 is not set -# CONFIG_BSP_USING_UART7 is not set -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C0=y -CONFIG_BSP_USING_I2C1=y -CONFIG_BSP_USING_I2C2=y -CONFIG_BSP_USING_USCI=y -CONFIG_BSP_USING_UUART=y -# CONFIG_BSP_USING_USPI_PDMA is not set -CONFIG_BSP_USING_USCI0=y -CONFIG_BSP_USING_UUART0=y -# CONFIG_BSP_USING_UI2C0 is not set -# CONFIG_BSP_USING_USPI0 is not set -CONFIG_BSP_USING_UUART0_TX_DMA=y -CONFIG_BSP_USING_UUART0_RX_DMA=y -# CONFIG_BSP_USING_USCI1 is not set -# CONFIG_BSP_USING_SDH is not set -# CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_EPWM is not set -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI_PDMA=y -# CONFIG_BSP_USING_SPII2S is not set -CONFIG_BSP_USING_SPI0_NONE=y -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPII2S0 is not set -# CONFIG_BSP_USING_SPI1_NONE is not set -CONFIG_BSP_USING_SPI1=y -# CONFIG_BSP_USING_SPII2S1 is not set -CONFIG_BSP_USING_SPI1_PDMA=y -# CONFIG_BSP_USING_SPI2_NONE is not set -CONFIG_BSP_USING_SPI2=y -# CONFIG_BSP_USING_SPII2S2 is not set -# CONFIG_BSP_USING_SPI2_PDMA is not set -CONFIG_BSP_USING_SPI3_NONE=y -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_USING_SPII2S3 is not set -# CONFIG_BSP_USING_I2S is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_SCUART is not set -# CONFIG_BSP_USING_ECAP is not set -# CONFIG_BSP_USING_QEI is not set -# CONFIG_BSP_USING_CRYPTO is not set -# CONFIG_BSP_USING_TRNG is not set -# CONFIG_BSP_USING_CRC is not set -# CONFIG_BSP_USING_SOFT_I2C is not set -# CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_EBI is not set -# CONFIG_BSP_USING_USBD is not set -# CONFIG_BSP_USING_HSUSBD is not set -# CONFIG_BSP_USING_USBH is not set -# CONFIG_BSP_USING_HSUSBH is not set -# CONFIG_BSP_USING_HSOTG is not set - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_NULINKME=y -# CONFIG_BOARD_USING_IP101GR is not set -# CONFIG_BOARD_USING_ESP8266 is not set -# CONFIG_BOARD_USING_BMX055 is not set -# CONFIG_BOARD_USING_NAU88L25 is not set -# CONFIG_BOARD_USING_STORAGE_SDCARD is not set -# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set -# CONFIG_BOARD_USING_USB_D_H is not set - -# -# Board extended module drivers -# -# CONFIG_BOARD_USING_MAX31875 is not set -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=69 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=19 -CONFIG_BOARD_USING_ILI9341_PIN_DC=18 - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -# CONFIG_NU_PKG_USING_DEMO is not set -# CONFIG_NU_PKG_USING_LVGL is not set -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -# CONFIG_NU_PKG_USING_NAU88L25 is not set -# CONFIG_NU_PKG_USING_NAU8822 is not set -# CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -CONFIG_NU_PKG_USING_ILI9341_SPI=y -# CONFIG_NU_PKG_USING_ILI9341_EBI is not set -CONFIG_NU_PKG_USING_ILI9341_SPI_CLK_FREQ=48000000 -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=30 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 -# CONFIG_NU_PKG_USING_SSD1963 is not set -# CONFIG_NU_PKG_USING_FSA506 is not set -# CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -CONFIG_NU_PKG_USING_ADC_TOUCH_SW=y -# CONFIG_NU_PKG_USING_SPINAND is not set -CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." -CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-iot-m487/rtconfig.h b/bsp/nuvoton/numaker-iot-m487/rtconfig.h index d2252b262e8..6eb51a2a891 100644 --- a/bsp/nuvoton/numaker-iot-m487/rtconfig.h +++ b/bsp/nuvoton/numaker-iot-m487/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-iot-ma35d1/.config b/bsp/nuvoton/numaker-iot-ma35d1/.config index 92f3a45419e..f56e83ca23f 100644 --- a/bsp/nuvoton/numaker-iot-ma35d1/.config +++ b/bsp/nuvoton/numaker-iot-ma35d1/.config @@ -107,7 +107,7 @@ CONFIG_USE_MA35D1_AARCH32=y # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-iot-ma35d1/rtconfig.h b/bsp/nuvoton/numaker-iot-ma35d1/rtconfig.h index 15b3322df35..26b3af08550 100644 --- a/bsp/nuvoton/numaker-iot-ma35d1/rtconfig.h +++ b/bsp/nuvoton/numaker-iot-ma35d1/rtconfig.h @@ -63,7 +63,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-m032ki/.config b/bsp/nuvoton/numaker-m032ki/.config index 4de5a26b009..fdd7458488a 100644 --- a/bsp/nuvoton/numaker-m032ki/.config +++ b/bsp/nuvoton/numaker-m032ki/.config @@ -106,7 +106,7 @@ # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-m032ki/config_lvgl b/bsp/nuvoton/numaker-m032ki/config_lvgl deleted file mode 100644 index 374031f2bbc..00000000000 --- a/bsp/nuvoton/numaker-m032ki/config_lvgl +++ /dev/null @@ -1,844 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=12 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=512 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y -# CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M0=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_CLOCK_TIME=y -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -CONFIG_RT_USING_UTESTCASES=y - -# -# Utest Self Testcase -# -CONFIG_RT_UTEST_SELF_PASS=y - -# -# Kernel Testcase -# -CONFIG_RT_UTEST_SMALL_MEM=y -# CONFIG_UTEST_IRQ_TC is not set -# CONFIG_UTEST_SEMAPHORE_TC is not set -# CONFIG_UTEST_EVENT_TC is not set -# CONFIG_UTEST_TIMER_TC is not set -# CONFIG_UTEST_MESSAGEQUEUE_TC is not set -# CONFIG_UTEST_SIGNAL_TC is not set -# CONFIG_UTEST_MUTEX_TC is not set -# CONFIG_UTEST_MAILBOX_TC is not set -# CONFIG_UTEST_THREAD_TC is not set - -# -# CPP11 Testcase -# -# CONFIG_UTEST_CPP11_THREAD_TC is not set - -# -# Utest Serial Testcase -# -# CONFIG_UTEST_SERIAL_TC is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -CONFIG_PKG_LVGL_VER_NUM=0x99999 -CONFIG_PKG_LVGL_VER="latest" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# POSIX extension functions -# -# CONFIG_PKG_USING_POSIX_GETLINE is not set -# CONFIG_PKG_USING_POSIX_WCWIDTH is not set -# CONFIG_PKG_USING_POSIX_ITOA is not set -# CONFIG_PKG_USING_POSIX_STRINGS is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_M032=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=4 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 -# CONFIG_BSP_USING_FMC is not set -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_CLK=y -CONFIG_NU_CLK_INVOKE_WKTMR=y -CONFIG_BSP_USING_RTC=y -CONFIG_NU_RTC_SUPPORT_IO_RW=y -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y -CONFIG_BSP_USING_ADC=y -CONFIG_BSP_USING_ADC0=y -CONFIG_BSP_USING_TMR=y -CONFIG_BSP_USING_TIMER=y -CONFIG_BSP_USING_TMR0=y -CONFIG_BSP_USING_TIMER0=y -# CONFIG_BSP_USING_TIMER0_CAPTURE is not set -CONFIG_BSP_USING_TMR1=y -CONFIG_BSP_USING_TIMER1=y -# CONFIG_BSP_USING_TIMER1_CAPTURE is not set -CONFIG_BSP_USING_TMR2=y -CONFIG_BSP_USING_TIMER2=y -# CONFIG_BSP_USING_TIMER2_CAPTURE is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -CONFIG_BSP_USING_UART1=y -CONFIG_BSP_USING_UART1_TX_DMA=y -CONFIG_BSP_USING_UART1_RX_DMA=y -CONFIG_BSP_USING_UART2=y -# CONFIG_BSP_USING_UART2_TX_DMA is not set -# CONFIG_BSP_USING_UART2_RX_DMA is not set -CONFIG_BSP_USING_UART3=y -# CONFIG_BSP_USING_UART3_TX_DMA is not set -# CONFIG_BSP_USING_UART3_RX_DMA is not set -CONFIG_BSP_USING_UART4=y -# CONFIG_BSP_USING_UART4_TX_DMA is not set -# CONFIG_BSP_USING_UART4_RX_DMA is not set -CONFIG_BSP_USING_UART5=y -# CONFIG_BSP_USING_UART5_TX_DMA is not set -# CONFIG_BSP_USING_UART5_RX_DMA is not set -CONFIG_BSP_USING_UART6=y -# CONFIG_BSP_USING_UART6_TX_DMA is not set -# CONFIG_BSP_USING_UART6_RX_DMA is not set -CONFIG_BSP_USING_UART7=y -# CONFIG_BSP_USING_UART7_TX_DMA is not set -# CONFIG_BSP_USING_UART7_RX_DMA is not set -# CONFIG_BSP_USING_I2C is not set -CONFIG_BSP_USING_USCI=y -CONFIG_BSP_USING_USPI=y -CONFIG_BSP_USING_USPI_PDMA=y -CONFIG_BSP_USING_USCI0=y -# CONFIG_BSP_USING_UUART0 is not set -# CONFIG_BSP_USING_UI2C0 is not set -CONFIG_BSP_USING_USPI0=y -CONFIG_BSP_USING_USPI0_PDMA=y -# CONFIG_BSP_USING_USCI1 is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_PWM is not set -CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI_PDMA is not set -# CONFIG_BSP_USING_SPII2S is not set -CONFIG_BSP_USING_SPI0_NONE=y -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPII2S0 is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_CRC is not set -# CONFIG_BSP_USING_SOFT_I2C is not set -CONFIG_BSP_USING_WDT=y -# CONFIG_BSP_USING_EBI is not set -# CONFIG_BSP_USING_USBD is not set - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_NULINKME=y - -# -# Board extended module drivers -# -# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=6 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=19 -CONFIG_BOARD_USING_ILI9341_PIN_DC=18 - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -# CONFIG_NU_PKG_USING_DEMO is not set -# CONFIG_NU_PKG_USING_LVGL is not set -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -# CONFIG_NU_PKG_USING_NAU88L25 is not set -# CONFIG_NU_PKG_USING_NAU8822 is not set -# CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -CONFIG_NU_PKG_USING_ILI9341_SPI=y -# CONFIG_NU_PKG_USING_ILI9341_EBI is not set -CONFIG_NU_PKG_USING_ILI9341_SPI_CLK_FREQ=24000000 -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=30 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 -# CONFIG_NU_PKG_USING_SSD1963 is not set -# CONFIG_NU_PKG_USING_FSA506 is not set -# CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -CONFIG_NU_PKG_USING_ADC_TOUCH_SW=y -# CONFIG_NU_PKG_USING_SPINAND is not set -CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." -CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-m032ki/rtconfig.h b/bsp/nuvoton/numaker-m032ki/rtconfig.h index cfb07b8beab..460939dc0c3 100644 --- a/bsp/nuvoton/numaker-m032ki/rtconfig.h +++ b/bsp/nuvoton/numaker-m032ki/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-m2354/.config b/bsp/nuvoton/numaker-m2354/.config index f5c9cc1e266..20943cdfec8 100644 --- a/bsp/nuvoton/numaker-m2354/.config +++ b/bsp/nuvoton/numaker-m2354/.config @@ -106,7 +106,7 @@ # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-m2354/rtconfig.h b/bsp/nuvoton/numaker-m2354/rtconfig.h index 8aad7b334fb..bea832e6a4d 100644 --- a/bsp/nuvoton/numaker-m2354/rtconfig.h +++ b/bsp/nuvoton/numaker-m2354/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-m2354/config_lvgl b/bsp/nuvoton/numaker-m3334ki/.config similarity index 63% rename from bsp/nuvoton/numaker-m2354/config_lvgl rename to bsp/nuvoton/numaker-m3334ki/.config index 57e8f347ba2..390681ad51f 100644 --- a/bsp/nuvoton/numaker-m2354/config_lvgl +++ b/bsp/nuvoton/numaker-m3334ki/.config @@ -1,17 +1,119 @@ + # -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration +# RT-Thread Kernel # # -# RT-Thread Kernel +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + # -CONFIG_RT_NAME_MAX=12 +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set @@ -20,22 +122,28 @@ CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=2048 -# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # -# kservice optimization +# kservice options # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice options + CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y -CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set # # Inter-Thread communication @@ -47,6 +155,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set CONFIG_RT_USING_SIGNALS=y +# end of Inter-Thread communication # # Memory Management @@ -54,7 +163,9 @@ CONFIG_RT_USING_SIGNALS=y CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_SLAB_AS_HEAP is not set @@ -63,27 +174,29 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management -# -# Kernel Device Object -# CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50001 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M23=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y # # RT-Thread Components @@ -101,6 +214,8 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -108,6 +223,7 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system @@ -116,7 +232,7 @@ CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y # CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=32 +CONFIG_DFS_FD_MAX=16 CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 @@ -139,52 +255,70 @@ CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y # CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set CONFIG_RT_DFS_ELM_LFN_UNICODE=0 CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_DRIVES=4 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +# end of elm-chan's FatFs, Generic FAT Filesystem Module + CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_9PFS is not set +# CONFIG_RT_USING_DFS_ISO9660 is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + CONFIG_RT_USING_FAL=y -CONFIG_FAL_DEBUG_CONFIG=y -CONFIG_FAL_DEBUG=1 +CONFIG_FAL_USING_DEBUG=y CONFIG_FAL_PART_HAS_TABLE_CFG=y # CONFIG_FAL_USING_SFUD_PORT is not set +CONFIG_FAL_DEV_NAME_MAX=24 +CONFIG_FAL_DEV_BLK_MAX=6 # # Device Drivers # +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=2048 +# CONFIG_RT_USING_SERIAL_BYPASS is not set CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_CLOCK_TIME=y +CONFIG_RT_CANMSG_BOX_SZ=16 +CONFIG_RT_CANSND_BOX_NUM=1 +CONFIG_RT_CANSND_MSG_TIMEOUT=100 +CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 +# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set +# CONFIG_RT_USING_CLOCK_TIME is not set CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set # CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PHY_V2 is not set CONFIG_RT_USING_ADC=y # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set CONFIG_RT_USING_PWM=y +CONFIG_RT_USING_PULSE_ENCODER=y +CONFIG_RT_USING_INPUT_CAPTURE=y +CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100 # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set CONFIG_RT_USING_PM=y @@ -193,21 +327,17 @@ CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 # CONFIG_PM_ENABLE_DEBUG is not set # CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set # CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -# CONFIG_RT_USING_FDT is not set CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y # CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_SOFT_SPI is not set CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -CONFIG_RT_SFUD_USING_SFDP=y -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -CONFIG_RT_SFUD_USING_QSPI=y -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -CONFIG_RT_DEBUG_SFUD=y +# CONFIG_RT_USING_SFUD is not set # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set CONFIG_RT_USING_WDT=y @@ -215,75 +345,37 @@ CONFIG_RT_USING_AUDIO=y CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 -CONFIG_RT_USING_SENSOR=y -# CONFIG_RT_USING_SENSOR_V2 is not set -CONFIG_RT_USING_SENSOR_CMD=y -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set CONFIG_RT_USING_HWCRYPTO=y CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 # CONFIG_RT_HWCRYPTO_USING_GCM is not set -CONFIG_RT_HWCRYPTO_USING_AES=y -CONFIG_RT_HWCRYPTO_USING_AES_ECB=y -CONFIG_RT_HWCRYPTO_USING_AES_CBC=y -CONFIG_RT_HWCRYPTO_USING_AES_CFB=y -CONFIG_RT_HWCRYPTO_USING_AES_CTR=y -CONFIG_RT_HWCRYPTO_USING_AES_OFB=y -CONFIG_RT_HWCRYPTO_USING_DES=y -CONFIG_RT_HWCRYPTO_USING_DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_DES_CBC=y -CONFIG_RT_HWCRYPTO_USING_3DES=y -CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y +# CONFIG_RT_HWCRYPTO_USING_AES is not set +# CONFIG_RT_HWCRYPTO_USING_DES is not set +# CONFIG_RT_HWCRYPTO_USING_3DES is not set # CONFIG_RT_HWCRYPTO_USING_RC4 is not set # CONFIG_RT_HWCRYPTO_USING_MD5 is not set -CONFIG_RT_HWCRYPTO_USING_SHA1=y -CONFIG_RT_HWCRYPTO_USING_SHA2=y -CONFIG_RT_HWCRYPTO_USING_SHA2_224=y -CONFIG_RT_HWCRYPTO_USING_SHA2_256=y -CONFIG_RT_HWCRYPTO_USING_SHA2_384=y -CONFIG_RT_HWCRYPTO_USING_SHA2_512=y -CONFIG_RT_HWCRYPTO_USING_RNG=y +# CONFIG_RT_HWCRYPTO_USING_SHA1 is not set +# CONFIG_RT_HWCRYPTO_USING_SHA2 is not set +# CONFIG_RT_HWCRYPTO_USING_RNG is not set CONFIG_RT_HWCRYPTO_USING_CRC=y CONFIG_RT_HWCRYPTO_USING_CRC_07=y CONFIG_RT_HWCRYPTO_USING_CRC_8005=y CONFIG_RT_HWCRYPTO_USING_CRC_1021=y -# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set +CONFIG_RT_HWCRYPTO_USING_CRC_3D65=y CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y # CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set # CONFIG_RT_USING_VIRTIO is not set - -# -# Using USB -# -CONFIG_RT_USING_USB=y -CONFIG_RT_USING_USB_HOST=y -CONFIG_RT_USBH_MSTORAGE=y -CONFIG_UDISK_MOUNTPOINT="/" -# CONFIG_RT_USBH_HID is not set -CONFIG_RT_USING_USB_DEVICE=y -CONFIG_RT_USBD_THREAD_STACK_SZ=4096 -CONFIG_USB_VENDOR_ID=0x0FFE -CONFIG_USB_PRODUCT_ID=0x0001 -# CONFIG_RT_USB_DEVICE_COMPOSITE is not set -# CONFIG__RT_USB_DEVICE_NONE is not set -# CONFIG__RT_USB_DEVICE_CDC is not set -# CONFIG__RT_USB_DEVICE_MSTORAGE is not set -CONFIG__RT_USB_DEVICE_HID=y -# CONFIG__RT_USB_DEVICE_WINUSB is not set -# CONFIG__RT_USB_DEVICE_AUDIO is not set -CONFIG_RT_USB_DEVICE_HID=y -# CONFIG_RT_USB_DEVICE_HID_KEYBOARD is not set -CONFIG_RT_USB_DEVICE_HID_MOUSE=y -# CONFIG_RT_USB_DEVICE_HID_GENERAL is not set -# CONFIG_RT_USB_DEVICE_HID_MEDIA is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -301,20 +393,13 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer # -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -# CONFIG_RT_USING_POSIX_STDIO is not set -CONFIG_RT_USING_POSIX_POLL=y -CONFIG_RT_USING_POSIX_SELECT=y -# CONFIG_RT_USING_POSIX_EVENTFD is not set -# CONFIG_RT_USING_POSIX_SOCKET is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set +# CONFIG_RT_USING_POSIX_FS is not set # CONFIG_RT_USING_POSIX_DELAY is not set # CONFIG_RT_USING_POSIX_CLOCK is not set # CONFIG_RT_USING_POSIX_TIMER is not set @@ -331,63 +416,91 @@ CONFIG_RT_USING_POSIX_SELECT=y # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network # -CONFIG_RT_USING_SAL=y -CONFIG_SAL_INTERNET_CHECK=y - -# -# Docking with protocol stacks -# -# CONFIG_SAL_USING_LWIP is not set -CONFIG_SAL_USING_AT=y -# CONFIG_SAL_USING_TLS is not set -CONFIG_SAL_USING_POSIX=y -# CONFIG_SAL_USING_AF_UNIX is not set -CONFIG_RT_USING_NETDEV=y -CONFIG_NETDEV_USING_IFCONFIG=y -CONFIG_NETDEV_USING_PING=y -CONFIG_NETDEV_USING_NETSTAT=y -CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set -CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 -# CONFIG_NETDEV_IPV6_SCOPES is not set +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set -CONFIG_RT_USING_AT=y -# CONFIG_AT_DEBUG is not set -# CONFIG_AT_USING_SERVER is not set -CONFIG_AT_USING_CLIENT=y -CONFIG_AT_CLIENT_NUM_MAX=1 -CONFIG_AT_USING_SOCKET=y -# CONFIG_AT_USING_SOCKET_SERVER is not set -CONFIG_AT_USING_CLI=y -# CONFIG_AT_PRINT_RAW_CMD is not set -CONFIG_AT_CMD_MAX_LEN=2048 -CONFIG_AT_SW_VERSION_NUM=0x10301 +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities # # CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +# CONFIG_ULOG_OUTPUT_LVL_EMERG is not set +# CONFIG_ULOG_OUTPUT_LVL_ALERT is not set +# CONFIG_ULOG_OUTPUT_LVL_CRIT is not set +# CONFIG_ULOG_OUTPUT_LVL_ERROR is not set +# CONFIG_ULOG_OUTPUT_LVL_WARNING is not set +# CONFIG_ULOG_OUTPUT_LVL_NOTICE is not set +# CONFIG_ULOG_OUTPUT_LVL_INFO is not set +# CONFIG_ULOG_OUTPUT_LVL_DEBUG is not set +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=1024 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +# end of log format + +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set -# CONFIG_RT_USING_CLOCK_TIME is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -396,7 +509,6 @@ CONFIG_UTEST_THR_PRIORITY=20 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -409,6 +521,8 @@ CONFIG_UTEST_THR_PRIORITY=20 # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -418,59 +532,41 @@ CONFIG_UTEST_THR_PRIORITY=20 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set # CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set -CONFIG_PKG_USING_AT_DEVICE=y -CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device" -# CONFIG_AT_DEVICE_USING_M26 is not set -# CONFIG_AT_DEVICE_USING_EC20 is not set -# CONFIG_AT_DEVICE_USING_ESP32 is not set -CONFIG_AT_DEVICE_USING_ESP8266=y -CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y -CONFIG_AT_DEVICE_ESP8266_SOCKET=y -# CONFIG_AT_DEVICE_ESP8266_SAMPLE is not set -# CONFIG_AT_DEVICE_ESP8266_SAMPLE_BSP_TAKEOVER is not set -# CONFIG_AT_DEVICE_USING_RW007 is not set -# CONFIG_AT_DEVICE_USING_SIM800C is not set -# CONFIG_AT_DEVICE_USING_SIM76XX is not set -# CONFIG_AT_DEVICE_USING_MW31 is not set -# CONFIG_AT_DEVICE_USING_W60X is not set -# CONFIG_AT_DEVICE_USING_A9G is not set -# CONFIG_AT_DEVICE_USING_BC26 is not set -# CONFIG_AT_DEVICE_USING_AIR720 is not set -# CONFIG_AT_DEVICE_USING_ME3616 is not set -# CONFIG_AT_DEVICE_USING_M6315 is not set -# CONFIG_AT_DEVICE_USING_BC28 is not set -# CONFIG_AT_DEVICE_USING_EC200X is not set -# CONFIG_AT_DEVICE_USING_N21 is not set -# CONFIG_AT_DEVICE_USING_N58 is not set -# CONFIG_AT_DEVICE_USING_M5311 is not set -# CONFIG_AT_DEVICE_USING_L610 is not set -# CONFIG_AT_DEVICE_USING_N720 is not set -# CONFIG_AT_DEVICE_USING_ML305 is not set -# CONFIG_PKG_USING_AT_DEVICE_V210 is not set -# CONFIG_PKG_USING_AT_DEVICE_V204 is not set -# CONFIG_PKG_USING_AT_DEVICE_V203 is not set -# CONFIG_PKG_USING_AT_DEVICE_V202 is not set -# CONFIG_PKG_USING_AT_DEVICE_V201 is not set -# CONFIG_PKG_USING_AT_DEVICE_V200 is not set -CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y -CONFIG_PKG_AT_DEVICE_VER="latest" -CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 +# CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # CONFIG_PKG_USING_ZB_COORDINATOR is not set @@ -486,8 +582,9 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -507,6 +604,8 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set # CONFIG_PKG_USING_MAVLINK is not set @@ -526,6 +625,13 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # CONFIG_PKG_USING_ZFTP is not set # CONFIG_PKG_USING_WOL is not set # CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things # # security packages @@ -536,6 +642,7 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -551,18 +658,23 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -571,37 +683,19 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999 # # LVGL: powerful and easy-to-use embedded GUI library # -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_USING_LVGL_SQUARELINE is not set -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -CONFIG_PKG_LVGL_USING_V08039=y -# CONFIG_PKG_LVGL_USING_V08038 is not set -# CONFIG_PKG_LVGL_USING_V08037 is not set -# CONFIG_PKG_LVGL_USING_V08036 is not set -# CONFIG_PKG_LVGL_USING_V08035 is not set -# CONFIG_PKG_LVGL_USING_V08034 is not set -# CONFIG_PKG_LVGL_USING_V08033 is not set -# CONFIG_PKG_LVGL_USING_V08032 is not set -# CONFIG_PKG_LVGL_USING_V08031 is not set -# CONFIG_PKG_LVGL_USING_V08030 is not set -# CONFIG_PKG_LVGL_USING_V08020 is not set -# CONFIG_PKG_LVGL_USING_V8_3_LATEST_VERSION is not set -# CONFIG_PKG_LVGL_USING_LATEST_VERSION is not set -CONFIG_PKG_LVGL_VER_NUM=0x080309 -CONFIG_PKG_LVGL_VER="v8.3.9" +# CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -621,11 +715,16 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -669,6 +768,13 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages # # system packages @@ -679,7 +785,9 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set # # acceleration: Assembly language or algorithmic acceleration packages @@ -687,13 +795,17 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -704,6 +816,8 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -711,6 +825,8 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set # CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set @@ -730,13 +846,13 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set # CONFIG_PKG_USING_LPM is not set # CONFIG_PKG_USING_TLSF is not set # CONFIG_PKG_USING_EVENT_RECORDER is not set # CONFIG_PKG_USING_ARM_2D is not set # CONFIG_PKG_USING_MCUBOOT is not set # CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set # CONFIG_PKG_USING_KMULTI_RTIMER is not set # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set @@ -744,12 +860,196 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_FLASH_BLOB is not set # CONFIG_PKG_USING_MLIBC is not set # CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set # CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages # # peripheral libraries and drivers # +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-cmsis" +CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nuvoton/nuvoton-series" +CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NUVOTON_SERIES_DRIVER_VER="latest" +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + # # sensors drivers # @@ -785,14 +1085,19 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_BMI088 is not set # CONFIG_PKG_USING_HMC5883 is not set # CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set # CONFIG_PKG_USING_TMP1075 is not set # CONFIG_PKG_USING_SR04 is not set # CONFIG_PKG_USING_CCS811 is not set # CONFIG_PKG_USING_PMSXX is not set # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -818,6 +1123,11 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers # # touch drivers @@ -831,9 +1141,11 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set @@ -841,14 +1153,6 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set @@ -863,7 +1167,6 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set # CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set @@ -886,7 +1189,6 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_RDA58XX is not set # CONFIG_PKG_USING_LIBNFC is not set # CONFIG_PKG_USING_MFOC is not set @@ -896,7 +1198,6 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_MICRO_ROS is not set # CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set @@ -904,14 +1205,34 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set # CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set # CONFIG_PKG_USING_BT_ECB02C is not set # CONFIG_PKG_USING_UAT is not set # CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -925,16 +1246,21 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set # CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -943,6 +1269,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -951,6 +1278,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -966,12 +1294,16 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -988,6 +1320,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_STATE_MACHINE is not set # CONFIG_PKG_USING_DESIGN_PATTERN is not set @@ -998,6 +1331,8 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages # # Arduino libraries @@ -1008,21 +1343,25 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # Projects and Demos # # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors # # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set @@ -1067,7 +1406,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set @@ -1106,7 +1445,6 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set @@ -1129,7 +1467,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set @@ -1137,7 +1475,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set @@ -1150,6 +1488,9 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1161,6 +1502,7 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1169,12 +1511,16 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing # # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1185,23 +1531,26 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1214,10 +1563,13 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages # # Hardware Drivers Config @@ -1226,125 +1578,146 @@ CONFIG_PKG_LVGL_VER="v8.3.9" # # On-chip Peripheral Drivers # -CONFIG_SOC_SERIES_M2354=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 -CONFIG_BSP_USING_FMC=y -CONFIG_BSP_USING_GPIO=y +CONFIG_SOC_FAMILY_NUMICRO=y +CONFIG_SOC_SERIES_M3331=y +CONFIG_BSP_USING_BPWM=y +CONFIG_BSP_USING_BPWM_CAPTURE=y +CONFIG_BSP_USING_BPWM0=y +# CONFIG_BSP_USING_BPWM0_CAPTURE is not set +CONFIG_BSP_USING_BPWM1_CAPTURE=y +CONFIG_BSP_USING_BPWM2=y +# CONFIG_BSP_USING_BPWM2_CAPTURE is not set +CONFIG_BSP_USING_BPWM3=y +# CONFIG_BSP_USING_BPWM3_CAPTURE is not set +CONFIG_BSP_USING_BPWM4=y +# CONFIG_BSP_USING_BPWM4_CAPTURE is not set +CONFIG_BSP_USING_BPWM5=y +# CONFIG_BSP_USING_BPWM5_CAPTURE is not set +CONFIG_BSP_USING_CANFD=y +CONFIG_BSP_USING_CANFD0=y +CONFIG_BSP_USING_CANFD1=y CONFIG_BSP_USING_CLK=y -CONFIG_NU_CLK_INVOKE_WKTMR=y -CONFIG_BSP_USING_RTC=y -# CONFIG_NU_RTC_SUPPORT_IO_RW is not set -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y +CONFIG_BSP_USING_CRC=y +CONFIG_BSP_USING_CRC0=y +CONFIG_BSP_USING_CRYPTO=y +CONFIG_BSP_USING_CRYPTO0=y CONFIG_BSP_USING_EADC=y CONFIG_BSP_USING_EADC0=y -CONFIG_BSP_USING_TMR=y -# CONFIG_BSP_USING_TMR0 is not set -# CONFIG_BSP_USING_TMR1 is not set -# CONFIG_BSP_USING_TMR2 is not set -# CONFIG_BSP_USING_TMR3 is not set -# CONFIG_BSP_USING_TMR4 is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_UART1_TX_DMA is not set -# CONFIG_BSP_USING_UART1_RX_DMA is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -CONFIG_BSP_USING_UART4=y -CONFIG_BSP_USING_UART4_TX_DMA=y -CONFIG_BSP_USING_UART4_RX_DMA=y -# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_EBI is not set +CONFIG_BSP_USING_EPWM=y +CONFIG_BSP_USING_EPWM0=y +# CONFIG_BSP_USING_EPWM0_CAPTURE is not set +CONFIG_BSP_USING_EPWM1=y +# CONFIG_BSP_USING_EPWM1_CAPTURE is not set +CONFIG_BSP_USING_EQEI=y +CONFIG_BSP_USING_EQEI0=y +CONFIG_BSP_USING_EQEI1=y +CONFIG_BSP_USING_EQEI2=y +CONFIG_BSP_USING_EQEI3=y +CONFIG_BSP_USING_FMC=y +CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_I2C=y -# CONFIG_BSP_USING_I2C0 is not set +CONFIG_BSP_USING_I2C0=y CONFIG_BSP_USING_I2C1=y -# CONFIG_BSP_USING_I2C2 is not set -# CONFIG_BSP_USING_USCI is not set -# CONFIG_BSP_USING_SDH is not set -# CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_EPWM is not set +CONFIG_BSP_USING_I2C2=y +CONFIG_BSP_USING_I2C3=y +# CONFIG_BSP_USING_LPADC is not set +# CONFIG_BSP_USING_LPTMR is not set +CONFIG_BSP_USING_PDMA=y +CONFIG_BSP_USING_PDMA0=y +CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 +CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 +CONFIG_BSP_USING_QSPI=y +CONFIG_BSP_USING_QSPI0=y +CONFIG_BSP_USING_QSPI0_PDMA=y +CONFIG_BSP_USING_RTC=y +CONFIG_BSP_USING_RTC_INTERNAL=y +CONFIG_BSP_USING_SC=y +CONFIG_BSP_USING_SC0=y +CONFIG_BSP_USING_SC1=y +CONFIG_BSP_USING_SC2=y CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI_PDMA is not set -# CONFIG_BSP_USING_SPII2S is not set -# CONFIG_BSP_USING_SPI0_NONE is not set +CONFIG_BSP_USING_SPI_PDMA=y +CONFIG_BSP_USING_SPII2S=y CONFIG_BSP_USING_SPI0=y # CONFIG_BSP_USING_SPII2S0 is not set -# CONFIG_BSP_USING_SPI0_PDMA is not set -# CONFIG_BSP_USING_SPI1_NONE is not set -CONFIG_BSP_USING_SPI1=y -# CONFIG_BSP_USING_SPII2S1 is not set -# CONFIG_BSP_USING_SPI1_PDMA is not set -CONFIG_BSP_USING_SPI2_NONE=y -# CONFIG_BSP_USING_SPI2 is not set +CONFIG_BSP_USING_SPI0_PDMA=y +CONFIG_BSP_USING_SPII2S1=y +CONFIG_BSP_USING_SPI2=y # CONFIG_BSP_USING_SPII2S2 is not set -CONFIG_BSP_USING_SPI3_NONE=y -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_USING_SPII2S3 is not set -# CONFIG_BSP_USING_I2S is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_SCUART is not set -# CONFIG_BSP_USING_ECAP is not set -# CONFIG_BSP_USING_QEI is not set -# CONFIG_BSP_USING_CRYPTO is not set -# CONFIG_BSP_USING_TRNG is not set -# CONFIG_BSP_USING_CRC is not set -# CONFIG_BSP_USING_SOFT_I2C is not set +CONFIG_BSP_USING_SPI2_PDMA=y +CONFIG_BSP_USING_TMR=y +CONFIG_BSP_USING_TIMER=y +CONFIG_BSP_USING_TPWM=y +CONFIG_BSP_USING_TMR0=y +CONFIG_BSP_USING_TPWM0=y +CONFIG_BSP_USING_TMR1=y +CONFIG_BSP_USING_TIMER1=y +# CONFIG_BSP_USING_TPWM1 is not set +CONFIG_BSP_USING_TMR2=y +# CONFIG_BSP_USING_TIMER2 is not set +# CONFIG_BSP_USING_TPWM2 is not set +CONFIG_BSP_USING_TMR3=y +CONFIG_BSP_USING_TPWM3=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART3=y +CONFIG_BSP_USING_UART4=y +CONFIG_BSP_USING_UART5=y +CONFIG_BSP_USING_USCI=y +CONFIG_BSP_USING_UUART=y +CONFIG_BSP_USING_USCI0=y +CONFIG_BSP_USING_USCI1=y +CONFIG_BSP_USING_UUART0=y +CONFIG_BSP_USING_UUART0_TX_DMA=y +CONFIG_BSP_USING_UUART0_RX_DMA=y +CONFIG_BSP_USING_UUART1=y +CONFIG_BSP_USING_UUART1_TX_DMA=y +CONFIG_BSP_USING_UUART1_RX_DMA=y +CONFIG_BSP_USING_HSUSBD=y +CONFIG_BSP_USING_HSUSBH=y +CONFIG_BSP_USING_HSOTG=y CONFIG_BSP_USING_WDT=y -# CONFIG_BSP_USING_EBI is not set -# CONFIG_BSP_USING_SLCD is not set -# CONFIG_BSP_USING_USBD is not set -# CONFIG_BSP_USING_USBH is not set -# CONFIG_BSP_USING_OTG is not set +# end of On-chip Peripheral Drivers # # On-board Peripheral Drivers # -CONFIG_BSP_USING_NULINKME=y -CONFIG_BOARD_USING_ESP8266=y -# CONFIG_BOARD_USING_STORAGE_SDCARD is not set -# CONFIG_BOARD_USING_USBD is not set -# CONFIG_BOARD_USING_USBH is not set -# CONFIG_BOARD_USING_OTG is not set +CONFIG_BOARD_USING_NULINKME=y +# CONFIG_BSP_USING_CUSTOM_LOADER is not set +# CONFIG_BOARD_USING_HSUSBD is not set +# CONFIG_BOARD_USING_HSUSBH is not set +# CONFIG_BOARD_USING_USB_OTG is not set +# CONFIG_BOARD_USING_USB_SWOTG is not set CONFIG_BOARD_USING_USB_NONE=y +# end of On-board Peripheral Drivers # # Board extended module drivers # -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=43 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=9 -CONFIG_BOARD_USING_ILI9341_PIN_DC=8 -# CONFIG_BOARD_USING_SEGMENT_LCD is not set +CONFIG_BOARD_USING_NONE=y +# CONFIG_BOARD_USING_NUFUN is not set +# CONFIG_BOARD_USING_NUTFT is not set +# end of Board extended module drivers # # Nuvoton Packages Config # CONFIG_NU_PKG_USING_UTILS=y -# CONFIG_NU_PKG_USING_DEMO is not set +CONFIG_NU_PKG_USING_DEMO=y # CONFIG_NU_PKG_USING_BMX055 is not set # CONFIG_NU_PKG_USING_MAX31875 is not set # CONFIG_NU_PKG_USING_NCT7717U is not set # CONFIG_NU_PKG_USING_NAU88L25 is not set # CONFIG_NU_PKG_USING_NAU8822 is not set # CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -CONFIG_NU_PKG_USING_ILI9341_SPI=y -# CONFIG_NU_PKG_USING_ILI9341_EBI is not set -CONFIG_NU_PKG_USING_ILI9341_SPI_CLK_FREQ=48000000 -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=240 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 +# CONFIG_NU_PKG_USING_ILI9341 is not set # CONFIG_NU_PKG_USING_SSD1963 is not set # CONFIG_NU_PKG_USING_FSA506 is not set # CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -CONFIG_NU_PKG_USING_ADC_TOUCH_SW=y +# CONFIG_NU_PKG_USING_ADC_TOUCH is not set # CONFIG_NU_PKG_USING_SPINAND is not set +# end of Nuvoton Packages Config +# end of Hardware Drivers Config diff --git a/bsp/nuvoton/numaker-m3334ki/Kconfig b/bsp/nuvoton/numaker-m3334ki/Kconfig new file mode 100644 index 00000000000..8e96d9b51be --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/Kconfig @@ -0,0 +1,14 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +# you can change the RTT_ROOT default "../../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +source "$(BSP_DIR)/board/Kconfig" diff --git a/bsp/nuvoton/numaker-m3334ki/README.md b/bsp/nuvoton/numaker-m3334ki/README.md new file mode 100644 index 00000000000..799a226f551 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/README.md @@ -0,0 +1,61 @@ +# NuMaker-M3334KI + +## 1. Introduction +The NuMaker M3334KI is a microcontroller platform with comprehensive peripheral integration specially developed by Nuvoton. The NuMaker-M3334KI is based on the NuMicro® M3331 series MCU with ARM® -Cortex®-M33 core. + + +### 1.1 MCU specification + +| | Features | +| -- | -- | +| MCU | 32-bit Arm CM33 M3334KIGAE | +| Operation frequency | 180 MHz | +| Embedded Flash size | 512KB, Dual Bank | +| SRAM size | 320 kB | + +### 1.2 Interface + +| Interface | +| -- | +| Arduino UNO | +| USB 2.0 Type-C ports | + +### 1.3 On-board devices (NuMaker-M3334KI V2.0) + +| Device | Description | Driver supporting status | +| -- | -- | -- | +| LED | on-board | Supported | +| HSUSB | DRP (HOST or Device Role) | Supported | + +### 1.4 Extended boards + +| Board | Description | Driver supporting status | +| -- | -- | -- | +| NUTFT | v1.3 | Supported | +| NUFUN | v2.0 | Coming soon | + +## 2. Supported compiler + +Support GCC, MDK5 IDE/compilers. More information of these compiler version as following: + +| IDE/Compiler | Tested version | +| ---------- | ------------------------------------ | +| MDK5 | 5.40 | +| GCC | Arm Embedded Toolchain 10.3-2021.10 (Env 1.3.5 embedded version)| + +Notice: +(1) Please install Nu-Link_Keil_Driver for development. + +## 3. Program firmware + +### Step 1 + +At first, you need to configure ICESW2 switch on the NuMaker-M2L31KI board. Set the four switches to ‘ON’ position. After the configuration is done, connect the NuMaker-M2L31KI board and your computer using the USB Type-C cable. After that, window manager will show a ‘NuMicro MCU’ virtual disk. Finally, you will use this virtual disk to burn firmware. + +### Step 2 + +A simple firmware burning method is that you can drag and drop the binary image file to NuMicro MCU virtual disk or copy the binary file to NuMicro MCU disk to burn firmware. + +## 4. Test + +You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager. diff --git a/bsp/nuvoton/numaker-m3334ki/SConscript b/bsp/nuvoton/numaker-m3334ki/SConscript new file mode 100644 index 00000000000..fe0ae941ae9 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/numaker-m3334ki/SConstruct b/bsp/nuvoton/numaker-m3334ki/SConstruct new file mode 100644 index 00000000000..f54828241c9 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +nuvoton_library = 'm3331' +rtconfig.BSP_LIBRARY_TYPE = nuvoton_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript'))) + +# include nu_pkgs +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton/numaker-m3334ki/Template.uvprojx b/bsp/nuvoton/numaker-m3334ki/Template.uvprojx new file mode 100644 index 00000000000..8d38105a3f6 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/Template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m3331 + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + M3334KIGAE + Nuvoton + Nuvoton.NuMicroM33_DFP.1.0.1 + https://github.com/OpenNuvoton/cmsis-packs/raw/master/Nuvoton_DFP/ + IRAM(0x20000000,0x60000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC4000 -FN3 -FF0M3331_AP_512 -FS00 -FL080000 -FF1M3331_LD_8 -FS1F100000 -FL12000 -FF2M3331_NS -FS210000000 -FL280000 -FP0($$Device:M3334KIGAE$Flash\M3331_AP_512.FLM) -FP1($$Device:M3334KIGAE$Flash\M3331_LD_8.FLM) -FP2($$Device:M3334KIGAE$Flash\M3331_NS.FLM)) + 0 + $$Device:M3334KIGAE$Device\M3331\Include\m3331.h + + + + + + + + + + $$Device:M3334KIGAE$SVD\Nuvoton\M3331.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf --bin ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.bin" + fromelf --text -c ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.txt" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 3 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\linking_scripts\M3331.sct + + + --map --first='startup_M3331.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler + + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/numaker-m3334ki/applications/SConscript b/bsp/nuvoton/numaker-m3334ki/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nuvoton/numaker-m3334ki/applications/lv_conf.h b/bsp/nuvoton/numaker-m3334ki/applications/lv_conf.h new file mode 100644 index 00000000000..b5b3a672875 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/applications/lv_conf.h @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file lv_conf.h + * @brief lvgl configuration + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef LV_CONF_H +#define LV_CONF_H + +#include "rtconfig.h" + +#define LV_COLOR_DEPTH BSP_LCD_BPP +#define LV_HOR_RES_MAX BSP_LCD_WIDTH +#define LV_VER_RES_MAX BSP_LCD_HEIGHT + +#define LV_FONT_MONTSERRAT_12 1 +#define LV_FONT_MONTSERRAT_16 1 + +#define CONFIG_LV_MEM_SIZE (64*1024) +#define CONFIG_LV_CACHE_DEF_SIZE (64*1024) + +/* Please comment LV_USE_DEMO_MUSIC declaration before un-comment below */ +//#define LV_USE_DEMO_WIDGETS 1 + +/* For V8 definitions */ +//#define LV_USE_PERF_MONITOR 1 + +/* For V9 definitions */ +#define LV_USE_SYSMON 1 +#define LV_USE_PERF_MONITOR 1 +#define LV_USE_LOG 0 + +#if 1 + + //LV_CONF_MINIMAL + + #undef LV_USE_DEMO_WIDGETS + #undef LV_USE_SYSMON + #undef LV_USE_PERF_MONITOR + #undef LV_USE_LOG + + #define LV_USE_THEME_DEFAULT 1 + #define LV_WIDGETS_HAS_DEFAULT_VALUE 0 + #define LV_USE_ANIMIMG 0 + #define LV_USE_ARC 1 + #define LV_USE_BAR 1 + #define LV_USE_BUTTON 1 + #define LV_USE_BUTTONMATRIX 1 + #define LV_USE_CALENDAR 0 + #define LV_USE_CALENDAR_HEADER_ARROW 0 + #define LV_USE_CALENDAR_HEADER_DROPDOWN 0 + #define LV_USE_CALENDAR_CHINESE 0 + #define LV_USE_CANVAS 0 + #define LV_USE_CHART 0 + #define LV_USE_CHECKBOX 0 + #define LV_USE_DROPDOWN 0 + #define LV_USE_IMAGE 1 + #define LV_USE_IMAGEBUTTON 0 + #define LV_USE_KEYBOARD 0 + #define LV_USE_LABEL 1 + #define LV_LABEL_TEXT_SELECTION 0 + #define LV_LABEL_LONG_TXT_HINT 0 + #define LV_LABEL_WAIT_CHAR_COUNT 0 + #define LV_USE_LED 1 + #define LV_USE_LINE 1 + #define LV_USE_LIST 0 + #define LV_USE_MENU 0 + #define LV_USE_MSGBOX 0 + #define LV_USE_ROLLER 0 + #define LV_USE_SCALE 1 + #define LV_USE_SLIDER 1 + #define LV_USE_SPAN 0 + #define LV_USE_SPINBOX 0 + #define LV_USE_SPINNER 0 + #define LV_USE_SWITCH 1 + #define LV_USE_TEXTAREA 0 + #define LV_USE_TABLE 0 + #define LV_USE_TABVIEW 0 + #define LV_USE_TILEVIEW 0 + #define LV_USE_WIN 0 + #define LV_DRAW_SW_SUPPORT_RGB565 1 + #define LV_DRAW_SW_SUPPORT_RGB565A8 0 + #define LV_DRAW_SW_SUPPORT_RGB888 1 + #define LV_DRAW_SW_SUPPORT_XRGB8888 0 + #define LV_DRAW_SW_SUPPORT_ARGB8888 1 + #define LV_DRAW_SW_SUPPORT_L8 0 + #define LV_DRAW_SW_SUPPORT_AL88 0 + #define LV_DRAW_SW_SUPPORT_A8 0 + #define LV_DRAW_SW_SUPPORT_I1 0 + #define LV_DRAW_SW_COMPLEX 1 + +#endif + +#if LV_USE_LOG == 1 + #define LV_LOG_LEVEL LV_LOG_LEVEL_TRACE + //#define LV_LOG_LEVEL LV_LOG_LEVEL_INFO + //#define LV_LOG_LEVEL LV_LOG_LEVEL_WARN + //#define LV_LOG_LEVEL LV_LOG_LEVEL_ERROR + //#define LV_LOG_LEVEL LV_LOG_LEVEL_USER + //#define LV_LOG_LEVEL LV_LOG_LEVEL_NONE +#endif + +#endif /* LV_CONF_H */ diff --git a/bsp/nuvoton/numaker-m3334ki/applications/main.c b/bsp/nuvoton/numaker-m3334ki/applications/main.c new file mode 100644 index 00000000000..18188570f99 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/applications/main.c @@ -0,0 +1,32 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +******************************************************************************/ + +#include +#include +#include "drv_gpio.h" + +/* defined the LEDR pin: PC14 */ +#define LEDR NU_GET_PININDEX(NU_PC, 14) + +int main(int argc, char **argv) +{ +#if defined(RT_USING_PIN) + /* set LEDR pin mode to output */ + rt_pin_mode(LEDR, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LEDR, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LEDR, PIN_LOW); + rt_thread_mdelay(500); + } +#endif + + return 0; +} diff --git a/bsp/nuvoton/numaker-m3334ki/applications/mnt.c b/bsp/nuvoton/numaker-m3334ki/applications/mnt.c new file mode 100644 index 00000000000..9684935dc04 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/applications/mnt.c @@ -0,0 +1,70 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +******************************************************************************/ + +#include + +#if defined(RT_USING_DFS) + +#define LOG_TAG "mnt" +#define DBG_ENABLE +#define DBG_SECTION_NAME "mnt" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +#include +#include +#include +#include +#include +#include + +#if defined(RT_USING_FAL) + #include +#endif + +#ifdef RT_USING_DFS_MNTTABLE +const struct dfs_mount_tbl mount_table[] = +{ + { "sd0p0", "/", "elm", 0, RT_NULL }, + {0}, +}; +#endif + +#if defined(BOARD_USING_QSPI_FLASH) +#define PARTITION_NAME_FILESYSTEM "filesystem" +#define MOUNT_POINT_SPIFLASH0 "/" +int mnt_init_spiflash0(void) +{ +#if defined(RT_USING_FAL) + extern int fal_init_check(void); + if (!fal_init_check()) + fal_init(); +#endif + struct rt_device *psNorFlash = fal_blk_device_create(PARTITION_NAME_FILESYSTEM); + if (!psNorFlash) + { + rt_kprintf("Failed to create block device for %s.\n", PARTITION_NAME_FILESYSTEM); + goto exit_mnt_init_spiflash0; + } + else if (dfs_mount(psNorFlash->parent.name, MOUNT_POINT_SPIFLASH0, "elm", 0, 0) != 0) + { + rt_kprintf("Failed to mount elm on %s.\n", MOUNT_POINT_SPIFLASH0); + rt_kprintf("Try to execute 'mkfs -t elm %s' first, then reboot.\n", PARTITION_NAME_FILESYSTEM); + goto exit_mnt_init_spiflash0; + } + rt_kprintf("mount %s with elmfat type: ok\n", PARTITION_NAME_FILESYSTEM); + +exit_mnt_init_spiflash0: + + return 0; +} +//INIT_APP_EXPORT(mnt_init_spiflash0); +#endif + +#endif /* defined(RT_USING_DFS) */ diff --git a/bsp/nuvoton/numaker-m3334ki/applications/pm_test.c b/bsp/nuvoton/numaker-m3334ki/applications/pm_test.c new file mode 100644 index 00000000000..ad515a77803 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/applications/pm_test.c @@ -0,0 +1,251 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +******************************************************************************/ +#if defined(BSP_USING_CLK) + +#include +#include +#include +#include "drv_gpio.h" +#include "NuMicro.h" + +#if defined(RT_USING_PIN) + +/* defined the BTN0 pin: PB0 */ +#define BTN0 NU_GET_PININDEX(NU_PB, 0) + +/* defined the BTN1 pin: PB1 */ +#define BTN1 NU_GET_PININDEX(NU_PB, 1) + +static void nu_btn0_event_cb(void *args) +{ + uint32_t u32PinIdxValue = (uint32_t)args; + static int32_t i32Count = 0; + + rt_kprintf("%d pressed!!(%d)\n", u32PinIdxValue, i32Count); + +#if defined(RT_USING_PM) + if (i32Count++ > 4) + { + rt_kprintf("Back to normal\n"); + + /* Request normal mode */ + rt_pm_request(PM_SLEEP_MODE_NONE); + + i32Count = 0; + } +#endif +} + +#if defined(RT_USING_PM) + +void pm_sleep_before(rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_STANDBY: + /* FALLTHROUGH */ + case PM_SLEEP_MODE_SHUTDOWN: + rt_kprintf("ZzZzZ\n"); + break; + + default: + return; + } +} + +void pm_get_wksrc(void) +{ + uint32_t u32RegRstsrc; + + if ((u32RegRstsrc = CLK_GetPMUWKSrc()) != 0) + { + /* Release I/O hold status after wake-up from Standby Power-down Mode (SPD) */ + CLK->IOPDCTL = 1; + + rt_kprintf("CLK_PMUSTS: 0x%08X\n", u32RegRstsrc); + + if ((u32RegRstsrc & CLK_PMUSTS_ACMPWK0_Msk) != 0) + rt_kprintf("Wake-up source is ACMP.\n"); + if ((u32RegRstsrc & CLK_PMUSTS_RTCWK_Msk) != 0) + rt_kprintf("Wake-up source is RTC.\n"); + if ((u32RegRstsrc & CLK_PMUSTS_TMRWK_Msk) != 0) + rt_kprintf("Wake-up source is Wake-up Timer.\n"); + if ((u32RegRstsrc & CLK_PMUSTS_GPCWK0_Msk) != 0) + rt_kprintf("Wake-up source is GPIO PortC.\n"); + if ((u32RegRstsrc & CLK_PMUSTS_LVRWK_Msk) != 0) + rt_kprintf("Wake-up source is LVR.\n"); + if ((u32RegRstsrc & CLK_PMUSTS_BODWK_Msk) != 0) + rt_kprintf("Wake-up source is BOD.\n"); + + /* Clear Power Manager Status register */ + CLK->PMUSTS = CLK_PMUSTS_CLRWK_Msk; + } +} + +void pm_set_wksrc(rt_uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_STANDBY: + /* FALLTHROUGH */ + case PM_SLEEP_MODE_SHUTDOWN: + /* Enable RTC wake-up. */ + CLK_ENABLE_RTCWK(); + + /* Configure GPIO as input mode */ + //GPIO_SetMode(PA, BIT13, GPIO_MODE_INPUT); + //GPIO_SetMode(PC, BIT0, GPIO_MODE_INPUT); + + /* GPIO SPD Power-down Wake-up Pin Select */ + //CLK_EnableSPDWKPin(0, 13, CLK_SPDWKPIN_RISING, CLK_SPDWKPIN_DEBOUNCEDIS); + //CLK_EnableSPDWKPin(2, 0, CLK_SPDWKPIN_RISING, CLK_SPDWKPIN_DEBOUNCEDIS); + + break; + default: + return; + } +} + +static int pm_cko_init(void) +{ + rt_kprintf("Enable CLK0 function to observe HCLK/4 waveform.\n"); + + CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 3, 0); + SYS->GPC_MFP3 = (SYS->GPC_MFP3 & ~SYS_GPC_MFP3_PC13MFP_Msk) | SYS_GPC_MFP3_PC13MFP_CLKO; + + return 0; +} +INIT_APP_EXPORT(pm_cko_init); +#endif + +#if defined(BOARD_USING_NUTFT_BUTTON) +static int pm_test_pin(void) +{ + /* Configure BTN0/BTN1 as Input mode and enable interrupt by rising edge trigger */ + rt_pin_mode(BTN0, PIN_MODE_INPUT); + rt_pin_attach_irq(BTN0, PIN_IRQ_MODE_FALLING, nu_btn0_event_cb, (void *)BTN0); + rt_pin_irq_enable(BTN0, PIN_IRQ_ENABLE); + + rt_pin_mode(BTN1, PIN_MODE_INPUT); + rt_pin_attach_irq(BTN1, PIN_IRQ_MODE_FALLING, nu_btn0_event_cb, (void *)BTN1); + rt_pin_irq_enable(BTN1, PIN_IRQ_ENABLE); + + /* Enable interrupt de-bounce function and select de-bounce sampling cycle time is 1024 clocks of LIRC clock */ + GPIO_SET_DEBOUNCE_TIME(PB, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_1024); + GPIO_ENABLE_DEBOUNCE(PB, BIT2 | BIT3); + + return 0; +} +INIT_APP_EXPORT(pm_test_pin); +#endif +#endif + +#if defined(RT_USING_ALARM) + +#define ENCODE_TM(tm, year, mon, mday, hour, min, sec) \ +{ \ + (tm).tm_year = (year) - 1900; \ + (tm).tm_mon = (mon) - 1; \ + (tm).tm_mday = (mday); \ + (tm).tm_hour = (hour); \ + (tm).tm_min = (min); \ + (tm).tm_sec = (sec); \ +} + +static volatile uint32_t bWaitAlarmNotify = 0; +static void rt_alarm_cb(rt_alarm_t alarm, time_t timestamp) +{ +#if defined(RT_USING_PM) + /* Request normal mode */ + rt_pm_request(PM_SLEEP_MODE_NONE); +#endif + + bWaitAlarmNotify = 1; + + rt_kprintf("[%s/%d] alarm=0x%08x, %08x\n", __func__, rt_tick_get(), alarm, timestamp); +} + +static int pm_test_rtc_alarm(void) +{ + struct rt_rtc_wkalarm wkalarm; /* Define RTC wake-up alarm structure */ + struct rt_alarm_setup alarm_setup; /* Define alarm setup structure */ + struct rt_alarm *alarm; /* Define alarm pointer */ + rt_device_t rtc_dev; /* Define RTC device pointer */ + + struct tm tm; /* Define time structure */ + time_t tw = 0; /* Define time variable */ + + /* Find the RTC device */ + if ((rtc_dev = rt_device_find("rtc")) == RT_NULL) + { + rt_kprintf("Can't find rtc device!\n"); /* Print error message if RTC device is not found */ + goto exit_pm_test_rtc_alarm; /* Jump to error handling section */ + } + + /* Clear the alarm_setup.wktime structure and set it to current time */ + rt_memset(&alarm_setup.wktime, RT_ALARM_TM_NOW, sizeof(struct tm)); + + /* Set the current date and time (2024-05-28 15:15:00) */ + ENCODE_TM(tm, 2024, 5, 28, 15, 15, 0); + + /* Set the wake-up date and time (2024-05-28 15:15:10) */ + ENCODE_TM(alarm_setup.wktime, 2024, 5, 28, 15, 15, 10); + + /* Convert the time to time_t format */ + tw = timegm(&tm); + + /* Set the RTC device time */ + rt_device_control(rtc_dev, RT_DEVICE_CTRL_RTC_SET_TIME, &tw); + + /* Set the alarm as one-shot */ + alarm_setup.flag = RT_ALARM_ONESHOT; + + /* Create the alarm */ + alarm = rt_alarm_create(rt_alarm_cb, &alarm_setup); + + /* Initialize the alarm notification flag */ + bWaitAlarmNotify = 0; + + /* Start the alarm and check if it is successful */ + if (alarm && (rt_alarm_start(alarm) == RT_EOK)) + { + rt_kprintf("Sleep 10 seconds for waiting alarm occurred.\n"); + +#if defined(RT_USING_PM) + rt_uint8_t mode = PM_SLEEP_MODE_STANDBY; /* Define power management mode as standby mode */ + //rt_uint8_t mode = PM_SLEEP_MODE_DEEP; /* Define power management mode as deep sleep mode */ + rt_pm_request(mode); /* Request to enter the specified sleep mode */ + + /* Release all power management resources */ + for (int i = (mode - 1); i >= 0; i--) + rt_pm_release_all(i); + + /* Enter idle task to perform pm_sleep */ + rt_thread_mdelay(10); + + /* Now, the system enters deep mode and wakes up from RTC alarm */ +#endif + + /* Wait for notification from the alarm callback */ + while (!bWaitAlarmNotify); + + /* Stop and delete the alarm */ + rt_alarm_stop(alarm); + rt_alarm_delete(alarm); + } + + return 0; + +exit_pm_test_rtc_alarm: + return -1; /* Error handling section, return -1 to indicate failure */ +} + +MSH_CMD_EXPORT(pm_test_rtc_alarm, test rtc alarm); +#endif +#endif + diff --git a/bsp/nuvoton/numaker-m3334ki/board/Kconfig b/bsp/nuvoton/numaker-m3334ki/board/Kconfig new file mode 100644 index 00000000000..8488818e64d --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/Kconfig @@ -0,0 +1,82 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + source "$BSP_DIR/../libraries/m3331/rtt_port/Kconfig" + endmenu + + menu "On-board Peripheral Drivers" + + config BOARD_USING_NULINKME + bool "Enable UART0 for RTT Console.(uart0)" + select BSP_USING_UART + select BSP_USING_UART0 + default y + + config BSP_USING_CUSTOM_LOADER + bool "Enable Custom Loader for Swapping Flash Bank." + select BSP_USING_RMC + + choice + prompt "Select HSUSB Ports" + + config BOARD_USING_HSUSBD + select BSP_USING_HSUSBD + bool "Enable HSUSBD" + help + Choose this option if you need HSUSBD function mode. + + config BOARD_USING_HSUSBH + select BSP_USING_HSUSBH + bool "Enable HSUSBH" + help + Choose this option if you need HSUSBH function mode. + + config BOARD_USING_USB_OTG + select BSP_USING_OTG + bool "Enable HSUSB OTG" + help + Choose this option if you need HSUSB Device, Host and H/W OTG function. + + config BOARD_USING_USB_SWOTG + select BSP_USING_HSUSBH + select BSP_USING_HSUSBD + select RT_USING_PIN + select RT_USING_ADC + select BSP_USING_EADC0 + bool "Enable HSUSB S/W OTG" + help + Choose this option if you need HSUSB Device, Host and S/W OTG function. + + config BOARD_USING_USB_NONE + select BSP_USING_USB_NONE + bool "Disable HSUSB port" + help + Choose this option if you need not USB function. + endchoice + + + endmenu + + menu "Board extended module drivers" + choice + prompt "Select On-board Module" + config BOARD_USING_NONE + bool "None" + config BOARD_USING_NUFUN + bool "NuFUN V2.0" + config BOARD_USING_NUTFT + bool "NuTFT V1.3" + endchoice + + if BOARD_USING_NUFUN + source "$BSP_DIR/board/Kconfig_Board_NUFUN" + endif + + if BOARD_USING_NUTFT + source "$BSP_DIR/board/Kconfig_Board_NUTFT" + endif + endmenu + + source "$BSP_DIR/../libraries/nu_packages/Kconfig" + +endmenu diff --git a/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUFUN b/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUFUN new file mode 100644 index 00000000000..88087aac004 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUFUN @@ -0,0 +1,143 @@ + config BOARD_USING_QSPI_FLASH + bool "Enable QSPI Flash(Over QSPI0)" + select BSP_USING_SPI + select BSP_USING_QSPI + select BSP_USING_QSPI0 + select RT_USING_FAL + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + select FAL_USING_SFUD_PORT + default y + + config BOARD_USING_NUFUN_I2C_EEPROM + bool "Enable I2C EEPROM(Over I2C0)" + select BSP_USING_I2C + select BSP_USING_I2C0 + select RT_USING_I2C + select PKG_USING_AT24CXX + default y + + config BOARD_USING_NUFUN_I2C_TEMPERATURE_SENSOR + bool "Enable I2C TEMPERATURE SENSOR(Over I2C2)" + select BSP_USING_I2C + select BSP_USING_I2C2 + select RT_USING_I2C + select NU_PKG_USING_TMP112 + default y + + config BOARD_USING_NUFUN_I2C_3AXIS_SENSOR + bool "Enable I2C 3-AXIS SENSOR(Over I2C2)" + select BSP_USING_I2C + select BSP_USING_I2C2 + select RT_USING_I2C + select NU_PKG_USING_LIS3DH + default y + + config BOARD_USING_NUFUN_I3C_BAROMETER_SENSOR + bool "Enable I3C Barometer SENSOR(Over I3C0)" + select BSP_USING_I3C0 + select NU_PKG_USING_LPS22HH + default y + + config BOARD_USING_NUFUN_PWM_RGB_LED + bool "Enable BPWM RGB LED(Over BPWM0, CH0~CH2)" + select BSP_USING_BPWM + select BSP_USING_BPWM0 + select RT_USING_PWM + default y + + config BOARD_USING_NUFUN_LLSI_RGB_LED + bool "Enable LLSI RGB LED(Over LLSI0)" + select BSP_USING_LLSI + select BSP_USING_LLSI0 + default y + + config BOARD_USING_LCD_ILI9341 + bool "Enable LCM(Over SPI1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select NU_PKG_USING_ILI9341 + select NU_PKG_USING_ILI9341_SPI + select NU_PKG_ILI9341_HORIZONTAL + default y + + if BOARD_USING_LCD_ILI9341 + config BOARD_USING_ILI9341_PIN_BACKLIGHT + hex "Specify the pin index of backlight pin index" + range 0x0 0x7F + default 0x7B + + config BOARD_USING_ILI9341_PIN_RESET + hex "Specify the pin index of reset pin index" + range 0x0 0x7F + default 0x3E + + config BOARD_USING_ILI9341_PIN_DC + hex "Specify the pin index of data&command switching" + range 0x0 0x7F + default 0x7A + endif + + config BOARD_USING_NUFUN_ADC_TOUCH + bool "Enable ADC Touching(Over EADC0)" + select BSP_USING_EADC + select BSP_USING_EADC0 + select RT_USING_TOUCH + select NU_PKG_USING_ADC_TOUCH + select NU_PKG_USING_ADC_TOUCH_SW + default y + + config BOARD_USING_EQEI_MAGNETIC_ENCODER + bool "Enable Magnetic Encoder (Over EQEI0)" + select BSP_USING_EQEI + select BSP_USING_EQEI0 + select RT_USING_PULSE_ENCODER + default y + + config BOARD_USING_NUFUN_FAN + bool "Enable FAN (Over EPWM1.CH0)" + select BSP_USING_EPWM + select BSP_USING_EPWM1 + select RT_USING_PWM + default y + + config BOARD_USING_NUFUN_LED + bool "Enable Status LEDs" + select RT_USING_PIN + default y + + config BOARD_USING_NUFUN_BUTTON + bool "Enable BUTTONs" + select RT_USING_PIN + default y + + config BOARD_USING_SDCARD + bool "Enable SD Card(Over SD0)" + select BSP_USING_SDH + select BSP_USING_SDH0 + select RT_USING_SDIO + default y + + config BOARD_USING_CANFD + bool "Enable CANFD port(Over CANFD0)" + select BSP_USING_CANFD + select BSP_USING_CANFD0 + select RT_USING_CAN + default y + + config BOARD_USING_RS485 + bool "Enable RS-485 port(Over UART2)" + select BSP_USING_UART + select BSP_USING_UART2 + select RT_USING_SERIAL + default y + + config BOARD_USING_AUDIO_CODEC + bool "Enable Audio Codec(Over I2S0)" + select BSP_USING_I2S + select BSP_USING_I2S0 + select BSP_USING_I2C + select BSP_USING_I2C1 + select RT_USING_AUDIO + select NU_PKG_USING_NAU8822 + default y diff --git a/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUTFT b/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUTFT new file mode 100644 index 00000000000..04e534da8b8 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/Kconfig_Board_NUTFT @@ -0,0 +1,49 @@ + config BOARD_USING_LCD_ILI9341 + bool "Enable LCM(Over SPI2)" + select BSP_USING_SPI + select BSP_USING_SPI2 + select NU_PKG_USING_ILI9341 + select NU_PKG_USING_ILI9341_SPI + #select NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER + select NU_PKG_ILI9341_HORIZONTAL + default y + + if BOARD_USING_LCD_ILI9341 + config BOARD_USING_ILI9341_PIN_BACKLIGHT + hex "Specify the pin index of backlight pin index" + range 0x0 0x7F + default 0x15 + + config BOARD_USING_ILI9341_PIN_RESET + hex "Specify the pin index of reset pin index" + range 0x0 0x7F + default 0x13 + + config BOARD_USING_ILI9341_PIN_DC + hex "Specify the pin index of data&command switching" + range 0x0 0x7F + default 0x12 + endif + + config BOARD_USING_NUTFT_ADC_TOUCH + bool "Enable ADC Touching(Over EADC0)" + select BSP_USING_EADC + select BSP_USING_EADC0 + select RT_USING_TOUCH + select NU_PKG_USING_ADC_TOUCH + select NU_PKG_USING_ADC_TOUCH_SW + default y + + config BOARD_USING_QSPI_FLASH + bool "Enable QSPI Flash(Over QSPI0)" + select BSP_USING_SPI + select BSP_USING_QSPI + select BSP_USING_QSPI0 + select RT_USING_FAL + select RT_USING_SFUD + default y + + config BOARD_USING_NUTFT_BUTTON + bool "Enable BUTTON(UNO_A4, UNO_A5)" + select RT_USING_PIN + default y diff --git a/bsp/nuvoton/numaker-m3334ki/board/NTFUN_board_dev.c b/bsp/nuvoton/numaker-m3334ki/board/NTFUN_board_dev.c new file mode 100644 index 00000000000..e51787ff86c --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NTFUN_board_dev.c @@ -0,0 +1,187 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include "NuMicro.h" +#include "drv_common.h" + +#if defined(BOARD_USING_NUFUN) + +#if defined(BOARD_USING_QSPI_FLASH) +#include "qspinor.h" + +static int rt_hw_spiflash_init(void) +{ + /* Here, we use Dual I/O to drive the SPI flash by default. */ + /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK) + return -1; + +#if defined(RT_USING_SFUD) + if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL) + { + return -(RT_ERROR); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_spiflash_init); +#endif /* BOARD_USING_QSPI_FLASH */ + +#if defined(BOARD_USING_NUFUN_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) + +#include "adc_touch.h" +#include "touch_sw.h" + +S_CALIBRATION_MATRIX g_sCalMat = { 36, 6227, -2817292, 4936, -37, -1969986, 65536 }; + +static void tp_switch_to_analog(rt_base_t pin) +{ + GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin)); + + nu_pin_func(pin, (1 << NU_MFP_POS(NU_GET_PINS(pin)))); + + /* Disable the digital input path to avoid the leakage current. */ + /* Disable digital path on these ADC pin */ + GPIO_DISABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin))); +} + +static void tp_switch_to_digital(rt_base_t pin) +{ + GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin)); + + nu_pin_func(pin, 0); + + /* Enable digital path on these ADC pins */ + GPIO_ENABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin))); +} + +static S_TOUCH_SW sADCTP = +{ + .adc_name = "eadc0", + .i32ADCChnYU = 4, + .i32ADCChnXR = 3, + .pin = + { + NU_GET_PININDEX(NU_PB, 5), // XL + NU_GET_PININDEX(NU_PB, 4), // YU + NU_GET_PININDEX(NU_PB, 3), // XR + NU_GET_PININDEX(NU_PB, 2), // YD + }, + .switch_to_analog = tp_switch_to_analog, + .switch_to_digital = tp_switch_to_digital, +}; + +#endif /* defined(BOARD_USING_NUFUN_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) */ + +#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI) + +#include +#if defined(PKG_USING_GUIENGINE) + #include +#endif + +int rt_hw_ili9341_port(void) +{ + if (rt_hw_lcd_ili9341_spi_init("spi1", (void *)RT_NULL) != RT_EOK) + return -1; + + rt_hw_lcd_ili9341_init(); + +#if defined(PKG_USING_GUIENGINE) + rt_device_t lcd_ili9341; + lcd_ili9341 = rt_device_find("lcd"); + if (lcd_ili9341) + { + rtgui_graphic_set_device(lcd_ili9341); + } +#endif + +#if defined(BOARD_USING_NUFUN_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) + rt_err_t nu_adc_touch_sw_register(S_TOUCH_SW * psTouchSW); + nu_adc_touch_sw_register(&sADCTP); +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_ili9341_port); +#endif /* defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI) */ + +#if defined(BOARD_USING_AUDIO_CODEC) && defined(NU_PKG_USING_NAU8822) +#include "acodec_nau8822.h" +S_NU_NAU8822_CONFIG sCodecConfig = +{ + .i2c_bus_name = "i2c1", + .i2s_bus_name = "sound0", + .pin_phonejack_en = NU_GET_PININDEX(NU_PD, 11), + .pin_phonejack_det = NU_GET_PININDEX(NU_PD, 10), +}; + +int rt_hw_nau8822_port(void) +{ + if (nu_hw_nau8822_init(&sCodecConfig) != RT_EOK) + return -1; + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_nau8822_port); +#endif /* BOARD_USING_AUDIO_CODEC */ + +#if defined(BOARD_USING_NUFUN_I2C_TEMPERATURE_SENSOR) + +#include "sensor_tmp112.h" + +int rt_hw_tmp112_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i2c2"; + cfg.irq_pin.pin = RT_PIN_NONE; + + return rt_hw_tmp112_init("tmp112", &cfg); +} +INIT_ENV_EXPORT(rt_hw_tmp112_port); +#endif /* BOARD_USING_NUFUN_I2C_TEMPERATURE_SENSOR */ + +#if defined(BOARD_USING_NUFUN_I2C_3AXIS_SENSOR) && defined(NU_PKG_USING_LIS3DH) + +#include "st_lis3dh_sensor_v1.h" + +int rt_hw_lis3dh_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i2c2"; + cfg.irq_pin.pin = RT_PIN_NONE; + + return rt_hw_lis3dh_init("lis3dh", &cfg); +} +INIT_ENV_EXPORT(rt_hw_lis3dh_port); +#endif /* BOARD_USING_NUFUN_I2C_TEMPERATURE_SENSOR */ + +#if defined(BOARD_USING_NUFUN_I3C_BAROMETER_SENSOR) && defined(NU_PKG_USING_LPS22HH) + +#include "st_lps22hh_sensor_v1.h" + +int rt_hw_lps22hh_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = "i3c0"; + cfg.irq_pin.pin = RT_PIN_NONE; + + return rt_hw_lps22hh_init("lps22hh", &cfg); +} +INIT_ENV_EXPORT(rt_hw_lps22hh_port); +#endif /* BOARD_USING_NUFUN_I2C_TEMPERATURE_SENSOR */ + +#endif /* defined(BOARD_USING_NUFUN) */ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NUTFT_board_dev.c b/bsp/nuvoton/numaker-m3334ki/board/NUTFT_board_dev.c new file mode 100644 index 00000000000..1ef4208c7a1 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NUTFT_board_dev.c @@ -0,0 +1,117 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include +#include "NuMicro.h" +#include "drv_common.h" + +#if defined(BOARD_USING_NUTFT) + +#if defined(BOARD_USING_QSPI_FLASH) +#include "qspinor.h" +static int rt_hw_spiflash_init(void) +{ + /* Here, we use Dual I/O to drive the SPI flash by default. */ + /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK) + return -1; + +#if defined(RT_USING_SFUD) + if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL) + { + return -(RT_ERROR); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_spiflash_init); +#endif /* BOARD_USING_QSPI_FLASH */ + +#if defined(BOARD_USING_NUTFT_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) + +#include "adc_touch.h" +#include "touch_sw.h" + +S_CALIBRATION_MATRIX g_sCalMat = { 36, 6227, -2817292, 4936, -37, -1969986, 65536 }; + +static void tp_switch_to_analog(rt_base_t pin) +{ + GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin)); + + nu_pin_func(pin, (1 << NU_MFP_POS(NU_GET_PINS(pin)))); + + /* Disable the digital input path to avoid the leakage current. */ + /* Disable digital path on these ADC pin */ + GPIO_DISABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin))); +} + +static void tp_switch_to_digital(rt_base_t pin) +{ + GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin)); + + nu_pin_func(pin, 0); + + /* Enable digital path on these ADC pins */ + GPIO_ENABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin))); +} + +static S_TOUCH_SW sADCTP = +{ + .adc_name = "eadc0", + .i32ADCChnYU = 14, + .i32ADCChnXR = 9, + .pin = + { + NU_GET_PININDEX(NU_PB, 15), // XL + NU_GET_PININDEX(NU_PB, 14), // YU + NU_GET_PININDEX(NU_PB, 9), // XR + NU_GET_PININDEX(NU_PB, 8), // YD + }, + .switch_to_analog = tp_switch_to_analog, + .switch_to_digital = tp_switch_to_digital, +}; + +#endif /* defined(BOARD_USING_NUTFT_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) */ + +#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI) + +#include +#if defined(PKG_USING_GUIENGINE) + #include +#endif + +int rt_hw_ili9341_port(void) +{ + if (rt_hw_lcd_ili9341_spi_init("spi2", (void *)RT_NULL) != RT_EOK) + return -1; + + rt_hw_lcd_ili9341_init(); + +#if defined(PKG_USING_GUIENGINE) + rt_device_t lcd_ili9341; + lcd_ili9341 = rt_device_find("lcd"); + if (lcd_ili9341) + { + rtgui_graphic_set_device(lcd_ili9341); + } +#endif + +#if defined(BOARD_USING_NUTFT_ADC_TOUCH) && defined(NU_PKG_USING_ADC_TOUCH_SW) + nu_adc_touch_sw_register(&sADCTP); +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_ili9341_port); +#endif /* defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI) */ + +#endif /* defined(BOARD_USING_NUTFT) */ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/M3334KIGAE(LQFP128).ncfg b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/M3334KIGAE(LQFP128).ncfg new file mode 100644 index 00000000000..ff53fa7e6db --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/M3334KIGAE(LQFP128).ncfg @@ -0,0 +1,188 @@ +/**************************************************************************** + * @file M3334KIGAE(LQFP128).ncfg + * @version v1.35.3 + * @Date Mon Oct 27 2025 19:42:34 GMT+0800 (Taipei Standard Time) + * @brief NuMicro config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2025 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M3334KIGAE(LQFP128) +Pin1:EPWM0_CH0 +Pin2:PB.4 +Pin3:PB.3 +Pin4:PB.2 +Pin5:PC.12 +Pin6:PC.11 +Pin7:PC.10 +Pin8:I3C0_PUPEN +Pin9:I3C0_SCL +Pin10:I3C0_SDA +Pin11:VSS +Pin12:VDD +Pin13:I2C2_SCL +Pin14:I2C2_SDA +Pin15:PA.9 +Pin16:PA.8 +Pin17:PC.13 +Pin18:PD.12 +Pin19:PD.11 +Pin20:PD.10 +Pin21:I2C0_SMBAL +Pin22:I2C0_SMBSUS +Pin23:PG.4 +Pin24:PF.11 +Pin25:I2S0_BCLK +Pin26:I2S0_MCLK +Pin27:I2S0_DI +Pin28:I2S0_DO +Pin29:I2S0_LRCK +Pin30:PF.14 +Pin31:PF.5 +Pin32:PF.4 +Pin33:PH.4 +Pin34:PH.5 +Pin35:PH.6 +Pin36:PH.7 +Pin37:PF.3 +Pin38:PF.2 +Pin39:VSS +Pin40:VDD +Pin41:PE.8 +Pin42:PE.9 +Pin43:PE.10 +Pin44:PE.11 +Pin45:PE.12 +Pin46:I2C0_SCL +Pin47:I2C0_SDA +Pin48:PC.7 +Pin49:UART0_nRTS +Pin50:UART0_TXD +Pin51:UART0_RXD +Pin52:VSS +Pin53:VDD +Pin54:LDO_CAP +Pin55:EQEI0_INDEX +Pin56:EQEI0_A +Pin57:EQEI0_B +Pin58:PA.2 +Pin59:PA.1 +Pin60:QSPI0_MOSI0 +Pin61:PF.15 +Pin62:CANFD0_TXD +Pin63:CANFD0_RXD +Pin64:nRESET +Pin65:ICE_DAT +Pin66:ICE_CLK +Pin67:PD.9 +Pin68:PD.8 +Pin69:QSPI0_MISO1 +Pin70:QSPI0_MOSI1 +Pin71:QSPI0_SS +Pin72:QSPI0_CLK +Pin73:QSPI0_MISO0 +Pin74:PC.0 +Pin75:VSS +Pin76:VDD +Pin77:PG.9 +Pin78:PG.10 +Pin79:PG.11 +Pin80:BPWM0_CH2 +Pin81:BPWM0_CH1 +Pin82:BPWM0_CH0 +Pin83:PG.15 +Pin84:SD0_nCD +Pin85:PA.12 +Pin86:PA.13 +Pin87:PA.14 +Pin88:PA.15 +Pin89:HSUSB_VRES +Pin90:HSUSB_VDD33 +Pin91:HSUSB_VBUS +Pin92:HSUSB_D- +Pin93:HSUSB_VSS +Pin94:HSUSB_D+ +Pin95:HSUSB_VDD12_CAP +Pin96:HSUSB_ID +Pin97:SD0_CMD +Pin98:SD0_CLK +Pin99:SD0_DAT3 +Pin100:SD0_DAT2 +Pin101:SD0_DAT1 +Pin102:SD0_DAT0 +Pin103:VSS +Pin104:VDD +Pin105:SPI1_MISO +Pin106:SPI1_MOSI +Pin107:SPI1_CLK +Pin108:SPI1_SS +Pin109:PH.10 +Pin110:PH.11 +Pin111:PD.14 +Pin112:VSS +Pin113:LDO_CAP +Pin114:VDD +Pin115:PC.14 +Pin116:LLSI0_OUT +Pin117:PB.14 +Pin118:PB.13 +Pin119:PB.12 +Pin120:AVDD +Pin121:VREF +Pin122:AVSS +Pin123:PB.11 +Pin124:PB.10 +Pin125:PB.9 +Pin126:PB.8 +Pin127:PB.7 +Pin128:PB.6 +GPIOpin:15 +GPIOpin:14 +GPIOpin:16 +GPIOpin:108 +GPIOpin:109 +GPIOpin:116 +GPIOpin:123 +GPIOpin:122 +GPIOpin:124 +GPIOpin:125 +GPIOpin:126 +GPIOpin:127 +GPIOpin:17 +GPIOpin:110 +GPIOpin:19 +GPIOpin:18 +SYS->GPA_MFP0 = 0x0E000003 +SYS->GPA_MFP1 = 0x07070E0E +SYS->GPA_MFP2 = 0x07070000 +SYS->GPA_MFP3 = 0x00000000 +SYS->GPB_MFP0 = 0x00000E0E +SYS->GPB_MFP1 = 0x00000B00 +SYS->GPB_MFP2 = 0x00000000 +SYS->GPB_MFP3 = 0x10000000 +SYS->GPC_MFP0 = 0x04040400 +SYS->GPC_MFP1 = 0x00070404 +SYS->GPC_MFP2 = 0x00000F04 +SYS->GPC_MFP3 = 0x00000000 +SYS->GPD_MFP2 = 0x00000000 +SYS->GPD_MFP3 = 0x00000300 +SYS->GPE_MFP0 = 0x03030606 +SYS->GPE_MFP1 = 0x03030303 +SYS->GPE_MFP2 = 0x00000000 +SYS->GPE_MFP3 = 0x04040400 +SYS->GPF_MFP0 = 0x00000E0E +SYS->GPF_MFP1 = 0x04040000 +SYS->GPF_MFP2 = 0x00040404 +SYS->GPF_MFP3 = 0x00000000 +SYS->GPG_MFP0 = 0x04040000 +SYS->GPG_MFP1 = 0x00000000 +SYS->GPG_MFP2 = 0x00000000 +SYS->GPG_MFP3 = 0x000C0C0C +SYS->GPH_MFP1 = 0x00000000 +SYS->GPH_MFP2 = 0x00000606 +LockedPins=[] +/*** (C) COPYRIGHT 2013-2025 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.c b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.c new file mode 100644 index 00000000000..c93baf9d252 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version V1.21 + * @Date 2024/4/1-12:06:36 + * @brief NuMicro generated code file + * + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "rtconfig.h" +#include "NuMicro.h" + +#if defined(BOARD_USING_NUTFT) +void expansion_nutft_pin_init(void) +{ +#if defined(BOARD_USING_LCD_ILI9341) + SET_SPI2_SS_PA11(); + SET_SPI2_CLK_PA10(); + SET_SPI2_MISO_PA9(); + SET_SPI2_MOSI_PA8(); + + + SET_GPIO_PB2(); + SET_GPIO_PB3(); + SET_GPIO_PB5(); +#endif + +#if defined(BOARD_USING_NUTFT_ADC_TOUCH) + GPIO_SetMode(PB, BIT4 | BIT5 | BIT6 | BIT7, GPIO_MODE_INPUT); + + /* EADC Analog Pin: UNO_A0, UNO_A1, UNO_A2, UNO_A3 */ + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP3_PB14MFP_Msk | SYS_GPB_MFP3_PB15MFP_Msk); + SYS->GPB_MFP1 |= (SYS_GPB_MFP3_PB14MFP_EADC0_CH14 | SYS_GPB_MFP3_PB15MFP_EADC0_CH15); + SYS->GPB_MFP2 &= ~(SYS_GPB_MFP2_PB9MFP_Msk | SYS_GPB_MFP2_PB8MFP_Msk); + SYS->GPB_MFP2 |= (SYS_GPB_MFP2_PB9MFP_EADC0_CH9 | SYS_GPB_MFP2_PB8MFP_EADC0_CH8); + + /* Disable digital path on these EADC pins */ + GPIO_DISABLE_DIGITAL_PATH(PB, BIT8 | BIT9 | BIT14 | BIT15); +#endif + +#if defined(BOARD_USING_QSPI_FLASH) + SET_QSPI0_MOSI0_PA0(); + SET_QSPI0_MISO0_PA1(); + SET_QSPI0_CLK_PA2(); + SET_QSPI0_SS_PA3(); + SET_QSPI0_MOSI1_PA4(); + SET_QSPI0_MISO1_PA5(); +#endif + +#if defined(BOARD_USING_NUTFT_BUTTON) + SYS->GPB_MFP0 &= ~(SYS_GPB_MFP0_PB0MFP_Msk | SYS_GPB_MFP0_PB1MFP_Msk); + + /* Disable digital path on these ADC pins */ + GPIO_ENABLE_DIGITAL_PATH(PB, BIT0 | BIT1); +#endif + +} +#endif + +void nutool_pincfg_init_sd0(void) +{ + SET_SD0_nCD_PD13(); + SET_SD0_DAT1_PE3(); + SET_SD0_DAT0_PE2(); + SET_SD0_CMD_PE7(); + SET_SD0_CLK_PE6(); + SET_SD0_DAT3_PE5(); + SET_SD0_DAT2_PE4(); + + return; +} + +void nutool_pincfg_deinit_sd0(void) +{ + SET_GPIO_PD13(); + SET_GPIO_PE3(); + SET_GPIO_PE2(); + SET_GPIO_PE7(); + SET_GPIO_PE6(); + SET_GPIO_PE5(); + SET_GPIO_PE4(); +} + +void nutool_pincfg_init_uart0(void) +{ + SET_UART0_RXD_PB12(); + SET_UART0_TXD_PB13(); +} + +void nutool_pincfg_deinit_uart0(void) +{ + SET_GPIO_PB12(); + SET_GPIO_PB13(); +} + +void nutool_pincfg_init_hsusb(void) +{ +} + +void nutool_pincfg_init(void) +{ + /* Vref connect to internal */ + SYS_SetVRef(SYS_VREFCTL_VREF_PIN); + +#if defined(BSP_USING_UART0) + nutool_pincfg_init_uart0(); +#endif + +#if defined(BSP_USING_SDH0) + nutool_pincfg_init_sd0(); +#endif + +#if defined(BOARD_USING_NUTFT) + expansion_nutft_pin_init(); +#else + /* Set PB15 multi-function pin for LLSI0 output */ + SET_LLSI0_OUT_PB15(); + + /* Set PB9 multi-function pin for ELLSI0 output */ + //SET_ELLSI0_OUT_PB9(); + + /* Configure EPWM1 channel 3 pin */ + SET_EPWM1_CH3_PC9(); + + /* Configure BPWM0 channel 0 pin */ + SET_BPWM0_CH0_PA0(); +#endif + + /* HSUSB_VBUS_EN (USB 2.0 VBUS power enable pin) multi-function pin - PB.10 */ + SET_HSUSB_VBUS_EN_PB10(); + + /* HSUSB_VBUS_ST (USB 2.0 over-current detect pin) multi-function pin - PB.11 */ + SET_HSUSB_VBUS_ST_PB11(); + + + return; +} + +void nutool_pincfg_deinit(void) +{ +#if defined(BSP_USING_UART0) + nutool_pincfg_deinit_uart0(); +#endif + +#if defined(BSP_USING_SDH0) + nutool_pincfg_deinit_sd0(); +#endif + + return; +} diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.h b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.h new file mode 100644 index 00000000000..7ba6993fc57 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/V1.0/nutool_pincfg.h @@ -0,0 +1,23 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version V1.21 + * @Date 2020/11/11-12:06:36 + * @brief NuMicro generated code file + * + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.c b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.c new file mode 100644 index 00000000000..c692bba7e2a --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.c @@ -0,0 +1,556 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version v1.35.3 + * @Date Mon Oct 27 2025 19:42:48 GMT+0800 (Taipei Standard Time) + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2025 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:M3334KIGAE(LQFP128) +********************/ + +#include "rtconfig.h" +#include "NuMicro.h" + +#if defined(BOARD_USING_NUFUN) +void nutool_pincfg_init_bpwm0(void) +{ + SYS->GPG_MFP3 &= ~(SYS_GPG_MFP3_PG14MFP_Msk | SYS_GPG_MFP3_PG13MFP_Msk | SYS_GPG_MFP3_PG12MFP_Msk); + SYS->GPG_MFP3 |= (SYS_GPG_MFP3_PG14MFP_BPWM0_CH0 | SYS_GPG_MFP3_PG13MFP_BPWM0_CH1 | SYS_GPG_MFP3_PG12MFP_BPWM0_CH2); + + return; +} + +void nutool_pincfg_deinit_bpwm0(void) +{ + SYS->GPG_MFP3 &= ~(SYS_GPG_MFP3_PG14MFP_Msk | SYS_GPG_MFP3_PG13MFP_Msk | SYS_GPG_MFP3_PG12MFP_Msk); + + return; +} + +void nutool_pincfg_init_canfd0(void) +{ + SYS->GPE_MFP3 &= ~(SYS_GPE_MFP3_PE15MFP_Msk | SYS_GPE_MFP3_PE14MFP_Msk); + SYS->GPE_MFP3 |= (SYS_GPE_MFP3_PE15MFP_CANFD0_RXD | SYS_GPE_MFP3_PE14MFP_CANFD0_TXD); + + return; +} + +void nutool_pincfg_deinit_canfd0(void) +{ + SYS->GPE_MFP3 &= ~(SYS_GPE_MFP3_PE15MFP_Msk | SYS_GPE_MFP3_PE14MFP_Msk); + + return; +} + +void nutool_pincfg_init_epwm1(void) +{ + SYS->GPC_MFP3 &= ~(SYS_GPC_MFP3_PC12MFP_Msk); + SYS->GPC_MFP3 |= (SYS_GPC_MFP3_PC12MFP_EPWM1_CH0); + + return; +} + +void nutool_pincfg_deinit_epwm1(void) +{ + SYS->GPC_MFP3 &= ~(SYS_GPC_MFP3_PC12MFP_Msk); + + return; +} + +void nutool_pincfg_init_eqei0(void) +{ + SYS->GPA_MFP0 &= ~(SYS_GPA_MFP0_PA3MFP_Msk); + SYS->GPA_MFP0 |= (SYS_GPA_MFP0_PA3MFP_EQEI0_B); + SYS->GPA_MFP1 &= ~(SYS_GPA_MFP1_PA4MFP_Msk); + SYS->GPA_MFP1 |= (SYS_GPA_MFP1_PA4MFP_EQEI0_A); + + return; +} + +void nutool_pincfg_deinit_eqei0(void) +{ + SYS->GPA_MFP0 &= ~(SYS_GPA_MFP0_PA3MFP_Msk); + SYS->GPA_MFP1 &= ~(SYS_GPA_MFP1_PA4MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c0(void) +{ + SYS->GPC_MFP2 &= ~(SYS_GPC_MFP2_PC8MFP_Msk); + SYS->GPC_MFP2 |= (SYS_GPC_MFP2_PC8MFP_I2C0_SDA); + SYS->GPE_MFP3 &= ~(SYS_GPE_MFP3_PE13MFP_Msk); + SYS->GPE_MFP3 |= (SYS_GPE_MFP3_PE13MFP_I2C0_SCL); + + return; +} + +void nutool_pincfg_deinit_i2c0(void) +{ + SYS->GPC_MFP2 &= ~(SYS_GPC_MFP2_PC8MFP_Msk); + SYS->GPE_MFP3 &= ~(SYS_GPE_MFP3_PE13MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c1(void) +{ + SYS->GPG_MFP0 &= ~(SYS_GPG_MFP0_PG2MFP_Msk | SYS_GPG_MFP0_PG3MFP_Msk); + SYS->GPG_MFP0 |= (SYS_GPG_MFP0_PG2MFP_I2C1_SCL | SYS_GPG_MFP0_PG3MFP_I2C1_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c1(void) +{ + SYS->GPG_MFP0 &= ~(SYS_GPG_MFP0_PG2MFP_Msk | SYS_GPG_MFP0_PG3MFP_Msk); + + return; +} + + +void nutool_pincfg_init_i2c2(void) +{ + SYS->GPA_MFP2 &= ~(SYS_GPA_MFP2_PA11MFP_Msk | SYS_GPA_MFP2_PA10MFP_Msk); + SYS->GPA_MFP2 |= (SYS_GPA_MFP2_PA11MFP_I2C2_SCL | SYS_GPA_MFP2_PA10MFP_I2C2_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c2(void) +{ + SYS->GPA_MFP2 &= ~(SYS_GPA_MFP2_PA11MFP_Msk | SYS_GPA_MFP2_PA10MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2s0(void) +{ + SYS->GPF_MFP1 &= ~(SYS_GPF_MFP1_PF7MFP_Msk | SYS_GPF_MFP1_PF6MFP_Msk); + SYS->GPF_MFP1 |= (SYS_GPF_MFP1_PF7MFP_I2S0_DO | SYS_GPF_MFP1_PF6MFP_I2S0_LRCK); + SYS->GPF_MFP2 &= ~(SYS_GPF_MFP2_PF10MFP_Msk | SYS_GPF_MFP2_PF9MFP_Msk | SYS_GPF_MFP2_PF8MFP_Msk); + SYS->GPF_MFP2 |= (SYS_GPF_MFP2_PF10MFP_I2S0_BCLK | SYS_GPF_MFP2_PF9MFP_I2S0_MCLK | SYS_GPF_MFP2_PF8MFP_I2S0_DI); + + return; +} + +void nutool_pincfg_deinit_i2s0(void) +{ + SYS->GPF_MFP1 &= ~(SYS_GPF_MFP1_PF7MFP_Msk | SYS_GPF_MFP1_PF6MFP_Msk); + SYS->GPF_MFP2 &= ~(SYS_GPF_MFP2_PF10MFP_Msk | SYS_GPF_MFP2_PF9MFP_Msk | SYS_GPF_MFP2_PF8MFP_Msk); + + return; +} + +void nutool_pincfg_init_i3c0(void) +{ + /* Set multi-function pins for I3C pin */ + GPIO_ENABLE_SCHMITT_TRIGGER(PB, (BIT0 | BIT1)); + SET_I3C0_SDA_PB0(); + SET_I3C0_SCL_PB1(); + + /* Use TYPE-A Resistance Connection */ + PB->PUSEL = ((GPIO_PUSEL_PULL_UP << (0 << 1)) | (GPIO_PUSEL_PULL_UP << (1 << 1))); + SET_I3C0_PUPEN_PC9(); + + return; +} + +void nutool_pincfg_deinit_i3c0(void) +{ + SYS->GPB_MFP0 &= ~(SYS_GPB_MFP0_PB1MFP_Msk | SYS_GPB_MFP0_PB0MFP_Msk); + SYS->GPC_MFP2 &= ~(SYS_GPC_MFP2_PC9MFP_Msk); + + return; +} + +void nutool_pincfg_init_ice(void) +{ + SYS->GPF_MFP0 &= ~(SYS_GPF_MFP0_PF1MFP_Msk | SYS_GPF_MFP0_PF0MFP_Msk); + SYS->GPF_MFP0 |= (SYS_GPF_MFP0_PF1MFP_ICE_CLK | SYS_GPF_MFP0_PF0MFP_ICE_DAT); + + return; +} + +void nutool_pincfg_deinit_ice(void) +{ + SYS->GPF_MFP0 &= ~(SYS_GPF_MFP0_PF1MFP_Msk | SYS_GPF_MFP0_PF0MFP_Msk); + + return; +} + +void nutool_pincfg_init_llsi0(void) +{ + SYS->GPB_MFP3 &= ~(SYS_GPB_MFP3_PB15MFP_Msk); + SYS->GPB_MFP3 |= (SYS_GPB_MFP3_PB15MFP_LLSI0_OUT); + + return; +} + +void nutool_pincfg_deinit_llsi0(void) +{ + SYS->GPB_MFP3 &= ~(SYS_GPB_MFP3_PB15MFP_Msk); + + return; +} + +void nutool_pincfg_init_pa(void) +{ + SYS->GPA_MFP2 &= ~(SYS_GPA_MFP2_PA9MFP_Msk | SYS_GPA_MFP2_PA8MFP_Msk); + SYS->GPA_MFP2 |= (SYS_GPA_MFP2_PA9MFP_GPIO | SYS_GPA_MFP2_PA8MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pa(void) +{ + SYS->GPA_MFP2 &= ~(SYS_GPA_MFP2_PA9MFP_Msk | SYS_GPA_MFP2_PA8MFP_Msk); + + return; +} + +void nutool_pincfg_init_pb(void) +{ + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP1_PB7MFP_Msk | SYS_GPB_MFP1_PB6MFP_Msk); + SYS->GPB_MFP1 |= (SYS_GPB_MFP1_PB7MFP_GPIO | SYS_GPB_MFP1_PB6MFP_GPIO); + SYS->GPB_MFP2 &= ~(SYS_GPB_MFP2_PB9MFP_Msk | SYS_GPB_MFP2_PB8MFP_Msk + +#if defined(BOARD_USING_NUFUN_LED) + | SYS_GPB_MFP2_PB10MFP_Msk | SYS_GPB_MFP2_PB11MFP_Msk +#endif + ); + + SYS->GPB_MFP2 |= (SYS_GPB_MFP2_PB9MFP_GPIO | SYS_GPB_MFP2_PB8MFP_GPIO +#if defined(BOARD_USING_NUFUN_LED) + | SYS_GPB_MFP2_PB10MFP_GPIO | SYS_GPB_MFP2_PB11MFP_GPIO +#endif + ); + + SYS->GPB_MFP3 &= ~(SYS_GPB_MFP3_PB14MFP_Msk); + SYS->GPB_MFP3 |= (SYS_GPB_MFP3_PB14MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pb(void) +{ + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP1_PB7MFP_Msk | SYS_GPB_MFP1_PB6MFP_Msk); + SYS->GPB_MFP2 &= ~(SYS_GPB_MFP2_PB9MFP_Msk | SYS_GPB_MFP2_PB8MFP_Msk +#if defined(BOARD_USING_NUFUN_LED) + | SYS_GPB_MFP2_PB10MFP_Msk | SYS_GPB_MFP2_PB11MFP_Msk +#endif + ); + + SYS->GPB_MFP3 &= ~(SYS_GPB_MFP3_PB14MFP_Msk); + + return; +} + +void nutool_pincfg_init_pc(void) +{ + SYS->GPC_MFP3 &= ~(SYS_GPC_MFP3_PC13MFP_Msk); + SYS->GPC_MFP3 |= (SYS_GPC_MFP3_PC13MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pc(void) +{ + SYS->GPC_MFP3 &= ~(SYS_GPC_MFP3_PC13MFP_Msk); + + return; +} + +void nutool_pincfg_init_pd(void) +{ + SYS->GPD_MFP2 &= ~(SYS_GPD_MFP2_PD11MFP_Msk | SYS_GPD_MFP2_PD10MFP_Msk); + SYS->GPD_MFP2 |= (SYS_GPD_MFP2_PD11MFP_GPIO | SYS_GPD_MFP2_PD10MFP_GPIO); + SYS->GPD_MFP3 &= ~(SYS_GPD_MFP3_PD14MFP_Msk | SYS_GPD_MFP3_PD12MFP_Msk); + SYS->GPD_MFP3 |= (SYS_GPD_MFP3_PD14MFP_GPIO | SYS_GPD_MFP3_PD12MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_pd(void) +{ + SYS->GPD_MFP2 &= ~(SYS_GPD_MFP2_PD11MFP_Msk | SYS_GPD_MFP2_PD10MFP_Msk); + SYS->GPD_MFP3 &= ~(SYS_GPD_MFP3_PD14MFP_Msk | SYS_GPD_MFP3_PD12MFP_Msk); + + return; +} + +void nutool_pincfg_init_ph(void) +{ + SYS->GPH_MFP2 &= ~(SYS_GPH_MFP2_PH11MFP_Msk | SYS_GPH_MFP2_PH10MFP_Msk); + SYS->GPH_MFP2 |= (SYS_GPH_MFP2_PH11MFP_GPIO | SYS_GPH_MFP2_PH10MFP_GPIO); + + return; +} + +void nutool_pincfg_deinit_ph(void) +{ + SYS->GPH_MFP2 &= ~(SYS_GPH_MFP2_PH11MFP_Msk | SYS_GPH_MFP2_PH10MFP_Msk); + + return; +} + +void nutool_pincfg_init_qspi0(void) +{ + SYS->GPC_MFP0 &= ~(SYS_GPC_MFP0_PC3MFP_Msk | SYS_GPC_MFP0_PC2MFP_Msk | SYS_GPC_MFP0_PC1MFP_Msk | SYS_GPC_MFP0_PC0MFP_Msk); + SYS->GPC_MFP0 |= (SYS_GPC_MFP0_PC3MFP_QSPI0_SS | SYS_GPC_MFP0_PC2MFP_QSPI0_CLK | SYS_GPC_MFP0_PC1MFP_QSPI0_MISO0 | SYS_GPC_MFP0_PC0MFP_QSPI0_MOSI0); + SYS->GPC_MFP1 &= ~(SYS_GPC_MFP1_PC5MFP_Msk | SYS_GPC_MFP1_PC4MFP_Msk); + SYS->GPC_MFP1 |= (SYS_GPC_MFP1_PC5MFP_QSPI0_MISO1 | SYS_GPC_MFP1_PC4MFP_QSPI0_MOSI1); + + return; +} + +void nutool_pincfg_deinit_qspi0(void) +{ + SYS->GPC_MFP0 &= ~(SYS_GPC_MFP0_PC3MFP_Msk | SYS_GPC_MFP0_PC2MFP_Msk | SYS_GPC_MFP0_PC1MFP_Msk | SYS_GPC_MFP0_PC0MFP_Msk); + SYS->GPC_MFP1 &= ~(SYS_GPC_MFP1_PC5MFP_Msk | SYS_GPC_MFP1_PC4MFP_Msk); + + return; +} + +void nutool_pincfg_init_sd0(void) +{ + SYS->GPD_MFP3 &= ~(SYS_GPD_MFP3_PD13MFP_Msk); + SYS->GPD_MFP3 |= (SYS_GPD_MFP3_PD13MFP_SD0_nCD); + SYS->GPE_MFP0 &= ~(SYS_GPE_MFP0_PE3MFP_Msk | SYS_GPE_MFP0_PE2MFP_Msk); + SYS->GPE_MFP0 |= (SYS_GPE_MFP0_PE3MFP_SD0_DAT1 | SYS_GPE_MFP0_PE2MFP_SD0_DAT0); + SYS->GPE_MFP1 &= ~(SYS_GPE_MFP1_PE7MFP_Msk | SYS_GPE_MFP1_PE6MFP_Msk | SYS_GPE_MFP1_PE5MFP_Msk | SYS_GPE_MFP1_PE4MFP_Msk); + SYS->GPE_MFP1 |= (SYS_GPE_MFP1_PE7MFP_SD0_CMD | SYS_GPE_MFP1_PE6MFP_SD0_CLK | SYS_GPE_MFP1_PE5MFP_SD0_DAT3 | SYS_GPE_MFP1_PE4MFP_SD0_DAT2); + + return; +} + +void nutool_pincfg_deinit_sd0(void) +{ + SYS->GPD_MFP3 &= ~(SYS_GPD_MFP3_PD13MFP_Msk); + SYS->GPE_MFP0 &= ~(SYS_GPE_MFP0_PE3MFP_Msk | SYS_GPE_MFP0_PE2MFP_Msk); + SYS->GPE_MFP1 &= ~(SYS_GPE_MFP1_PE7MFP_Msk | SYS_GPE_MFP1_PE6MFP_Msk | SYS_GPE_MFP1_PE5MFP_Msk | SYS_GPE_MFP1_PE4MFP_Msk); + + return; +} + +void nutool_pincfg_init_spi1(void) +{ + SYS->GPE_MFP0 &= ~(SYS_GPE_MFP0_PE1MFP_Msk | SYS_GPE_MFP0_PE0MFP_Msk); + SYS->GPE_MFP0 |= (SYS_GPE_MFP0_PE1MFP_SPI1_MISO | SYS_GPE_MFP0_PE0MFP_SPI1_MOSI); + SYS->GPH_MFP2 &= ~(SYS_GPH_MFP2_PH9MFP_Msk | SYS_GPH_MFP2_PH8MFP_Msk); + SYS->GPH_MFP2 |= (SYS_GPH_MFP2_PH9MFP_SPI1_SS | SYS_GPH_MFP2_PH8MFP_SPI1_CLK); + + return; +} + +void nutool_pincfg_deinit_spi1(void) +{ + SYS->GPE_MFP0 &= ~(SYS_GPE_MFP0_PE1MFP_Msk | SYS_GPE_MFP0_PE0MFP_Msk); + SYS->GPH_MFP2 &= ~(SYS_GPH_MFP2_PH9MFP_Msk | SYS_GPH_MFP2_PH8MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart2_rs485(void) +{ + SET_UART2_RXD_PE9(); + SET_UART2_TXD_PE8(); + SET_UART2_nRTS_PD8(); + + return; +} + +void nutool_pincfg_deinit_uart2_rs485(void) +{ + SYS->GPE_MFP2 &= ~(SYS_GPE_MFP2_PE8MFP_Msk | SYS_GPE_MFP2_PE9MFP_Msk); + SYS->GPD_MFP2 &= ~(SYS_GPD_MFP2_PD8MFP_Msk); + + return; +} +#elif defined(BOARD_USING_NUTFT) +void expansion_nutft_pin_init(void) +{ +#if defined(BOARD_USING_LCD_ILI9341) + SET_SPI2_SS_PA11(); + SET_SPI2_CLK_PA10(); + SET_SPI2_MISO_PA9(); + SET_SPI2_MOSI_PA8(); + + + SET_GPIO_PB2(); + SET_GPIO_PB3(); + SET_GPIO_PB5(); +#endif + +#if defined(BOARD_USING_NUTFT_ADC_TOUCH) + GPIO_SetMode(PB, BIT4 | BIT5 | BIT6 | BIT7, GPIO_MODE_INPUT); + + /* EADC Analog Pin: UNO_A0, UNO_A1, UNO_A2, UNO_A3 */ + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP3_PB14MFP_Msk | SYS_GPB_MFP3_PB15MFP_Msk); + SYS->GPB_MFP1 |= (SYS_GPB_MFP3_PB14MFP_EADC0_CH14 | SYS_GPB_MFP3_PB15MFP_EADC0_CH15); + SYS->GPB_MFP2 &= ~(SYS_GPB_MFP2_PB9MFP_Msk | SYS_GPB_MFP2_PB8MFP_Msk); + SYS->GPB_MFP2 |= (SYS_GPB_MFP2_PB9MFP_EADC0_CH9 | SYS_GPB_MFP2_PB8MFP_EADC0_CH8); + + /* Disable digital path on these EADC pins */ + GPIO_DISABLE_DIGITAL_PATH(PB, BIT8 | BIT9 | BIT14 | BIT15); +#endif + +#if defined(BOARD_USING_QSPI_FLASH) + SET_QSPI0_MOSI0_PA0(); + SET_QSPI0_MISO0_PA1(); + SET_QSPI0_CLK_PA2(); + SET_QSPI0_SS_PA3(); + SET_QSPI0_MOSI1_PA4(); + SET_QSPI0_MISO1_PA5(); +#endif + +#if defined(BOARD_USING_NUTFT_BUTTON) + SYS->GPB_MFP0 &= ~(SYS_GPB_MFP0_PB0MFP_Msk | SYS_GPB_MFP0_PB1MFP_Msk); + + /* Disable digital path on these ADC pins */ + GPIO_ENABLE_DIGITAL_PATH(PB, BIT0 | BIT1); +#endif + +} +#endif + +void nutool_pincfg_init_uart0(void) +{ + SET_UART0_RXD_PB12(); + SET_UART0_TXD_PB13(); + + return; +} + +void nutool_pincfg_deinit_uart0(void) +{ + SET_GPIO_PB12(); + SET_GPIO_PB13(); + + return; +} + +void nutool_pincfg_init_hsusb(void) +{ + /* HSUSB_VBUS_EN (USB 2.0 VBUS power enable pin) multi-function pin - PB.10 */ + SET_HSUSB_VBUS_EN_PB10(); + + /* HSUSB_VBUS_ST (USB 2.0 over-current detect pin) multi-function pin - PB.11 */ + SET_HSUSB_VBUS_ST_PB11(); +} + +void nutool_pincfg_deinit_hsusb(void) +{ + SET_GPIO_PB10(); + SET_GPIO_PB11(); +} + +void nutool_pincfg_init_eadc(void) +{ +#if defined(BOARD_USING_NUFUN_ADC_TOUCH) + GPIO_SetMode(PB, BIT2 | BIT3 | BIT4 | BIT5, GPIO_MODE_INPUT); + + SYS->GPB_MFP0 &= ~(SYS_GPB_MFP0_PB2MFP_Msk | SYS_GPB_MFP0_PB2MFP_Msk); + SYS->GPB_MFP0 |= (SYS_GPB_MFP0_PB2MFP_EADC0_CH2 | SYS_GPB_MFP0_PB3MFP_EADC0_CH3); + + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP1_PB4MFP_Msk | SYS_GPB_MFP1_PB5MFP_Msk); + SYS->GPB_MFP1 |= (SYS_GPB_MFP1_PB4MFP_EADC0_CH4 | SYS_GPB_MFP1_PB5MFP_EADC0_CH5); + + GPIO_DISABLE_DIGITAL_PATH(PB, BIT2 | BIT3 | BIT4 | BIT5); +#endif + + GPIO_SetMode(PB, BIT6 | BIT7, GPIO_MODE_INPUT); + + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP1_PB6MFP_Msk | SYS_GPB_MFP1_PB7MFP_Msk); + SYS->GPB_MFP1 |= (SYS_GPB_MFP1_PB6MFP_EADC0_CH6 | SYS_GPB_MFP1_PB7MFP_EADC0_CH7); + + /* Disable digital path on these EADC pins */ + GPIO_DISABLE_DIGITAL_PATH(PB, BIT6 | BIT7); +} + +void nutool_pincfg_deinit_eadc(void) +{ + /* Disable digital path on these EADC pins */ + GPIO_ENABLE_DIGITAL_PATH(PB, BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7); + + SYS->GPB_MFP0 &= ~(SYS_GPB_MFP0_PB2MFP_Msk | SYS_GPB_MFP0_PB2MFP_Msk); + SYS->GPB_MFP1 &= ~(SYS_GPB_MFP1_PB4MFP_Msk | SYS_GPB_MFP1_PB5MFP_Msk | SYS_GPB_MFP1_PB6MFP_Msk | SYS_GPB_MFP1_PB7MFP_Msk); +} + +void nutool_pincfg_init(void) +{ + /* Vref connect to internal */ + SYS_SetVRef(SYS_VREFCTL_VREF_PIN); + + nutool_pincfg_init_uart0(); + nutool_pincfg_init_hsusb(); + nutool_pincfg_init_eadc(); + +#if defined(BOARD_USING_NUFUN) + nutool_pincfg_init_bpwm0(); + nutool_pincfg_init_canfd0(); + nutool_pincfg_init_epwm1(); + nutool_pincfg_init_eqei0(); + nutool_pincfg_init_i2c0(); + nutool_pincfg_init_i2c1(); + nutool_pincfg_init_i2c2(); + nutool_pincfg_init_i2s0(); + nutool_pincfg_init_i3c0(); + nutool_pincfg_init_ice(); + nutool_pincfg_init_llsi0(); + nutool_pincfg_init_pa(); + nutool_pincfg_init_pb(); + nutool_pincfg_init_pc(); + nutool_pincfg_init_pd(); + nutool_pincfg_init_ph(); + nutool_pincfg_init_qspi0(); + nutool_pincfg_init_sd0(); + nutool_pincfg_init_spi1(); + nutool_pincfg_init_uart2_rs485(); +#elif defined(BOARD_USING_NUTFT) + expansion_nutft_pin_init(); +#endif + + return; +} + +void nutool_pincfg_deinit(void) +{ + nutool_pincfg_deinit_uart0(); + nutool_pincfg_deinit_hsusb(); + nutool_pincfg_deinit_eadc(); + +#if defined(BOARD_USING_NUFUN) + nutool_pincfg_deinit_bpwm0(); + nutool_pincfg_deinit_canfd0(); + nutool_pincfg_deinit_epwm1(); + nutool_pincfg_deinit_eqei0(); + nutool_pincfg_deinit_i2c0(); + nutool_pincfg_deinit_i2c1(); + nutool_pincfg_deinit_i2c2(); + nutool_pincfg_deinit_i2s0(); + nutool_pincfg_deinit_i3c0(); + nutool_pincfg_deinit_ice(); + nutool_pincfg_deinit_llsi0(); + nutool_pincfg_deinit_pa(); + nutool_pincfg_deinit_pb(); + nutool_pincfg_deinit_pc(); + nutool_pincfg_deinit_pd(); + nutool_pincfg_deinit_ph(); + nutool_pincfg_deinit_qspi0(); + nutool_pincfg_deinit_sd0(); + nutool_pincfg_deinit_spi1(); + nutool_pincfg_deinit_uart2_rs485(); +#elif defined(BOARD_USING_NUTFT) + /* No de-initialization code is required for NuTFT pins */ +#endif + + return; +} + +/*** (C) COPYRIGHT 2013-2025 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.h b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.h new file mode 100644 index 00000000000..fa44171af73 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version v1.35.3 + * @Date Mon Oct 27 2025 19:42:48 GMT+0800 (Taipei Standard Time) + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2025 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_pincfg_init_bpwm0(void); +void nutool_pincfg_deinit_bpwm0(void); +void nutool_pincfg_init_canfd0(void); +void nutool_pincfg_deinit_canfd0(void); +void nutool_pincfg_init_epwm0(void); +void nutool_pincfg_deinit_epwm0(void); +void nutool_pincfg_init_eqei0(void); +void nutool_pincfg_deinit_eqei0(void); +void nutool_pincfg_init_i2c0(void); +void nutool_pincfg_deinit_i2c0(void); +void nutool_pincfg_init_i2c2(void); +void nutool_pincfg_deinit_i2c2(void); +void nutool_pincfg_init_i2s0(void); +void nutool_pincfg_deinit_i2s0(void); +void nutool_pincfg_init_i3c0(void); +void nutool_pincfg_deinit_i3c0(void); +void nutool_pincfg_init_ice(void); +void nutool_pincfg_deinit_ice(void); +void nutool_pincfg_init_llsi0(void); +void nutool_pincfg_deinit_llsi0(void); +void nutool_pincfg_init_pa(void); +void nutool_pincfg_deinit_pa(void); +void nutool_pincfg_init_pb(void); +void nutool_pincfg_deinit_pb(void); +void nutool_pincfg_init_pc(void); +void nutool_pincfg_deinit_pc(void); +void nutool_pincfg_init_pd(void); +void nutool_pincfg_deinit_pd(void); +void nutool_pincfg_init_ph(void); +void nutool_pincfg_deinit_ph(void); +void nutool_pincfg_init_qspi0(void); +void nutool_pincfg_deinit_qspi0(void); +void nutool_pincfg_init_sd0(void); +void nutool_pincfg_deinit_sd0(void); +void nutool_pincfg_init_spi1(void); +void nutool_pincfg_deinit_spi1(void); +void nutool_pincfg_init_uart0(void); +void nutool_pincfg_deinit_uart0(void); +void nutool_pincfg_init(void); +void nutool_pincfg_deinit(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2025 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.ncfg b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.ncfg new file mode 100644 index 00000000000..2c28d059d73 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/NuPinConfig/nutool_pincfg.ncfg @@ -0,0 +1,188 @@ +/**************************************************************************** + * @file nutool_pincfg.ncfg + * @version v1.35.3 + * @Date Mon Oct 27 2025 19:42:48 GMT+0800 (Taipei Standard Time) + * @brief NuMicro config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2025 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:M3334KIGAE(LQFP128) +Pin1:EPWM0_CH0 +Pin2:PB.4 +Pin3:PB.3 +Pin4:PB.2 +Pin5:PC.12 +Pin6:PC.11 +Pin7:PC.10 +Pin8:I3C0_PUPEN +Pin9:I3C0_SCL +Pin10:I3C0_SDA +Pin11:VSS +Pin12:VDD +Pin13:I2C2_SCL +Pin14:I2C2_SDA +Pin15:PA.9 +Pin16:PA.8 +Pin17:PC.13 +Pin18:PD.12 +Pin19:PD.11 +Pin20:PD.10 +Pin21:I2C0_SMBAL +Pin22:I2C0_SMBSUS +Pin23:PG.4 +Pin24:PF.11 +Pin25:I2S0_BCLK +Pin26:I2S0_MCLK +Pin27:I2S0_DI +Pin28:I2S0_DO +Pin29:I2S0_LRCK +Pin30:PF.14 +Pin31:PF.5 +Pin32:PF.4 +Pin33:PH.4 +Pin34:PH.5 +Pin35:PH.6 +Pin36:PH.7 +Pin37:PF.3 +Pin38:PF.2 +Pin39:VSS +Pin40:VDD +Pin41:PE.8 +Pin42:PE.9 +Pin43:PE.10 +Pin44:PE.11 +Pin45:PE.12 +Pin46:I2C0_SCL +Pin47:I2C0_SDA +Pin48:PC.7 +Pin49:UART0_nRTS +Pin50:UART0_TXD +Pin51:UART0_RXD +Pin52:VSS +Pin53:VDD +Pin54:LDO_CAP +Pin55:EQEI0_INDEX +Pin56:EQEI0_A +Pin57:EQEI0_B +Pin58:PA.2 +Pin59:PA.1 +Pin60:QSPI0_MOSI0 +Pin61:PF.15 +Pin62:CANFD0_TXD +Pin63:CANFD0_RXD +Pin64:nRESET +Pin65:ICE_DAT +Pin66:ICE_CLK +Pin67:PD.9 +Pin68:PD.8 +Pin69:QSPI0_MISO1 +Pin70:QSPI0_MOSI1 +Pin71:QSPI0_SS +Pin72:QSPI0_CLK +Pin73:QSPI0_MISO0 +Pin74:PC.0 +Pin75:VSS +Pin76:VDD +Pin77:PG.9 +Pin78:PG.10 +Pin79:PG.11 +Pin80:BPWM0_CH2 +Pin81:BPWM0_CH1 +Pin82:BPWM0_CH0 +Pin83:PG.15 +Pin84:SD0_nCD +Pin85:PA.12 +Pin86:PA.13 +Pin87:PA.14 +Pin88:PA.15 +Pin89:HSUSB_VRES +Pin90:HSUSB_VDD33 +Pin91:HSUSB_VBUS +Pin92:HSUSB_D- +Pin93:HSUSB_VSS +Pin94:HSUSB_D+ +Pin95:HSUSB_VDD12_CAP +Pin96:HSUSB_ID +Pin97:SD0_CMD +Pin98:SD0_CLK +Pin99:SD0_DAT3 +Pin100:SD0_DAT2 +Pin101:SD0_DAT1 +Pin102:SD0_DAT0 +Pin103:VSS +Pin104:VDD +Pin105:SPI1_MISO +Pin106:SPI1_MOSI +Pin107:SPI1_CLK +Pin108:SPI1_SS +Pin109:PH.10 +Pin110:PH.11 +Pin111:PD.14 +Pin112:VSS +Pin113:LDO_CAP +Pin114:VDD +Pin115:PC.14 +Pin116:LLSI0_OUT +Pin117:PB.14 +Pin118:PB.13 +Pin119:PB.12 +Pin120:AVDD +Pin121:VREF +Pin122:AVSS +Pin123:PB.11 +Pin124:PB.10 +Pin125:PB.9 +Pin126:PB.8 +Pin127:PB.7 +Pin128:PB.6 +GPIOpin:15 +GPIOpin:14 +GPIOpin:16 +GPIOpin:108 +GPIOpin:109 +GPIOpin:116 +GPIOpin:123 +GPIOpin:122 +GPIOpin:124 +GPIOpin:125 +GPIOpin:126 +GPIOpin:127 +GPIOpin:17 +GPIOpin:110 +GPIOpin:19 +GPIOpin:18 +SYS->GPA_MFP0 = 0x0E000003 +SYS->GPA_MFP1 = 0x07070E0E +SYS->GPA_MFP2 = 0x07070000 +SYS->GPA_MFP3 = 0x00000000 +SYS->GPB_MFP0 = 0x00000E0E +SYS->GPB_MFP1 = 0x00000B00 +SYS->GPB_MFP2 = 0x00000000 +SYS->GPB_MFP3 = 0x10000000 +SYS->GPC_MFP0 = 0x04040400 +SYS->GPC_MFP1 = 0x00070404 +SYS->GPC_MFP2 = 0x00000F04 +SYS->GPC_MFP3 = 0x00000000 +SYS->GPD_MFP2 = 0x00000000 +SYS->GPD_MFP3 = 0x00000300 +SYS->GPE_MFP0 = 0x03030606 +SYS->GPE_MFP1 = 0x03030303 +SYS->GPE_MFP2 = 0x00000000 +SYS->GPE_MFP3 = 0x04040400 +SYS->GPF_MFP0 = 0x00000E0E +SYS->GPF_MFP1 = 0x04040000 +SYS->GPF_MFP2 = 0x00040404 +SYS->GPF_MFP3 = 0x00000000 +SYS->GPG_MFP0 = 0x04040000 +SYS->GPG_MFP1 = 0x00000000 +SYS->GPG_MFP2 = 0x00000000 +SYS->GPG_MFP3 = 0x000C0C0C +SYS->GPH_MFP1 = 0x00000000 +SYS->GPH_MFP2 = 0x00000606 +LockedPins=[] +/*** (C) COPYRIGHT 2013-2025 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/SConscript b/bsp/nuvoton/numaker-m3334ki/board/SConscript new file mode 100644 index 00000000000..56e8ef94991 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Split(""" +NuPinConfig/nutool_pincfg.c +""") + +src += Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig'] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-m3334ki/board/board.h b/bsp/nuvoton/numaker-m3334ki/board/board.h new file mode 100644 index 00000000000..b46d053752f --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/board.h @@ -0,0 +1,37 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +#define SRAM_SIZE (320) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) + extern int Image$$RW_RAM$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_RAM$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="CSTACK" + #define HEAP_BEGIN (__segment_end("CSTACK")) +#else + extern int __bss_end__; + #define HEAP_BEGIN ((void *)&__bss_end__) +#endif + +#define HEAP_END (void *)SRAM_END + + +void rt_hw_board_init(void); +void rt_hw_cpu_reset(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c b/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c new file mode 100644 index 00000000000..b8816782c3f --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c @@ -0,0 +1,80 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2024-3-26 Wayne First version +* +******************************************************************************/ + +#include "rtconfig.h" + +#if defined(BSP_USING_CUSTOM_LOADER) + +#include "NuMicro.h" + +#ifndef __CUSTOM_LOADER_INFO_ATTRIBUTE +#define __CUSTOM_LOADER_INFO_ATTRIBUTE __attribute__((used, section("CLINFO"))) +#endif + +/* Use an unsigned integer number as version number. */ +#define DEF_FW_VER_NUM 0x20240328 + +typedef struct +{ +#define DEF_MAGIC_NUM 0xA5A5A5A5 + uint32_t m_u32MagicNum1; + uint32_t m_u32FwVer; + uint32_t m_u32Reserved; + uint32_t m_u32MagicNum2; +} customer_loader_info; + +static const customer_loader_info s_CLInfo __CUSTOM_LOADER_INFO_ATTRIBUTE = +{ + .m_u32MagicNum1 = DEF_MAGIC_NUM, + .m_u32FwVer = DEF_FW_VER_NUM, + .m_u32Reserved = sizeof(customer_loader_info), + .m_u32MagicNum2 = ~DEF_MAGIC_NUM, +}; + +static uint32_t custom_loader_swapbank(void) +{ + uint32_t u32CurBank, u32NextBank; + + u32CurBank = RMC_GET_ISP_BANK_SELECTION(); + u32NextBank = (~u32CurBank & 0x1); + + SYS_UnlockReg(); + RMC_ENABLE_ISP(); + + RMC_RemapBank(u32NextBank); + + return RMC_GET_ISP_BANK_SELECTION(); +} + +uint32_t custom_loader_exec_last(void) +{ + uint32_t u32CurBankNo = 0; + customer_loader_info *psInfoBank1 = (customer_loader_info *)((uint32_t)&s_CLInfo + RMC_APROM_BANK0_END); + + if ((psInfoBank1->m_u32MagicNum1 == s_CLInfo.m_u32MagicNum1) && + (psInfoBank1->m_u32MagicNum2 == s_CLInfo.m_u32MagicNum2) && + (psInfoBank1->m_u32FwVer > s_CLInfo.m_u32FwVer)) + { + // Swap to Bank#1 + u32CurBankNo = custom_loader_swapbank(); + } + /* else Stay bank#0 */ + + return u32CurBankNo; +} + +void *custom_loader_get_info(void) +{ + return (void *)&s_CLInfo; +} + +#endif diff --git a/bsp/nuvoton/numaker-m3334ki/board/fal_cfg.h b/bsp/nuvoton/numaker-m3334ki/board/fal_cfg.h new file mode 100644 index 00000000000..0b6aeded25e --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/fal_cfg.h @@ -0,0 +1,75 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2022-4-1 Wayne First version +* +******************************************************************************/ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include "drv_fmc.h" +#include "rtconfig.h" + +/* ===================== Flash device Configuration ========================= */ +#if defined(FAL_PART_HAS_TABLE_CFG) + +/* ---------------- FMC ---------------- */ +#if defined(BSP_USING_FMC) +#define IFDEF_BOARD_USING_FMC &g_falFMC_AP, &g_falFMC_LD, &g_falFMC_DF, +#define FAL_PART_FMC \ + {FAL_PART_MAGIC_WORD, "ldrom", "FMC_LD", 0x0, (8*1024), 0}, \ + {FAL_PART_MAGIC_WORD, "aprom", "FMC_AP", 0x0, (512*1024), 0}, \ + {FAL_PART_MAGIC_WORD, "dataflash", "FMC_DF", 0x0, (4*1024), 0}, +#else +#define IFDEF_BOARD_USING_FMC +#define FAL_PART_FMC +#endif + +/* ---------------- QSPI ---------------- */ +#if defined(BOARD_USING_QSPI_FLASH) || defined(BOARD_USING_NUFUN_QSPI_FLASH) +extern struct fal_flash_dev nor_flash0; +#define IFDEF_BOARD_USING_QSPI &nor_flash0, +#define FAL_PART_QSPI \ + {FAL_PART_MAGIC_WORD, "filesystem", FAL_USING_NOR_FLASH_DEV_NAME, 0, (2 * 1024 * 1024), 0}, +#else +#define IFDEF_BOARD_USING_QSPI +#define FAL_PART_QSPI +#endif + +/* ---------------- Device Table ---------------- */ +#if defined(BSP_USING_FMC) || defined(BOARD_USING_QSPI_FLASH) || defined(BOARD_USING_NUFUN_QSPI_FLASH) +#define FAL_FLASH_DEV_TABLE \ + { \ + IFDEF_BOARD_USING_FMC \ + IFDEF_BOARD_USING_QSPI \ + } +#else +#define FAL_FLASH_DEV_TABLE { } +#endif + +/* ---------------- Partition Table ---------------- */ +#if defined(BSP_USING_FMC) || defined(BOARD_USING_QSPI_FLASH) || defined(BOARD_USING_NUFUN_QSPI_FLASH) +#define FAL_PART_TABLE \ + { \ + FAL_PART_FMC \ + FAL_PART_QSPI \ + } +#else +#define FAL_PART_TABLE { } +#endif + +#else /* !FAL_PART_HAS_TABLE_CFG */ + +#define FAL_FLASH_DEV_TABLE { } +#define FAL_PART_TABLE { } + +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/nuvoton/numaker-m3334ki/board/nutool_clkcfg.h b/bsp/nuvoton/numaker-m3334ki/board/nutool_clkcfg.h new file mode 100644 index 00000000000..c4ffd553e38 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/nutool_clkcfg.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * @file nutool_clkcfg.h + * @version V1.05 + * @Date 2020/11/11-11:43:32 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_CLKCFG_H__ +#define __NUTOOL_CLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +#undef __HXT +#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency */ + +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_CLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.c b/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.c new file mode 100644 index 00000000000..71e3cf13b98 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.c @@ -0,0 +1,1521 @@ +/**************************************************************************** + * @file nutool_modclkcfg.c + * @version V1.05 + * @Date 2020/11/11-11:43:32 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" +#include "rtconfig.h" + +void nutool_modclkcfg_init_pdma0(void) +{ + CLK_EnableModuleClock(PDMA0_MODULE); + return; +} +void nutool_modclkcfg_deinit_pdma0(void) +{ + CLK_DisableModuleClock(PDMA0_MODULE); + return; +} + +void nutool_modclkcfg_init_isp(void) +{ + CLK_EnableModuleClock(ISP_MODULE); + return; +} +void nutool_modclkcfg_deinit_isp(void) +{ + CLK_DisableModuleClock(ISP_MODULE); + return; +} + +void nutool_modclkcfg_init_ebi(void) +{ + CLK_EnableModuleClock(EBI_MODULE); + return; +} +void nutool_modclkcfg_deinit_ebi(void) +{ + CLK_DisableModuleClock(EBI_MODULE); + return; +} + +void nutool_modclkcfg_init_st(void) +{ + CLK_EnableModuleClock(ST_MODULE); + return; +} +void nutool_modclkcfg_deinit_st(void) +{ + CLK_DisableModuleClock(ST_MODULE); + return; +} + +void nutool_modclkcfg_init_sdh0(void) +{ + /* Select IP clock source */ + CLK_SetModuleClock(SDH0_MODULE, CLK_CLKSEL0_SDH0SEL_PLL_DIV2, CLK_CLKDIV0_SDH0(5)); + + CLK_EnableModuleClock(SDH0_MODULE); + return; +} +void nutool_modclkcfg_deinit_sdh0(void) +{ + CLK_DisableModuleClock(SDH0_MODULE); + return; +} + +void nutool_modclkcfg_init_crc(void) +{ + CLK_EnableModuleClock(CRC_MODULE); + return; +} +void nutool_modclkcfg_deinit_crc(void) +{ + CLK_DisableModuleClock(CRC_MODULE); + return; +} + +void nutool_modclkcfg_init_canfd0(void) +{ + CLK_EnableModuleClock(CANFD0_MODULE); + return; +} +void nutool_modclkcfg_deinit_canfd0(void) +{ + CLK_DisableModuleClock(CANFD0_MODULE); + return; +} + +void nutool_modclkcfg_init_canfd1(void) +{ + CLK_EnableModuleClock(CANFD1_MODULE); + return; +} +void nutool_modclkcfg_deinit_canfd1(void) +{ + CLK_DisableModuleClock(CANFD1_MODULE); + return; +} + +void nutool_modclkcfg_init_hsusbd(void) +{ + CLK_EnableModuleClock(HSUSBD_MODULE); + return; +} +void nutool_modclkcfg_deinit_hsusbd(void) +{ + CLK_DisableModuleClock(HSUSBD_MODULE); + return; +} + +void nutool_modclkcfg_init_pdci(void) +{ + CLK_EnableModuleClock(PDCI_MODULE); + return; +} +void nutool_modclkcfg_deinit_pdci(void) +{ + CLK_DisableModuleClock(PDCI_MODULE); + return; +} + +void nutool_modclkcfg_init_fmcidle(void) +{ + CLK_EnableModuleClock(FMCIDLE_MODULE); + return; +} +void nutool_modclkcfg_deinit_fmcidle(void) +{ + CLK_DisableModuleClock(FMCIDLE_MODULE); + return; +} + +void nutool_modclkcfg_init_usbh(void) +{ + CLK_EnableModuleClock(USBH_MODULE); + + return; +} +void nutool_modclkcfg_deinit_usbh(void) +{ + CLK_DisableModuleClock(USBH_MODULE); + + return; +} + +void nutool_modclkcfg_init_canram0(void) +{ + CLK_EnableModuleClock(CANRAM0_MODULE); + return; +} +void nutool_modclkcfg_deinit_canram0(void) +{ + CLK_DisableModuleClock(CANRAM0_MODULE); + return; +} + +void nutool_modclkcfg_init_canram1(void) +{ + CLK_EnableModuleClock(CANRAM1_MODULE); + return; +} +void nutool_modclkcfg_deinit_canram1(void) +{ + CLK_DisableModuleClock(CANRAM1_MODULE); + return; +} + +void nutool_modclkcfg_init_trace(void) +{ + CLK_EnableModuleClock(TRACE_MODULE); + return; +} +void nutool_modclkcfg_deinit_trace(void) +{ + CLK_DisableModuleClock(TRACE_MODULE); + return; +} + +void nutool_modclkcfg_init_gpa(void) +{ + CLK_EnableModuleClock(GPA_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpa(void) +{ + CLK_DisableModuleClock(GPA_MODULE); + return; +} + +void nutool_modclkcfg_init_gpb(void) +{ + CLK_EnableModuleClock(GPB_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpb(void) +{ + CLK_DisableModuleClock(GPB_MODULE); + return; +} + +void nutool_modclkcfg_init_gpc(void) +{ + CLK_EnableModuleClock(GPC_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpc(void) +{ + CLK_DisableModuleClock(GPC_MODULE); + return; +} + +void nutool_modclkcfg_init_gpd(void) +{ + CLK_EnableModuleClock(GPD_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpd(void) +{ + CLK_DisableModuleClock(GPD_MODULE); + return; +} + +void nutool_modclkcfg_init_gpe(void) +{ + CLK_EnableModuleClock(GPE_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpe(void) +{ + CLK_DisableModuleClock(GPE_MODULE); + return; +} + +void nutool_modclkcfg_init_gpf(void) +{ + CLK_EnableModuleClock(GPF_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpf(void) +{ + CLK_DisableModuleClock(GPF_MODULE); + return; +} + +void nutool_modclkcfg_init_gpg(void) +{ + CLK_EnableModuleClock(GPG_MODULE); + return; +} +void nutool_modclkcfg_deinit_gpg(void) +{ + CLK_DisableModuleClock(GPG_MODULE); + return; +} + +void nutool_modclkcfg_init_gph(void) +{ + CLK_EnableModuleClock(GPH_MODULE); + return; +} +void nutool_modclkcfg_deinit_gph(void) +{ + CLK_DisableModuleClock(GPH_MODULE); + return; +} + +void nutool_modclkcfg_init_wdt0(void) +{ + CLK_EnableModuleClock(WDT0_MODULE); + CLK_SetModuleClock(WDT0_MODULE, CLK_CLKSEL1_WDT0SEL_HCLK_DIV2048, MODULE_NoMsk); + return; +} +void nutool_modclkcfg_deinit_wdt0(void) +{ + CLK_DisableModuleClock(WDT0_MODULE); + return; +} + +void nutool_modclkcfg_init_wdt1(void) +{ + CLK_EnableModuleClock(WDT1_MODULE); + CLK_SetModuleClock(WDT1_MODULE, CLK_CLKSEL1_WDT1SEL_HCLK_DIV2048, MODULE_NoMsk); + return; +} +void nutool_modclkcfg_deinit_wdt1(void) +{ + CLK_DisableModuleClock(WDT1_MODULE); + return; +} + +void nutool_modclkcfg_init_wwdt0(void) +{ + CLK_EnableModuleClock(WWDT0_MODULE); + return; +} +void nutool_modclkcfg_deinit_wwdt0(void) +{ + CLK_DisableModuleClock(WWDT0_MODULE); + return; +} + +void nutool_modclkcfg_init_wwdt1(void) +{ + CLK_EnableModuleClock(WWDT1_MODULE); + return; +} +void nutool_modclkcfg_deinit_wwdt1(void) +{ + CLK_DisableModuleClock(WWDT1_MODULE); + return; +} + +void nutool_modclkcfg_init_rtc(void) +{ + CLK_EnableModuleClock(RTC_MODULE); + + /* RTC clock source select LXT */ + CLK_SetModuleClock(RTC_MODULE, RTC_LXTCTL_RTCCKSEL_LXT, 0); + + /* Set LXT as RTC clock source */ + RTC_SetClockSource(RTC_CLOCK_SOURCE_LXT); + + return; +} +void nutool_modclkcfg_deinit_rtc(void) +{ + CLK_DisableModuleClock(RTC_MODULE); + return; +} + +void nutool_modclkcfg_init_tmr0(void) +{ + CLK_EnableModuleClock(TMR0_MODULE); + +#if defined(BSP_USING_TPWM0) + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, MODULE_NoMsk); +#else + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HIRC, MODULE_NoMsk); +#endif + + return; +} + +void nutool_modclkcfg_deinit_tmr0(void) +{ + CLK_DisableModuleClock(TMR0_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr1(void) +{ + CLK_EnableModuleClock(TMR1_MODULE); + +#if defined(BSP_USING_TPWM1) + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, MODULE_NoMsk); +#else + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HIRC, MODULE_NoMsk); +#endif + + return; +} + +void nutool_modclkcfg_deinit_tmr1(void) +{ + CLK_DisableModuleClock(TMR1_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr2(void) +{ + CLK_EnableModuleClock(TMR2_MODULE); + +#if defined(BSP_USING_TPWM2) + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, MODULE_NoMsk); +#else + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HIRC, MODULE_NoMsk); +#endif + + return; +} + +void nutool_modclkcfg_deinit_tmr2(void) +{ + CLK_DisableModuleClock(TMR2_MODULE); + + return; +} + +void nutool_modclkcfg_init_tmr3(void) +{ + CLK_EnableModuleClock(TMR3_MODULE); + +#if defined(BSP_USING_TPWM3) + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_PCLK1, MODULE_NoMsk); +#else + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HIRC, MODULE_NoMsk); +#endif + + return; +} + +void nutool_modclkcfg_deinit_tmr3(void) +{ + CLK_DisableModuleClock(TMR3_MODULE); + + return; +} + +void nutool_modclkcfg_init_clko(void) +{ + CLK_EnableModuleClock(CLKO_MODULE); + return; +} +void nutool_modclkcfg_deinit_clko(void) +{ + CLK_DisableModuleClock(CLKO_MODULE); + return; +} + +void nutool_modclkcfg_init_acmp01(void) +{ + CLK_EnableModuleClock(ACMP01_MODULE); + return; +} +void nutool_modclkcfg_deinit_acmp01(void) +{ + CLK_DisableModuleClock(ACMP01_MODULE); + return; +} + +void nutool_modclkcfg_init_i2c0(void) +{ + CLK_EnableModuleClock(I2C0_MODULE); + return; +} +void nutool_modclkcfg_deinit_i2c0(void) +{ + CLK_DisableModuleClock(I2C0_MODULE); + return; +} + +void nutool_modclkcfg_init_i2c1(void) +{ + CLK_EnableModuleClock(I2C1_MODULE); + return; +} +void nutool_modclkcfg_deinit_i2c1(void) +{ + CLK_DisableModuleClock(I2C1_MODULE); + return; +} + +void nutool_modclkcfg_init_i2c2(void) +{ + CLK_EnableModuleClock(I2C2_MODULE); + return; +} +void nutool_modclkcfg_deinit_i2c2(void) +{ + CLK_DisableModuleClock(I2C2_MODULE); + return; +} + +void nutool_modclkcfg_init_i3c0(void) +{ + CLK_EnableModuleClock(I3C0_MODULE); + return; +} +void nutool_modclkcfg_deinit_i3c0(void) +{ + CLK_DisableModuleClock(I3C0_MODULE); + return; +} + +void nutool_modclkcfg_init_qspi0(void) +{ + CLK_EnableModuleClock(QSPI0_MODULE); + CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_qspi0(void) +{ + CLK_DisableModuleClock(QSPI0_MODULE); + return; +} + +void nutool_modclkcfg_init_spi0(void) +{ + CLK_EnableModuleClock(SPI0_MODULE); + CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk); + return; +} +void nutool_modclkcfg_deinit_spi0(void) +{ + CLK_DisableModuleClock(SPI0_MODULE); + return; +} + +void nutool_modclkcfg_init_spi1(void) +{ + CLK_EnableModuleClock(SPI1_MODULE); + CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_spi1(void) +{ + CLK_DisableModuleClock(SPI1_MODULE); + return; +} + +void nutool_modclkcfg_init_spi2(void) +{ + CLK_EnableModuleClock(SPI2_MODULE); + CLK_SetModuleClock(SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_spi2(void) +{ + CLK_DisableModuleClock(SPI2_MODULE); + return; +} + + +void nutool_modclkcfg_init_uart0(void) +{ + CLK_EnableModuleClock(UART0_MODULE); + + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart0(void) +{ + CLK_DisableModuleClock(UART0_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart1(void) +{ + CLK_EnableModuleClock(UART1_MODULE); + CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART1SEL_HIRC, CLK_CLKDIV0_UART1(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart1(void) +{ + CLK_DisableModuleClock(UART1_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart2(void) +{ + CLK_EnableModuleClock(UART2_MODULE); + CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL3_UART2SEL_HIRC, CLK_CLKDIV1_UART2(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart2(void) +{ + CLK_DisableModuleClock(UART2_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart3(void) +{ + CLK_EnableModuleClock(UART3_MODULE); + CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL3_UART3SEL_HIRC, CLK_CLKDIV1_UART3(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart3(void) +{ + CLK_DisableModuleClock(UART3_MODULE); + + return; +} + +void nutool_modclkcfg_init_uart4(void) +{ + CLK_EnableModuleClock(UART4_MODULE); + CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL3_UART4SEL_HIRC, CLK_CLKDIV1_UART4(1)); + + return; +} + +void nutool_modclkcfg_deinit_uart4(void) +{ + CLK_DisableModuleClock(UART4_MODULE); + + return; +} + +void nutool_modclkcfg_init_eadc0(void) +{ + CLK_EnableModuleClock(EADC0_MODULE); + CLK_SetModuleClock(EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_PLL_DIV2, CLK_CLKDIV0_EADC0(8)); + + return; +} +void nutool_modclkcfg_deinit_eadc0(void) +{ + CLK_DisableModuleClock(EADC0_MODULE); + return; +} + +void nutool_modclkcfg_init_i2s0(void) +{ + CLK_EnableModuleClock(I2S0_MODULE); + CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL3_I2S0SEL_HIRC, 0); + + return; +} +void nutool_modclkcfg_deinit_i2s0(void) +{ + CLK_DisableModuleClock(I2S0_MODULE); + return; +} + +void nutool_modclkcfg_init_hsotg(void) +{ + CLK_EnableModuleClock(HSOTG_MODULE); + return; +} +void nutool_modclkcfg_deinit_hsotg(void) +{ + CLK_DisableModuleClock(HSOTG_MODULE); + return; +} + +void nutool_modclkcfg_init_usci0(void) +{ + CLK_EnableModuleClock(USCI0_MODULE); + return; +} +void nutool_modclkcfg_deinit_usci0(void) +{ + CLK_DisableModuleClock(USCI0_MODULE); + return; +} + +void nutool_modclkcfg_init_usci1(void) +{ + CLK_EnableModuleClock(USCI1_MODULE); + return; +} +void nutool_modclkcfg_deinit_usci1(void) +{ + CLK_DisableModuleClock(USCI1_MODULE); + return; +} + +void nutool_modclkcfg_init_epwm0(void) +{ + CLK_EnableModuleClock(EPWM0_MODULE); + CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_epwm0(void) +{ + CLK_DisableModuleClock(EPWM0_MODULE); + return; +} + +void nutool_modclkcfg_init_epwm1(void) +{ + CLK_EnableModuleClock(EPWM1_MODULE); + CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} + +void nutool_modclkcfg_deinit_epwm1(void) +{ + CLK_DisableModuleClock(EPWM1_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm0(void) +{ + CLK_EnableModuleClock(BPWM0_MODULE); + CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PCLK0, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm0(void) +{ + CLK_DisableModuleClock(BPWM0_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm1(void) +{ + CLK_EnableModuleClock(BPWM1_MODULE); + CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PCLK1, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm1(void) +{ + CLK_DisableModuleClock(BPWM1_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm2(void) +{ + CLK_EnableModuleClock(BPWM2_MODULE); + CLK_SetModuleClock(BPWM2_MODULE, CLK_CLKSEL2_BPWM2SEL_PCLK0, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm2(void) +{ + CLK_DisableModuleClock(BPWM2_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm3(void) +{ + CLK_EnableModuleClock(BPWM3_MODULE); + CLK_SetModuleClock(BPWM3_MODULE, CLK_CLKSEL2_BPWM3SEL_PCLK1, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm3(void) +{ + CLK_DisableModuleClock(BPWM3_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm4(void) +{ + CLK_EnableModuleClock(BPWM4_MODULE); + CLK_SetModuleClock(BPWM4_MODULE, CLK_CLKSEL2_BPWM4SEL_PCLK0, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm4(void) +{ + CLK_DisableModuleClock(BPWM4_MODULE); + return; +} + +void nutool_modclkcfg_init_bpwm5(void) +{ + CLK_EnableModuleClock(BPWM5_MODULE); + CLK_SetModuleClock(BPWM5_MODULE, CLK_CLKSEL2_BPWM5SEL_PCLK1, MODULE_NoMsk); + + return; +} +void nutool_modclkcfg_deinit_bpwm5(void) +{ + CLK_DisableModuleClock(BPWM5_MODULE); + return; +} + +void nutool_modclkcfg_init_eqei0(void) +{ + CLK_EnableModuleClock(EQEI0_MODULE); + return; +} +void nutool_modclkcfg_deinit_eqei0(void) +{ + CLK_DisableModuleClock(EQEI0_MODULE); + return; +} + +void nutool_modclkcfg_init_ecap0(void) +{ + CLK_EnableModuleClock(ECAP0_MODULE); + return; +} +void nutool_modclkcfg_deinit_ecap0(void) +{ + CLK_DisableModuleClock(ECAP0_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi0(void) +{ + CLK_EnableModuleClock(LLSI0_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi0(void) +{ + CLK_DisableModuleClock(LLSI0_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi1(void) +{ + CLK_EnableModuleClock(LLSI1_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi1(void) +{ + CLK_DisableModuleClock(LLSI1_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi2(void) +{ + CLK_EnableModuleClock(LLSI2_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi2(void) +{ + CLK_DisableModuleClock(LLSI2_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi3(void) +{ + CLK_EnableModuleClock(LLSI3_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi3(void) +{ + CLK_DisableModuleClock(LLSI3_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi4(void) +{ + CLK_EnableModuleClock(LLSI4_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi4(void) +{ + CLK_DisableModuleClock(LLSI4_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi5(void) +{ + CLK_EnableModuleClock(LLSI5_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi5(void) +{ + CLK_DisableModuleClock(LLSI5_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi6(void) +{ + CLK_EnableModuleClock(LLSI6_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi6(void) +{ + CLK_DisableModuleClock(LLSI6_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi7(void) +{ + CLK_EnableModuleClock(LLSI7_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi7(void) +{ + CLK_DisableModuleClock(LLSI7_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi8(void) +{ + CLK_EnableModuleClock(LLSI8_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi8(void) +{ + CLK_DisableModuleClock(LLSI8_MODULE); + return; +} + +void nutool_modclkcfg_init_llsi9(void) +{ + CLK_EnableModuleClock(LLSI9_MODULE); + return; +} +void nutool_modclkcfg_deinit_llsi9(void) +{ + CLK_DisableModuleClock(LLSI9_MODULE); + return; +} + +void nutool_modclkcfg_init_ellsi0(void) +{ + CLK_EnableModuleClock(ELLSI0_MODULE); + return; +} +void nutool_modclkcfg_deinit_ellsi0(void) +{ + CLK_DisableModuleClock(ELLSI0_MODULE); + return; +} + + +void nutool_modclkcfg_init_systick(void) +{ + CLK_EnableSysTick(CLK_CLKSEL0_STCLKSEL_HCLK, 0); + + return; +} + +void nutool_modclkcfg_deinit_systick(void) +{ + CLK_DisableSysTick(); + + return; +} + +void nutool_modclkcfg_init_base(void) +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* HXT filter select */ + outpw(0x400002D4, 0x00FF8800); + +#if defined(RT_USING_PM) && defined(BSP_USING_CLK) + /* Release I/O hold status to resume normal I/O operation. */ + /* Note: This option must be set; otherwise, the HXT may not stabilize properly. */ + CLK->IOPDCTL = 1; +#endif + + /* Enable HIRC/HXT/LXT/LIRC clocks */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_LIRCEN_Msk | CLK_PWRCTL_HIRCEN_Msk); + + /* Wait for HIRC/HXT/LXT/LIRC clocks ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk | CLK_STATUS_LXTSTB_Msk | CLK_STATUS_LIRCSTB_Msk | CLK_STATUS_HIRCSTB_Msk); + + /* Set PLL to 180MHz */ + CLK_SetCoreClock(__HSI); + + /* Set PCLK-related clock */ + CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); + + /* Enable all GPIO clock */ + CLK->AHBCLK0 |= CLK_AHBCLK0_GPACKEN_Msk | CLK_AHBCLK0_GPBCKEN_Msk | CLK_AHBCLK0_GPCCKEN_Msk | CLK_AHBCLK0_GPDCKEN_Msk | + CLK_AHBCLK0_GPECKEN_Msk | CLK_AHBCLK0_GPFCKEN_Msk | CLK_AHBCLK0_GPGCKEN_Msk | CLK_AHBCLK0_GPHCKEN_Msk; + + SystemCoreClockUpdate(); + + return; +} + +void Reset_Handler_PreInit(void) +{ + /* Enable base clock */ + nutool_modclkcfg_init_base(); +} + +void nutool_modclkcfg_init(void) +{ +#if defined(BSP_USING_PDMA0) + nutool_modclkcfg_init_pdma0(); +#endif + +#if defined(BSP_USING_ISP) + nutool_modclkcfg_init_isp(); +#endif + +#if defined(BSP_USING_EBI) + nutool_modclkcfg_init_ebi(); +#endif + +#if defined(BSP_USING_ST) + nutool_modclkcfg_init_st(); +#endif + +#if defined(BSP_USING_SDH0) + nutool_modclkcfg_init_sdh0(); +#endif + +#if defined(BSP_USING_CRC) + nutool_modclkcfg_init_crc(); +#endif + +#if defined(BSP_USING_CANFD0) + nutool_modclkcfg_init_canfd0(); +#endif + +#if defined(BSP_USING_CANFD1) + nutool_modclkcfg_init_canfd1(); +#endif + +#if defined(BSP_USING_HSUSBD) + nutool_modclkcfg_init_hsusbd(); +#endif + +#if defined(BSP_USING_SPB) + nutool_modclkcfg_init_spb(); +#endif + +#if defined(BSP_USING_FMCIDLE) + nutool_modclkcfg_init_fmcidle(); +#endif + +#if defined(BSP_USING_USBH) || defined(BSP_USING_HSUSBH) + nutool_modclkcfg_init_usbh(); +#endif + +#if defined(BSP_USING_CANRAM0) + nutool_modclkcfg_init_canram0(); +#endif + +#if defined(BSP_USING_CANRAM1) + nutool_modclkcfg_init_canram1(); +#endif + +#if defined(BSP_USING_TRACE) + nutool_modclkcfg_init_trace(); +#endif + +#if defined(BSP_USING_WDT0) + nutool_modclkcfg_init_wdt0(); +#endif + +#if defined(BSP_USING_WDT1) + nutool_modclkcfg_init_wdt1(); +#endif + +#if defined(BSP_USING_WWDT0) + nutool_modclkcfg_init_wwdt0(); +#endif + +#if defined(BSP_USING_WWDT1) + nutool_modclkcfg_init_wwdt1(); +#endif + +#if defined(BSP_USING_RTC) + nutool_modclkcfg_init_rtc(); +#endif + +#if defined(BSP_USING_TMR0) + nutool_modclkcfg_init_tmr0(); +#endif + +#if defined(BSP_USING_TMR1) + nutool_modclkcfg_init_tmr1(); +#endif + +#if defined(BSP_USING_TMR2) + nutool_modclkcfg_init_tmr2(); +#endif + +#if defined(BSP_USING_TMR3) + nutool_modclkcfg_init_tmr3(); +#endif + +#if defined(BSP_USING_CLKO) + nutool_modclkcfg_init_clko(); +#endif + +#if defined(BSP_USING_ACMP01) + nutool_modclkcfg_init_acmp01(); +#endif + +#if defined(BSP_USING_I2C0) + nutool_modclkcfg_init_i2c0(); +#endif + +#if defined(BSP_USING_I2C1) + nutool_modclkcfg_init_i2c1(); +#endif + +#if defined(BSP_USING_I2C2) + nutool_modclkcfg_init_i2c2(); +#endif + +#if defined(BSP_USING_I3C0) + nutool_modclkcfg_init_i3c0(); +#endif + +#if defined(BSP_USING_QSPI0) + nutool_modclkcfg_init_qspi0(); +#endif + +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPII2S0) + nutool_modclkcfg_init_spi0(); +#endif + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPII2S1) + nutool_modclkcfg_init_spi1(); +#endif + +#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPII2S2) + nutool_modclkcfg_init_spi2(); +#endif + +#if defined(BSP_USING_UART0) + nutool_modclkcfg_init_uart0(); +#endif + +#if defined(BSP_USING_UART1) + nutool_modclkcfg_init_uart1(); +#endif + +#if defined(BSP_USING_UART2) + nutool_modclkcfg_init_uart2(); +#endif + +#if defined(BSP_USING_UART3) + nutool_modclkcfg_init_uart3(); +#endif + +#if defined(BSP_USING_UART4) + nutool_modclkcfg_init_uart4(); +#endif + +#if defined(BSP_USING_EADC0) + nutool_modclkcfg_init_eadc0(); +#endif + +#if defined(BSP_USING_I2S0) + nutool_modclkcfg_init_i2s0(); +#endif + +#if defined(BSP_USING_HSOTG) + nutool_modclkcfg_init_hsotg(); +#endif + +#if defined(BSP_USING_USCI0) + nutool_modclkcfg_init_usci0(); +#endif + +#if defined(BSP_USING_USCI1) + nutool_modclkcfg_init_usci1(); +#endif + +#if defined(BSP_USING_EPWM0) + nutool_modclkcfg_init_epwm0(); +#endif + +#if defined(BSP_USING_EPWM1) + nutool_modclkcfg_init_epwm1(); +#endif + +#if defined(BSP_USING_BPWM0) + nutool_modclkcfg_init_bpwm0(); +#endif + +#if defined(BSP_USING_BPWM1) + nutool_modclkcfg_init_bpwm1(); +#endif + +#if defined(BSP_USING_EQEI0) + nutool_modclkcfg_init_eqei0(); +#endif + +#if defined(BSP_USING_ECAP0) + nutool_modclkcfg_init_ecap0(); +#endif + +#if defined(BSP_USING_BPWM2) + nutool_modclkcfg_init_bpwm2(); +#endif + +#if defined(BSP_USING_BPWM3) + nutool_modclkcfg_init_bpwm3(); +#endif + +#if defined(BSP_USING_BPWM4) + nutool_modclkcfg_init_bpwm4(); +#endif + +#if defined(BSP_USING_BPWM5) + nutool_modclkcfg_init_bpwm5(); +#endif + +#if defined(BSP_USING_LLSI0) + nutool_modclkcfg_init_llsi0(); +#endif + +#if defined(BSP_USING_LLSI1) + nutool_modclkcfg_init_llsi1(); +#endif + +#if defined(BSP_USING_LLSI2) + nutool_modclkcfg_init_llsi2(); +#endif + +#if defined(BSP_USING_LLSI3) + nutool_modclkcfg_init_llsi3(); +#endif + +#if defined(BSP_USING_LLSI4) + nutool_modclkcfg_init_llsi4(); +#endif + +#if defined(BSP_USING_LLSI5) + nutool_modclkcfg_init_llsi5(); +#endif + +#if defined(BSP_USING_LLSI6) + nutool_modclkcfg_init_llsi6(); +#endif + +#if defined(BSP_USING_LLSI7) + nutool_modclkcfg_init_llsi7(); +#endif + +#if defined(BSP_USING_LLSI8) + nutool_modclkcfg_init_llsi8(); +#endif + +#if defined(BSP_USING_LLSI9) + nutool_modclkcfg_init_llsi9(); +#endif + +#if defined(BSP_USING_ELLSI0) + nutool_modclkcfg_init_ellsi0(); +#endif + + /* Update System Core Clock */ + SystemCoreClockUpdate(); +} + +void nutool_modclkcfg_deinit(void) +{ +#if defined(BSP_USING_PDMA0) + nutool_modclkcfg_deinit_pdma0(); +#endif + +#if defined(BSP_USING_ISP) + nutool_modclkcfg_deinit_isp(); +#endif + +#if defined(BSP_USING_EBI) + nutool_modclkcfg_deinit_ebi(); +#endif + +#if defined(BSP_USING_ST) + nutool_modclkcfg_deinit_st(); +#endif + +#if defined(BSP_USING_SDH0) + nutool_modclkcfg_deinit_sdh0(); +#endif + +#if defined(BSP_USING_CRC) + nutool_modclkcfg_deinit_crc(); +#endif + +#if defined(BSP_USING_CANFD0) + nutool_modclkcfg_deinit_canfd0(); +#endif + +#if defined(BSP_USING_CANFD1) + nutool_modclkcfg_deinit_canfd1(); +#endif + +#if defined(BSP_USING_HSOTG) + nutool_modclkcfg_init_hsotg(); +#endif +#if defined(BSP_USING_HSUSBD) + nutool_modclkcfg_init_hsusbd(); +#endif + +#if defined(BSP_USING_SPB) + nutool_modclkcfg_deinit_spb(); +#endif + +#if defined(BSP_USING_FMCIDLE) + nutool_modclkcfg_deinit_fmcidle(); +#endif + +#if defined(BSP_USING_USBH) || defined(BSP_USING_HSUSBH) + nutool_modclkcfg_deinit_usbh(); +#endif + +#if defined(BSP_USING_CANRAM0) + nutool_modclkcfg_deinit_canram0(); +#endif + +#if defined(BSP_USING_CANRAM1) + nutool_modclkcfg_deinit_canram1(); +#endif + +#if defined(BSP_USING_TRACE) + nutool_modclkcfg_deinit_trace(); +#endif + +#if defined(BSP_USING_GPIO) + nutool_modclkcfg_deinit_gpa(); + nutool_modclkcfg_deinit_gpb(); + nutool_modclkcfg_deinit_gpc(); + nutool_modclkcfg_deinit_gpd(); + nutool_modclkcfg_deinit_gpe(); + nutool_modclkcfg_deinit_gpf(); + nutool_modclkcfg_deinit_gpg(); + nutool_modclkcfg_deinit_gph(); +#endif + +#if defined(BSP_USING_WDT0) + nutool_modclkcfg_deinit_wdt0(); +#endif + +#if defined(BSP_USING_WDT1) + nutool_modclkcfg_deinit_wdt1(); +#endif + +#if defined(BSP_USING_WWDT0) + nutool_modclkcfg_deinit_wwdt0(); +#endif + +#if defined(BSP_USING_WWDT1) + nutool_modclkcfg_deinit_wwdt1(); +#endif + +#if defined(BSP_USING_RTC) + nutool_modclkcfg_deinit_rtc(); +#endif + +#if defined(BSP_USING_TMR0) + nutool_modclkcfg_deinit_tmr0(); +#endif + +#if defined(BSP_USING_TMR1) + nutool_modclkcfg_deinit_tmr1(); +#endif + +#if defined(BSP_USING_TMR2) + nutool_modclkcfg_deinit_tmr2(); +#endif + +#if defined(BSP_USING_TMR3) + nutool_modclkcfg_deinit_tmr3(); +#endif + +#if defined(BSP_USING_CLKO) + nutool_modclkcfg_deinit_clko(); +#endif + +#if defined(BSP_USING_ACMP01) + nutool_modclkcfg_deinit_acmp01(); +#endif + +#if defined(BSP_USING_I2C0) + nutool_modclkcfg_deinit_i2c0(); +#endif + +#if defined(BSP_USING_I2C1) + nutool_modclkcfg_deinit_i2c1(); +#endif + +#if defined(BSP_USING_I2C2) + nutool_modclkcfg_deinit_i2c2(); +#endif + +#if defined(BSP_USING_I3C0) + nutool_modclkcfg_deinit_i3c0(); +#endif + +#if defined(BSP_USING_QSPI0) + nutool_modclkcfg_deinit_qspi0(); +#endif + +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPII2S0) + nutool_modclkcfg_deinit_spi0(); +#endif + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPII2S1) + nutool_modclkcfg_deinit_spi1(); +#endif + +#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPII2S2) + nutool_modclkcfg_deinit_spi2(); +#endif + +#if defined(BSP_USING_UART0) + nutool_modclkcfg_deinit_uart0(); +#endif + +#if defined(BSP_USING_UART1) + nutool_modclkcfg_deinit_uart1(); +#endif + +#if defined(BSP_USING_UART2) + nutool_modclkcfg_deinit_uart2(); +#endif + +#if defined(BSP_USING_UART3) + nutool_modclkcfg_deinit_uart3(); +#endif + +#if defined(BSP_USING_UART4) + nutool_modclkcfg_deinit_uart4(); +#endif + +#if defined(BSP_USING_EADC0) + nutool_modclkcfg_deinit_eadc0(); +#endif + +#if defined(BSP_USING_I2S0) + nutool_modclkcfg_deinit_i2s0(); +#endif + +#if defined(BSP_USING_HSOTG) + nutool_modclkcfg_deinit_hsotg(); +#endif + +#if defined(BSP_USING_USCI0) + nutool_modclkcfg_deinit_usci0(); +#endif + +#if defined(BSP_USING_USCI1) + nutool_modclkcfg_deinit_usci1(); +#endif + +#if defined(BSP_USING_EPWM0) + nutool_modclkcfg_deinit_epwm0(); +#endif + +#if defined(BSP_USING_EPWM1) + nutool_modclkcfg_deinit_epwm1(); +#endif + +#if defined(BSP_USING_BPWM0) + nutool_modclkcfg_deinit_bpwm0(); +#endif + +#if defined(BSP_USING_BPWM1) + nutool_modclkcfg_deinit_bpwm1(); +#endif + +#if defined(BSP_USING_BPWM2) + nutool_modclkcfg_deinit_bpwm2(); +#endif + +#if defined(BSP_USING_BPWM3) + nutool_modclkcfg_deinit_bpwm3(); +#endif + +#if defined(BSP_USING_BPWM4) + nutool_modclkcfg_deinit_bpwm4(); +#endif + +#if defined(BSP_USING_BPWM5) + nutool_modclkcfg_deinit_bpwm5(); +#endif + +#if defined(BSP_USING_EQEI0) + nutool_modclkcfg_deinit_eqei0(); +#endif + +#if defined(BSP_USING_ECAP0) + nutool_modclkcfg_deinit_ecap0(); +#endif + +#if defined(BSP_USING_LLSI0) + nutool_modclkcfg_deinit_llsi0(); +#endif + +#if defined(BSP_USING_LLSI1) + nutool_modclkcfg_deinit_llsi1(); +#endif + +#if defined(BSP_USING_LLSI2) + nutool_modclkcfg_deinit_llsi2(); +#endif + +#if defined(BSP_USING_LLSI3) + nutool_modclkcfg_deinit_llsi3(); +#endif + +#if defined(BSP_USING_LLSI4) + nutool_modclkcfg_deinit_llsi4(); +#endif + +#if defined(BSP_USING_LLSI5) + nutool_modclkcfg_deinit_llsi5(); +#endif + +#if defined(BSP_USING_LLSI6) + nutool_modclkcfg_deinit_llsi6(); +#endif + +#if defined(BSP_USING_LLSI7) + nutool_modclkcfg_deinit_llsi7(); +#endif + +#if defined(BSP_USING_LLSI8) + nutool_modclkcfg_deinit_llsi8(); +#endif + +#if defined(BSP_USING_LLSI9) + nutool_modclkcfg_deinit_llsi9(); +#endif + +#if defined(BSP_USING_ELLSI0) + nutool_modclkcfg_deinit_ellsi0(); +#endif + + /* Update System Core Clock */ + SystemCoreClockUpdate(); +} + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.h b/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.h new file mode 100644 index 00000000000..2ddd8cb5af9 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/board/nutool_modclkcfg.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * @file nutool_modclkcfg.h + * @version V1.05 + * @Date 2020/11/11-11:43:32 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_MODCLKCFG_H__ +#define __NUTOOL_MODCLKCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_modclkcfg_init_base(void); +void nutool_modclkcfg_init(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_MODCLKCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.ld b/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.ld new file mode 100644 index 00000000000..2d3a2eb8abe --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.ld @@ -0,0 +1,247 @@ +PROVIDE(__STACK_SIZE = 0x00001000); +PROVIDE(__HEAP_SIZE = 0x00000000); + +/* System memory brief */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x50000 /* 320k */ +} + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + KEEP(*(CLINFO)) + *custom_loader.o(.text* .rodata*) + *startup_*.o(.text*) + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for cherryusb usb host class */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + *(.ctors) + + /* NN-Model section */ + *(nn_model) + + /* Label section*/ + *(labels) + + /* Label section*/ + *(ifm) + + KEEP(*(.eh_frame*)) + } > FLASH + + .rodata : { + . = ALIGN(8); + *(.rodata*) + . = ALIGN(8); + } >FLASH + + .rel.dyn : { + . = ALIGN(8); + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + . = ALIGN(8); + } > FLASH + + .dynsym : { + . = ALIGN(8); + __dynsym_start = .; + *(.dynsym) + __dynsym_end = .; + . = ALIGN(8); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__) / 4) + __zero_table_end__ = .; + } > FLASH + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Section to be copied - part 1: RW data for SRAM */ + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + __copy_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2 byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .stack (ORIGIN(SRAM)) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > SRAM + PROVIDE(__stack = __StackTop); + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > SRAM + + + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + PROVIDE(__ctors_start__ = .); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > SRAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > SRAM AT > SRAM +} diff --git a/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.sct b/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.sct new file mode 100644 index 00000000000..145c931f175 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/linking_scripts/M3331.sct @@ -0,0 +1,89 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x00080000 + +/*--------------------- Cacheable SRAM Configuration --------------------------- +; SRAM Configuration +; SRAM Size (in Bytes) <0x0-0x00150000:8> +; SRAM Base Address <0x20100000-0x2024FFFF:8> +; SRAM Size (in Bytes) <0x0-0x00150000:8> +; + *----------------------------------------------------------------------------*/ +#define SRAM_START 0x20000000 +#define SRAM_SIZE 0x00050000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define STACK_SIZE 0x00001000 +#define HEAP_SIZE 0x00000000 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +/* Starts at end*/ +#define __STACK_TOP (SRAM_START + SRAM_SIZE - 0) +/* Starts after RW_RAM section, 8 byte aligned */ +#define __HEAP_BASE (AlignExpr(+0, 8)) + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#define RO_ROM_BASE ( FLASH_START ) +#define RO_ROM_SIZE ( FLASH_SIZE ) + +#define RW_RAM_BASE ( SRAM_START ) +#define RW_RAM_SIZE ( SRAM_SIZE - STACK_SIZE - HEAP_SIZE ) + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM RO_ROM_BASE RO_ROM_SIZE { ; load region size_region + ER_ROM0 RO_ROM_BASE RO_ROM_SIZE { ; load address = execution address + startup_m3331.o (RESET, +First) + } + + ER_ROM1 AlignExpr(+0, 4) { ; load address = execution address + //*.o (CLINFO, +First) + //custom_loader.o (+RO) + startup_m3331.o (+RO) + + } + + ER_ROM2 AlignExpr(+0, 4) { ; load address = execution address + * (InRoot$$Sections) + ; Make sure reset_handler ends up in root segment + .ANY (+RO) + } + + RW_RAM RW_RAM_BASE RW_RAM_SIZE ; RW data + { + .ANY (+RW +ZI) + } + +#if HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY HEAP_SIZE {} ; Reserve empty region for heap +#endif + +#if STACK_SIZE > 0 + ARM_LIB_STACK __STACK_TOP EMPTY - STACK_SIZE {} ; Reserve empty region for stack +#endif +} \ No newline at end of file diff --git a/bsp/nuvoton/numaker-m3334ki/rtconfig.h b/bsp/nuvoton/numaker-m3334ki/rtconfig.h new file mode 100644 index 00000000000..02c5e37b37b --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/rtconfig.h @@ -0,0 +1,606 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 4 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ +#define RT_USING_FAL +#define FAL_USING_DEBUG +#define FAL_PART_HAS_TABLE_CFG +#define FAL_DEV_NAME_MAX 24 +#define FAL_DEV_BLK_MAX 6 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 2048 +#define RT_USING_CAN +#define RT_CANMSG_BOX_SZ 16 +#define RT_CANSND_BOX_NUM 1 +#define RT_CANSND_MSG_TIMEOUT 100 +#define RT_CAN_NB_TX_FIFO_SIZE 256 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_PULSE_ENCODER +#define RT_USING_INPUT_CAPTURE +#define RT_INPUT_CAPTURE_RB_SIZE 100 +#define RT_USING_PM +#define PM_TICKLESS_THRESHOLD_TIME 2 +#define RT_USING_RTC +#define RT_USING_SPI +#define RT_USING_SPI_ISR +#define RT_USING_QSPI +#define RT_USING_WDT +#define RT_USING_AUDIO +#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096 +#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2 +#define RT_AUDIO_RECORD_PIPE_SIZE 2048 +#define RT_USING_HWCRYPTO +#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto" +#define RT_HWCRYPTO_IV_MAX_SIZE 16 +#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256 +#define RT_HWCRYPTO_USING_CRC +#define RT_HWCRYPTO_USING_CRC_07 +#define RT_HWCRYPTO_USING_CRC_8005 +#define RT_HWCRYPTO_USING_CRC_1021 +#define RT_HWCRYPTO_USING_CRC_3D65 +#define RT_HWCRYPTO_USING_CRC_04C11DB7 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 1024 + +/* log format */ + +#define ULOG_USING_COLOR +#define ULOG_OUTPUT_TIME +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +/* end of log format */ +#define ULOG_BACKEND_USING_CONSOLE +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +#define PKG_USING_NUVOTON_CMSIS_DRIVER +#define PKG_USING_NUVOTON_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NUVOTON_SERIES_DRIVER +#define PKG_USING_NUVOTON_SERIES_DRIVER_LATEST_VERSION +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define SOC_FAMILY_NUMICRO +#define SOC_SERIES_M3331 +#define BSP_USING_BPWM +#define BSP_USING_BPWM_CAPTURE +#define BSP_USING_BPWM0 +#define BSP_USING_BPWM1_CAPTURE +#define BSP_USING_BPWM2 +#define BSP_USING_BPWM3 +#define BSP_USING_BPWM4 +#define BSP_USING_BPWM5 +#define BSP_USING_CANFD +#define BSP_USING_CANFD0 +#define BSP_USING_CANFD1 +#define BSP_USING_CLK +#define BSP_USING_CRC +#define BSP_USING_CRC0 +#define BSP_USING_CRYPTO +#define BSP_USING_CRYPTO0 +#define BSP_USING_EADC +#define BSP_USING_EADC0 +#define BSP_USING_EPWM +#define BSP_USING_EPWM0 +#define BSP_USING_EPWM1 +#define BSP_USING_EQEI +#define BSP_USING_EQEI0 +#define BSP_USING_EQEI1 +#define BSP_USING_EQEI2 +#define BSP_USING_EQEI3 +#define BSP_USING_FMC +#define BSP_USING_GPIO +#define BSP_USING_I2C +#define BSP_USING_I2C0 +#define BSP_USING_I2C1 +#define BSP_USING_I2C2 +#define BSP_USING_I2C3 +#define BSP_USING_PDMA +#define BSP_USING_PDMA0 +#define NU_PDMA_SGTBL_POOL_SIZE 16 +#define NU_PDMA_MEMFUN_ACTOR_MAX 2 +#define BSP_USING_QSPI +#define BSP_USING_QSPI0 +#define BSP_USING_QSPI0_PDMA +#define BSP_USING_RTC +#define BSP_USING_RTC_INTERNAL +#define BSP_USING_SC +#define BSP_USING_SC0 +#define BSP_USING_SC1 +#define BSP_USING_SC2 +#define BSP_USING_SPI +#define BSP_USING_SPI_PDMA +#define BSP_USING_SPII2S +#define BSP_USING_SPI0 +#define BSP_USING_SPI0_PDMA +#define BSP_USING_SPII2S1 +#define BSP_USING_SPI2 +#define BSP_USING_SPI2_PDMA +#define BSP_USING_TMR +#define BSP_USING_TIMER +#define BSP_USING_TPWM +#define BSP_USING_TMR0 +#define BSP_USING_TPWM0 +#define BSP_USING_TMR1 +#define BSP_USING_TIMER1 +#define BSP_USING_TMR2 +#define BSP_USING_TMR3 +#define BSP_USING_TPWM3 +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_UART1 +#define BSP_USING_UART2 +#define BSP_USING_UART3 +#define BSP_USING_UART4 +#define BSP_USING_UART5 +#define BSP_USING_USCI +#define BSP_USING_UUART +#define BSP_USING_USCI0 +#define BSP_USING_USCI1 +#define BSP_USING_UUART0 +#define BSP_USING_UUART0_TX_DMA +#define BSP_USING_UUART0_RX_DMA +#define BSP_USING_UUART1 +#define BSP_USING_UUART1_TX_DMA +#define BSP_USING_UUART1_RX_DMA +#define BSP_USING_HSUSBD +#define BSP_USING_HSUSBH +#define BSP_USING_HSOTG +#define BSP_USING_WDT +/* end of On-chip Peripheral Drivers */ + +/* On-board Peripheral Drivers */ + +#define BOARD_USING_NULINKME +#define BOARD_USING_USB_NONE +/* end of On-board Peripheral Drivers */ + +/* Board extended module drivers */ + +#define BOARD_USING_NONE +/* end of Board extended module drivers */ + +/* Nuvoton Packages Config */ + +#define NU_PKG_USING_UTILS +#define NU_PKG_USING_DEMO +/* end of Nuvoton Packages Config */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nuvoton/numaker-m3334ki/rtconfig.py b/bsp/nuvoton/numaker-m3334ki/rtconfig.py new file mode 100644 index 00000000000..012d8494e6b --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/rtconfig.py @@ -0,0 +1,100 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:\Keil_v5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +#BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -ffunction-sections -fdata-sections -Wuninitialized ' + CFLAGS = DEVICE + ' -Dgcc -Wno-unused-variable -Wno-unused-function -Wno-unused-but-set-variable ' + + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ./linking_scripts/M3331.ld' + CXXFLAGS = DEVICE + ' -std=c++14 ' + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + #M_BIN_PATH = r'z:\fatdisk\root' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os -g' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M33' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter ./linking_scripts/M3331.sct' + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nuvoton/numaker-m467hj/.config b/bsp/nuvoton/numaker-m467hj/.config index ab3b2d863d6..46c8107155a 100644 --- a/bsp/nuvoton/numaker-m467hj/.config +++ b/bsp/nuvoton/numaker-m467hj/.config @@ -116,7 +116,7 @@ CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-m467hj/config_lvgl b/bsp/nuvoton/numaker-m467hj/config_lvgl deleted file mode 100644 index ff2e60bf01b..00000000000 --- a/bsp/nuvoton/numaker-m467hj/config_lvgl +++ /dev/null @@ -1,1177 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=12 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMART is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=32 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT is not set -# CONFIG_RT_DEBUG_THREAD is not set -# CONFIG_RT_DEBUG_SCHEDULER is not set -# CONFIG_RT_DEBUG_IPC is not set -# CONFIG_RT_DEBUG_TIMER is not set -# CONFIG_RT_DEBUG_IRQ is not set -# CONFIG_RT_DEBUG_MEM is not set -# CONFIG_RT_DEBUG_SLAB is not set -# CONFIG_RT_DEBUG_MEMHEAP is not set -# CONFIG_RT_DEBUG_MODULE is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -CONFIG_RT_USING_SIGNALS=y - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50001 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=32 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=8 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=8 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=128 -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -# CONFIG_RT_CAN_USING_CANFD is not set -# CONFIG_RT_USING_CLOCK_TIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -CONFIG_RT_USING_SENSOR=y -# CONFIG_RT_USING_SENSOR_V2 is not set -CONFIG_RT_USING_SENSOR_CMD=y -CONFIG_RT_USING_TOUCH=y -CONFIG_RT_TOUCH_PIN_IRQ=y -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -# CONFIG_RT_USING_POSIX_STDIO is not set -# CONFIG_RT_USING_POSIX_POLL is not set -# CONFIG_RT_USING_POSIX_SELECT is not set -# CONFIG_RT_USING_POSIX_SOCKET is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_USING_LVGL_SQUARELINE is not set -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -# CONFIG_PKG_LVGL_USING_V08035 is not set -# CONFIG_PKG_LVGL_USING_V08034 is not set -# CONFIG_PKG_LVGL_USING_V08033 is not set -# CONFIG_PKG_LVGL_USING_V08032 is not set -# CONFIG_PKG_LVGL_USING_V08031 is not set -# CONFIG_PKG_LVGL_USING_V08030 is not set -# CONFIG_PKG_LVGL_USING_V08020 is not set -CONFIG_PKG_LVGL_USING_V8_3_LATEST_VERSION=y -# CONFIG_PKG_LVGL_USING_LATEST_VERSION is not set -CONFIG_PKG_LVGL_VER_NUM=0x0803F -CONFIG_PKG_LVGL_VER="v8.3-latest" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set -# CONFIG_PKG_USING_RT_TRACE is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_M460=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 -# CONFIG_BSP_USING_FMC is not set -CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_EMAC is not set -# CONFIG_BSP_USING_RTC is not set -# CONFIG_BSP_USING_CCAP is not set -# CONFIG_BSP_USING_DAC is not set -# CONFIG_BSP_USING_EADC is not set -# CONFIG_BSP_USING_TMR is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_UART6 is not set -# CONFIG_BSP_USING_UART7 is not set -# CONFIG_BSP_USING_UART8 is not set -# CONFIG_BSP_USING_UART9 is not set -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C0=y -CONFIG_BSP_USING_I2C1=y -CONFIG_BSP_USING_I2C2=y -CONFIG_BSP_USING_I2C3=y -# CONFIG_BSP_USING_I2C4 is not set -# CONFIG_BSP_USING_USCI is not set -# CONFIG_BSP_USING_SDH is not set -# CONFIG_BSP_USING_CANFD is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_EPWM is not set -# CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_I2S is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_SCUART is not set -# CONFIG_BSP_USING_ECAP is not set -# CONFIG_BSP_USING_EQEI is not set -# CONFIG_BSP_USING_CRYPTO is not set -# CONFIG_BSP_USING_TRNG is not set -# CONFIG_BSP_USING_CRC is not set -# CONFIG_BSP_USING_SOFT_I2C is not set -# CONFIG_BSP_USING_WDT is not set -CONFIG_BSP_USING_EBI=y -# CONFIG_BSP_USING_HBI is not set -# CONFIG_BSP_USING_USBD is not set -# CONFIG_BSP_USING_HSUSBD is not set -# CONFIG_BSP_USING_USBH is not set -# CONFIG_BSP_USING_HSUSBH is not set -# CONFIG_BSP_USING_HSOTG is not set - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_NULINKME=y -# CONFIG_BOARD_USING_RTL8201FI is not set -# CONFIG_BOARD_USING_NAU8822 is not set -# CONFIG_BOARD_USING_STORAGE_SDCARD is not set -# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set -# CONFIG_BOARD_USING_CANFD0 is not set -# CONFIG_BOARD_USING_EXTERNAL_HYPERRAM is not set -# CONFIG_BOARD_USING_NCT7717U is not set -# CONFIG_BOARD_USING_USB_D_H is not set - -# -# Board extended module drivers -# -# CONFIG_BOARD_USING_LCD_SSD1963 is not set -# CONFIG_BOARD_USING_ILI2130 is not set -CONFIG_BOARD_USING_LCD_FSA506=y -CONFIG_BOARD_USING_FSA506_EBI_PORT=0 -CONFIG_BOARD_USING_FSA506_PIN_BACKLIGHT=101 -CONFIG_BOARD_USING_FSA506_PIN_RESET=103 -CONFIG_BOARD_USING_FSA506_PIN_DC=119 -CONFIG_BOARD_USING_FSA506_PIN_DISPLAY=104 -CONFIG_BOARD_USING_ST1663I=y -# CONFIG_BOARD_USING_SENSOR0 is not set -CONFIG_BOARD_USING_SENSON0_ID= - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -# CONFIG_NU_PKG_USING_DEMO is not set -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -# CONFIG_NU_PKG_USING_NCT7717U is not set -# CONFIG_NU_PKG_USING_NAU88L25 is not set -# CONFIG_NU_PKG_USING_NAU8822 is not set -# CONFIG_NU_PKG_USING_DA9062 is not set -# CONFIG_NU_PKG_USING_ILI9341 is not set -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=480 -CONFIG_BSP_LCD_HEIGHT=272 -# CONFIG_NU_PKG_USING_SSD1963 is not set -CONFIG_NU_PKG_USING_FSA506=y -CONFIG_NU_PKG_USING_FSA506_EBI=y -CONFIG_NU_PKG_FSA506_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_FSA506_LINE_BUFFER_NUMBER=272 -CONFIG_NU_PKG_USING_TPC=y -# CONFIG_NU_PKG_USING_TPC_ILI is not set -# CONFIG_NU_PKG_USING_TPC_GT911 is not set -# CONFIG_NU_PKG_USING_TPC_FT5446 is not set -CONFIG_NU_PKG_USING_TPC_ST1663I=y -# CONFIG_NU_PKG_TPC_REVERSE_XY is not set -# CONFIG_NU_PKG_USING_ADC_TOUCH is not set -# CONFIG_NU_PKG_USING_SPINAND is not set diff --git a/bsp/nuvoton/numaker-m467hj/rtconfig.h b/bsp/nuvoton/numaker-m467hj/rtconfig.h index 8569f17b3bc..b7317368f80 100644 --- a/bsp/nuvoton/numaker-m467hj/rtconfig.h +++ b/bsp/nuvoton/numaker-m467hj/rtconfig.h @@ -72,7 +72,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 diff --git a/bsp/nuvoton/numaker-pfm-m487/.config b/bsp/nuvoton/numaker-pfm-m487/.config index dbda5cb2aef..4f80f81b049 100644 --- a/bsp/nuvoton/numaker-pfm-m487/.config +++ b/bsp/nuvoton/numaker-pfm-m487/.config @@ -106,7 +106,7 @@ # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set diff --git a/bsp/nuvoton/numaker-pfm-m487/config_lvgl b/bsp/nuvoton/numaker-pfm-m487/config_lvgl deleted file mode 100644 index c6b879ba153..00000000000 --- a/bsp/nuvoton/numaker-pfm-m487/config_lvgl +++ /dev/null @@ -1,892 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=12 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -CONFIG_RT_USING_SIGNALS=y - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_MEMHEAP_FAST_MODE=y -# CONFIG_RT_MEMHEAP_BSET_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=8 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_DFS_FD_MAX=32 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=8 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=128 -# CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_CLOCK_TIME=y -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -CONFIG_RT_USING_TOUCH=y -# CONFIG_RT_TOUCH_PIN_IRQ is not set -CONFIG_RT_USING_HWCRYPTO=y -CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" -CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 -CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 -# CONFIG_RT_HWCRYPTO_USING_GCM is not set -CONFIG_RT_HWCRYPTO_USING_AES=y -CONFIG_RT_HWCRYPTO_USING_AES_ECB=y -CONFIG_RT_HWCRYPTO_USING_AES_CBC=y -CONFIG_RT_HWCRYPTO_USING_AES_CFB=y -CONFIG_RT_HWCRYPTO_USING_AES_CTR=y -CONFIG_RT_HWCRYPTO_USING_AES_OFB=y -CONFIG_RT_HWCRYPTO_USING_DES=y -CONFIG_RT_HWCRYPTO_USING_DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_DES_CBC=y -CONFIG_RT_HWCRYPTO_USING_3DES=y -CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y -CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y -# CONFIG_RT_HWCRYPTO_USING_RC4 is not set -# CONFIG_RT_HWCRYPTO_USING_MD5 is not set -CONFIG_RT_HWCRYPTO_USING_SHA1=y -CONFIG_RT_HWCRYPTO_USING_SHA2=y -CONFIG_RT_HWCRYPTO_USING_SHA2_224=y -CONFIG_RT_HWCRYPTO_USING_SHA2_256=y -CONFIG_RT_HWCRYPTO_USING_SHA2_384=y -CONFIG_RT_HWCRYPTO_USING_SHA2_512=y -CONFIG_RT_HWCRYPTO_USING_RNG=y -CONFIG_RT_HWCRYPTO_USING_CRC=y -CONFIG_RT_HWCRYPTO_USING_CRC_07=y -CONFIG_RT_HWCRYPTO_USING_CRC_8005=y -CONFIG_RT_HWCRYPTO_USING_CRC_1021=y -# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set -CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y -# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -# CONFIG_RT_USING_POSIX_STDIO is not set -# CONFIG_RT_USING_POSIX_POLL is not set -# CONFIG_RT_USING_POSIX_SELECT is not set -# CONFIG_RT_USING_POSIX_SOCKET is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -CONFIG_RT_USING_UTEST=y -CONFIG_UTEST_THR_STACK_SIZE=4096 -CONFIG_UTEST_THR_PRIORITY=20 -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -CONFIG_PKG_USING_LVGL=y -CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" -CONFIG_PKG_LVGL_THREAD_PRIO=20 -CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 -CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30 -# CONFIG_PKG_LVGL_USING_EXAMPLES is not set -CONFIG_PKG_LVGL_USING_DEMOS=y -CONFIG_PKG_LVGL_VER_NUM=0x99999 -CONFIG_PKG_LVGL_VER="latest" -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# POSIX extension functions -# -# CONFIG_PKG_USING_POSIX_GETLINE is not set -# CONFIG_PKG_USING_POSIX_WCWIDTH is not set -# CONFIG_PKG_USING_POSIX_ITOA is not set -# CONFIG_PKG_USING_POSIX_STRINGS is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_M480=y -CONFIG_BSP_USE_STDDRIVER_SOURCE=y -CONFIG_BSP_USING_PDMA=y -CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 -# CONFIG_BSP_USING_FMC is not set -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_CLK=y -CONFIG_NU_CLK_INVOKE_WKTMR=y -# CONFIG_BSP_USING_EMAC is not set -CONFIG_BSP_USING_RTC=y -# CONFIG_NU_RTC_SUPPORT_IO_RW is not set -CONFIG_NU_RTC_SUPPORT_MSH_CMD=y -CONFIG_BSP_USING_EADC=y -CONFIG_BSP_USING_EADC0=y -# CONFIG_BSP_USING_EADC1 is not set -CONFIG_BSP_USING_TMR=y -# CONFIG_BSP_USING_TMR0 is not set -# CONFIG_BSP_USING_TMR1 is not set -# CONFIG_BSP_USING_TMR2 is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART0_TX_DMA is not set -# CONFIG_BSP_USING_UART0_RX_DMA is not set -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_UART6 is not set -# CONFIG_BSP_USING_UART7 is not set -CONFIG_BSP_USING_I2C=y -# CONFIG_BSP_USING_I2C0 is not set -CONFIG_BSP_USING_I2C1=y -CONFIG_BSP_USING_I2C2=y -# CONFIG_BSP_USING_USCI is not set -# CONFIG_BSP_USING_SDH is not set -# CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_BPWM is not set -# CONFIG_BSP_USING_EPWM is not set -CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI_PDMA is not set -# CONFIG_BSP_USING_SPII2S is not set -CONFIG_BSP_USING_SPI0_NONE=y -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPII2S0 is not set -CONFIG_BSP_USING_SPI1_NONE=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPII2S1 is not set -CONFIG_BSP_USING_SPI2_NONE=y -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPII2S2 is not set -# CONFIG_BSP_USING_SPI3_NONE is not set -CONFIG_BSP_USING_SPI3=y -# CONFIG_BSP_USING_SPII2S3 is not set -# CONFIG_BSP_USING_SPI3_PDMA is not set -# CONFIG_BSP_USING_I2S is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_SCUART is not set -# CONFIG_BSP_USING_ECAP is not set -# CONFIG_BSP_USING_QEI is not set -CONFIG_BSP_USING_CRYPTO=y -# CONFIG_NU_PRNG_USE_SEED is not set -# CONFIG_BSP_USING_TRNG is not set -# CONFIG_BSP_USING_CRC is not set -# CONFIG_BSP_USING_SOFT_I2C is not set -# CONFIG_BSP_USING_WDT is not set -CONFIG_BSP_USING_EBI=y -# CONFIG_BSP_USING_USBD is not set -# CONFIG_BSP_USING_HSUSBD is not set -# CONFIG_BSP_USING_USBH is not set -# CONFIG_BSP_USING_HSUSBH is not set -# CONFIG_BSP_USING_HSOTG is not set - -# -# On-board Peripheral Drivers -# -CONFIG_BSP_USING_NULINKME=y -# CONFIG_BOARD_USING_IP101GR is not set -# CONFIG_BOARD_USING_NAU88L25 is not set -# CONFIG_BOARD_USING_STORAGE_SDCARD is not set -# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set -# CONFIG_BOARD_USING_USB_D_H is not set - -# -# Board extended module drivers -# -CONFIG_BOARD_USING_ADVANCE_V4=y -# CONFIG_BOARD_USING_MAX31875 is not set -# CONFIG_BOARD_USING_MPU6500 is not set -CONFIG_BOARD_USING_LCD_ILI9341=y -CONFIG_BOARD_USING_ILI9341_EBI_PORT=0 -CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=23 -CONFIG_BOARD_USING_ILI9341_PIN_RESET=22 -CONFIG_BOARD_USING_ILI9341_PIN_DC=115 -# CONFIG_BOARD_USING_AT24LC64 is not set -CONFIG_BOARD_USING_SRAM0_AS_MEMHEAP=y -# CONFIG_BOARD_USING_BUZZER is not set - -# -# Nuvoton Packages Config -# -CONFIG_NU_PKG_USING_UTILS=y -# CONFIG_NU_PKG_USING_DEMO is not set -# CONFIG_NU_PKG_USING_LVGL is not set -# CONFIG_NU_PKG_USING_BMX055 is not set -# CONFIG_NU_PKG_USING_MAX31875 is not set -# CONFIG_NU_PKG_USING_NAU88L25 is not set -# CONFIG_NU_PKG_USING_NAU8822 is not set -# CONFIG_NU_PKG_USING_DA9062 is not set -CONFIG_NU_PKG_USING_ILI9341=y -# CONFIG_NU_PKG_USING_ILI9341_SPI is not set -CONFIG_NU_PKG_USING_ILI9341_EBI=y -CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y -CONFIG_NU_PKG_ILI9341_LINE_BUFFER_NUMBER=60 -CONFIG_NU_PKG_ILI9341_HORIZONTAL=y -CONFIG_BSP_LCD_BPP=16 -CONFIG_BSP_LCD_WIDTH=320 -CONFIG_BSP_LCD_HEIGHT=240 -# CONFIG_NU_PKG_USING_SSD1963 is not set -# CONFIG_NU_PKG_USING_FSA506 is not set -# CONFIG_NU_PKG_USING_TPC is not set -CONFIG_NU_PKG_USING_ADC_TOUCH=y -CONFIG_NU_PKG_USING_ADC_TOUCH_SW=y -# CONFIG_NU_PKG_USING_SPINAND is not set -CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." -CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-pfm-m487/rtconfig.h b/bsp/nuvoton/numaker-pfm-m487/rtconfig.h index b18e06ab2fb..09726be3842 100644 --- a/bsp/nuvoton/numaker-pfm-m487/rtconfig.h +++ b/bsp/nuvoton/numaker-pfm-m487/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 From 7c0b98c02e1b0e699a7835f356d2bbe85bc72b6d Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Wed, 29 Apr 2026 19:57:39 +0800 Subject: [PATCH 2/2] fix code format issue. --- .../m3331/rtt_port/cherryusb/msh_cmd.c | 14 +- .../m3331/rtt_port/cherryusb/usb_config.h | 308 +- .../m3331/rtt_port/cherryusb/usb_hs_dc.c | 2 +- .../m3331/rtt_port/cherryusb/usb_sw_otg.c | 2 +- .../libraries/m3331/rtt_port/drv_canfd.c | 16 +- .../libraries/m3331/rtt_port/drv_clk.c | 2 +- .../libraries/m3331/rtt_port/drv_common.c | 4 +- .../libraries/m3331/rtt_port/drv_crc.c | 2 +- .../libraries/m3331/rtt_port/drv_eqei.c | 4 +- .../libraries/m3331/rtt_port/drv_fmc.c | 18 +- .../libraries/m3331/rtt_port/drv_fmc.h | 2 +- .../libraries/m3331/rtt_port/drv_gpio.c | 6 +- .../libraries/m3331/rtt_port/drv_i2c.c | 14 +- .../libraries/m3331/rtt_port/drv_i2s.h | 6 +- .../libraries/m3331/rtt_port/drv_llsi.c | 4 +- .../libraries/m3331/rtt_port/drv_log.h | 8 +- .../libraries/m3331/rtt_port/drv_pdma.c | 41 +- .../libraries/m3331/rtt_port/drv_pdma.h | 2 +- .../libraries/m3331/rtt_port/drv_qspi.c | 6 +- .../libraries/m3331/rtt_port/drv_rtc.c | 2 +- .../libraries/m3331/rtt_port/drv_sdio.c | 12 +- .../libraries/m3331/rtt_port/drv_spi.c | 6 +- .../libraries/m3331/rtt_port/drv_spi.h | 10 +- .../libraries/m3331/rtt_port/drv_timer.c | 8 +- .../libraries/m3331/rtt_port/drv_uart.c | 18 +- .../libraries/m3331/rtt_port/drv_ui2c.c | 12 +- .../libraries/m3331/rtt_port/drv_uspi.c | 6 +- .../libraries/m3331/rtt_port/drv_uuart.c | 28 +- .../nu_packages/NuUtils/inc/nu_bitutil.h | 5 +- bsp/nuvoton/numaker-m3334ki/.config | 290 +- .../numaker-m3334ki/Nu_Link_Driver.ini | 1755 ++++++++++ bsp/nuvoton/numaker-m3334ki/SConstruct | 17 + .../numaker-m3334ki/board/custom_loader.c | 2 +- bsp/nuvoton/numaker-m3334ki/project.uvoptx | 2116 +++++++++++ bsp/nuvoton/numaker-m3334ki/project.uvprojx | 3116 +++++++++++++++++ bsp/nuvoton/numaker-m3334ki/rtconfig.h | 166 +- bsp/nuvoton/numaker-m467hj/rtconfig.h | 2 +- 37 files changed, 7479 insertions(+), 553 deletions(-) create mode 100644 bsp/nuvoton/numaker-m3334ki/Nu_Link_Driver.ini create mode 100644 bsp/nuvoton/numaker-m3334ki/project.uvoptx create mode 100644 bsp/nuvoton/numaker-m3334ki/project.uvprojx diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c index c1957aaafa3..8bac7544ef8 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/msh_cmd.c @@ -1,3 +1,10 @@ +/* Functions Implementation --------------------------------------------------*/ +/* + * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + /* Includes ------------------------------------------------------------------*/ #include "rtthread.h" #include "NuMicro.h" @@ -8,13 +15,6 @@ #define DBG_TAG LOG_TAG #include "drv_log.h" -/* Functions Implementation --------------------------------------------------*/ -/* - * @copyright (C) 2026 Nuvoton Technology Corp. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - #if defined(PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) void cdc_acm_init(uint8_t busid, uint32_t reg_base); diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h index c1dd12aae19..223ca6ec94c 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_config.h @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ - + #ifndef __USB_CONFIG_H__ #define __USB_CONFIG_H__ @@ -20,7 +20,7 @@ //#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG #if !defined(CONFIG_USB_DBG_LEVEL) -#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif /* Enable print with color */ @@ -34,8 +34,6 @@ /* attribute data into no cache ram */ #define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) - - #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip /* Ep0 max transfer buffer, specially for receiving data from ep0 out */ @@ -76,189 +74,189 @@ #endif #if !defined(CONFIG_USBDEV_MSC_MAX_LUN) -#define CONFIG_USBDEV_MSC_MAX_LUN 1 -#if !defined(CONFIG_USBDEV_MSC_MAX_BUFSIZE) -#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 -#endif + #define CONFIG_USBDEV_MSC_MAX_LUN 1 + #if !defined(CONFIG_USBDEV_MSC_MAX_BUFSIZE) + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 + #endif -#if !defined(CONFIG_USBDEV_MSC_MANUFACTURER_STRING) -#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" -#endif -#if !defined(CONFIG_USBDEV_MSC_PRODUCT_STRING) -#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" -#endif -#if !defined(CONFIG_USBDEV_MSC_VERSION_STRING) -#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" -#endif + #if !defined(CONFIG_USBDEV_MSC_MANUFACTURER_STRING) + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" + #endif + #if !defined(CONFIG_USBDEV_MSC_PRODUCT_STRING) + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" + #endif + #if !defined(CONFIG_USBDEV_MSC_VERSION_STRING) + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" + #endif -/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ -// #define CONFIG_USBDEV_MSC_POLLING + /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ + // #define CONFIG_USBDEV_MSC_POLLING -/* move msc read & write from isr to thread */ -#define CONFIG_USBDEV_MSC_THREAD + /* move msc read & write from isr to thread */ + #define CONFIG_USBDEV_MSC_THREAD -#if !defined(CONFIG_USBDEV_MSC_PRIO) -#define CONFIG_USBDEV_MSC_PRIO 4 -#endif -#if !defined(CONFIG_USBDEV_MSC_STACKSIZE) -#define CONFIG_USBDEV_MSC_STACKSIZE 2048 -#endif + #if !defined(CONFIG_USBDEV_MSC_PRIO) + #define CONFIG_USBDEV_MSC_PRIO 4 + #endif + #if !defined(CONFIG_USBDEV_MSC_STACKSIZE) + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 + #endif -#if !defined(CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE) -#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 -#endif + #if !defined(CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE) + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 + #endif -/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ -#if !defined(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE) -#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 -#endif + /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ + #if !defined(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE) + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 + #endif -#if !defined(CONFIG_USBDEV_RNDIS_VENDOR_ID) -#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff -#endif + #if !defined(CONFIG_USBDEV_RNDIS_VENDOR_ID) + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff + #endif -#if !defined(CONFIG_USBDEV_RNDIS_VENDOR_DESC) -#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" -#endif + #if !defined(CONFIG_USBDEV_RNDIS_VENDOR_DESC) + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" + #endif -#define CONFIG_USBDEV_RNDIS_USING_LWIP + #define CONFIG_USBDEV_RNDIS_USING_LWIP -#define CONFIG_USBHOST_MAX_RHPORTS 1 -#define CONFIG_USBHOST_MAX_EXTHUBS 4 -#define CONFIG_USBHOST_MAX_EHPORTS 8 -#define CONFIG_USBHOST_MAX_INTERFACES 8 -#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 -#define CONFIG_USBHOST_MAX_ENDPOINTS 8 + #define CONFIG_USBHOST_MAX_RHPORTS 1 + #define CONFIG_USBHOST_MAX_EXTHUBS 4 + #define CONFIG_USBHOST_MAX_EHPORTS 8 + #define CONFIG_USBHOST_MAX_INTERFACES 8 + #define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 + #define CONFIG_USBHOST_MAX_ENDPOINTS 8 -#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 -#define CONFIG_USBHOST_MAX_HID_CLASS 4 -#define CONFIG_USBHOST_MAX_MSC_CLASS 2 -#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 -#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 -#define CONFIG_USBHOST_MAX_RNDIS_CLASS 1 + #define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 + #define CONFIG_USBHOST_MAX_HID_CLASS 4 + #define CONFIG_USBHOST_MAX_MSC_CLASS 2 + #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 + #define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + #define CONFIG_USBHOST_MAX_RNDIS_CLASS 1 -#define CONFIG_USBHOST_DEV_NAMELEN 16 + #define CONFIG_USBHOST_DEV_NAMELEN 16 -#if !defined(CONFIG_USBHOST_PSC_PRIO) -#define CONFIG_USBHOST_PSC_PRIO 0 -#endif -#if !defined(CONFIG_USBHOST_PSC_STACKSIZE) -#define CONFIG_USBHOST_PSC_STACKSIZE 2048 -#endif + #if !defined(CONFIG_USBHOST_PSC_PRIO) + #define CONFIG_USBHOST_PSC_PRIO 0 + #endif + #if !defined(CONFIG_USBHOST_PSC_STACKSIZE) + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 + #endif -//#define CONFIG_USBHOST_GET_STRING_DESC + //#define CONFIG_USBHOST_GET_STRING_DESC -// #define CONFIG_USBHOST_MSOS_ENABLE -#if !defined(CONFIG_USBHOST_MSOS_VENDOR_CODE) -#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 -#endif + // #define CONFIG_USBHOST_MSOS_ENABLE + #if !defined(CONFIG_USBHOST_MSOS_VENDOR_CODE) + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 + #endif -/* Ep0 max transfer buffer */ -#if !defined(CONFIG_USBHOST_REQUEST_BUFFER_LEN) -#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 -#endif + /* Ep0 max transfer buffer */ + #if !defined(CONFIG_USBHOST_REQUEST_BUFFER_LEN) + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 + #endif -#if !defined(CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT) -#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 -#endif + #if !defined(CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT) + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 + #endif -#if !defined(CONFIG_USBHOST_MSC_TIMEOUT) -#define CONFIG_USBHOST_MSC_TIMEOUT 5000 -#endif + #if !defined(CONFIG_USBHOST_MSC_TIMEOUT) + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 + #endif -/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, - * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. - */ -#if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) -#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) -#endif + /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ + #if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) + #endif -/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ -#if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE) -#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) -#endif + /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ + #if !defined(CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE) + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) + #endif -/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, - * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. - */ -#if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) -#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) -#endif -/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ -#if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE) -#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) -#endif + /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ + #if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) + #endif + /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ + #if !defined(CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE) + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) + #endif -/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, - * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. - */ -#if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) -#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) -#endif -/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ -#if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE) -#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) -#endif + /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ + #if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) + #endif + /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ + #if !defined(CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE) + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) + #endif -/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, - * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. - */ -#if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) -#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) -#endif -/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ -#if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE) -#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) -#endif + /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ + #if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) + #endif + /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ + #if !defined(CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE) + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) + #endif -#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 -// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 + // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG -#if !defined(CONFIG_USBHOST_BLUETOOTH_TX_SIZE) -#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 -#endif -#if !defined(CONFIG_USBHOST_BLUETOOTH_RX_SIZE) -#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 -#endif + #if !defined(CONFIG_USBHOST_BLUETOOTH_TX_SIZE) + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 + #endif + #if !defined(CONFIG_USBHOST_BLUETOOTH_RX_SIZE) + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 + #endif -#if !defined(CONFIG_USB_HS) -#define CONFIG_USB_HS -#endif + #if !defined(CONFIG_USB_HS) + #define CONFIG_USB_HS + #endif -#if !defined(CONFIG_USBDEV_EP_NUM) - #define CONFIG_USBDEV_EP_NUM 8 -#endif -#if !defined(CONFIG_USBHOST_MAX_BUS) -#define CONFIG_USBHOST_MAX_BUS 1 -#endif + #if !defined(CONFIG_USBDEV_EP_NUM) + #define CONFIG_USBDEV_EP_NUM 8 + #endif + #if !defined(CONFIG_USBHOST_MAX_BUS) + #define CONFIG_USBHOST_MAX_BUS 1 + #endif -#if !defined(CONFIG_USBHOST_PIPE_NUM) -#define CONFIG_USBHOST_PIPE_NUM 10 -#endif + #if !defined(CONFIG_USBHOST_PIPE_NUM) + #define CONFIG_USBHOST_PIPE_NUM 10 + #endif -/* ---------------- EHCI Configuration ---------------- */ -#define CONFIG_USB_EHCI_HCCR_OFFSET (0) -#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 -#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM -#define CONFIG_USB_EHCI_QTD_NUM 3 -#define CONFIG_USB_EHCI_ITD_NUM 20 -// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE -#define CONFIG_USB_EHCI_CONFIGFLAG -// #define CONFIG_USB_EHCI_ISO -//#define CONFIG_USB_EHCI_WITH_OHCI - -/* ---------------- OHCI Configuration ---------------- */ -#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) - -#if !defined(usb_phyaddr2ramaddr) -#define usb_phyaddr2ramaddr(addr) (addr) -#endif + /* ---------------- EHCI Configuration ---------------- */ + #define CONFIG_USB_EHCI_HCCR_OFFSET (0) + #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 + #define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USB_EHCI_QTD_NUM 3 + #define CONFIG_USB_EHCI_ITD_NUM 20 + // #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE + #define CONFIG_USB_EHCI_CONFIGFLAG + // #define CONFIG_USB_EHCI_ISO + //#define CONFIG_USB_EHCI_WITH_OHCI + + /* ---------------- OHCI Configuration ---------------- */ + #define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + + #if !defined(usb_phyaddr2ramaddr) + #define usb_phyaddr2ramaddr(addr) (addr) + #endif -#if !defined(usb_ramaddr2phyaddr) -#define usb_ramaddr2phyaddr(addr) (addr) -#endif + #if !defined(usb_ramaddr2phyaddr) + #define usb_ramaddr2phyaddr(addr) (addr) + #endif #endif diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c index 6de0b43a7e4..c287e5f3457 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_hs_dc.c @@ -931,7 +931,7 @@ static void process_epxif(uint8_t busid) if ((u32Len < s_sUDC.ep[HWEP].ep_mps) || (s_sUDC.ep[HWEP].xfer_len == 0)) - { + { usbd_event_ep_out_complete_handler(busid, SWEP, s_sUDC.ep[HWEP].actual_xfer_len); } else diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c index 0d7fa12a607..9672e57a45b 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/cherryusb/usb_sw_otg.c @@ -53,7 +53,7 @@ static int isConnectedUSBRole(const rt_int16_t *cc_sum) /* Check if CC1+CC2 voltage is within the threshold range. */ if ((cc_sum[role] >= s_swotg_ccx_threshold[role][0]) && (cc_sum[role] <= s_swotg_ccx_threshold[role][1])) - { + { /* Found the connected USB role */ return role; } diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c index 22c61b919d2..234165ee5e9 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_canfd.c @@ -146,14 +146,14 @@ static const char *szIR[] = /* Functions Implementation --------------------------------------------------*/ #if defined(BSP_USING_CANFD0) -/* CAN0 interrupt entry */ -DEFINE_CANFD_IRQ_HANDLER(00, 0) -DEFINE_CANFD_IRQ_HANDLER(01, 0) + /* CAN0 interrupt entry */ + DEFINE_CANFD_IRQ_HANDLER(00, 0) + DEFINE_CANFD_IRQ_HANDLER(01, 0) #endif #if defined(BSP_USING_CANFD1) -DEFINE_CANFD_IRQ_HANDLER(10, 1) -DEFINE_CANFD_IRQ_HANDLER(11, 1) + DEFINE_CANFD_IRQ_HANDLER(10, 1) + DEFINE_CANFD_IRQ_HANDLER(11, 1) #endif static void dump_interrupt_event(uint32_t u32Status) @@ -479,7 +479,7 @@ static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg) (argval == RT_CAN_MODE_LISTEN) || (argval == RT_CAN_MODE_LOOPBACK) || (argval == RT_CAN_MODE_LOOPBACKANLISTEN)) - { + { if (argval != can->config.mode) { can->config.mode = argval; @@ -504,7 +504,7 @@ static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg) (argval == CAN50kBaud) || (argval == CAN20kBaud) || (argval == CAN10kBaud)) - { + { if (argval != can->config.baud_rate) { can->config.baud_rate = argval; @@ -522,7 +522,7 @@ static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg) { if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV) - { + { return -(RT_ERROR); } if (argval != can->config.privmode) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c index e4b18ce378c..534e8963b12 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_clk.c @@ -46,7 +46,7 @@ * CLK_PMUCTL_WKTMRIS_2097152 - Select Wake-up Timer Time-out Interval is 2097152 LIRC clocks (65536 ms) * CLK_PMUCTL_WKTMRIS_4194304 - Select Wake-up Timer Time-out Interval is 4194304 LIRC clocks (131072 ms) */ -#define WKTMR_INTERVAL (CLK_PMUCTL_WKTMRIS_131072) + #define WKTMR_INTERVAL (CLK_PMUCTL_WKTMRIS_131072) #endif /* Timer module assigned for pm device usage. */ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c index 4b01e2a2e6f..7c5c9db72f8 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_common.c @@ -161,11 +161,11 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_err_t ret = RT_EOK; struct rt_spi_device *spi_device = (struct rt_spi_device *) -rt_malloc(sizeof(struct rt_spi_device)); + rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); rt_uint32_t *cs_pin = (rt_uint32_t *) -rt_malloc(sizeof(rt_uint32_t)); + rt_malloc(sizeof(rt_uint32_t)); RT_ASSERT(cs_pin != RT_NULL); *cs_pin = pin; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c index 6ec19a5ef20..42eb93b461a 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_crc.c @@ -78,7 +78,7 @@ static rt_uint32_t nu_crc_run( uint32_t u32Attr, uint8_t *pu8InData, uint32_t u32DataLen) - { +{ uint32_t u32CalChecksum = 0; uint32_t i = 0; rt_err_t result; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c index b71b95f909e..40a1336b2cc 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_eqei.c @@ -98,11 +98,11 @@ static const struct rt_pulse_encoder_ops nu_eqei_ops = /* Functions Implementation --------------------------------------------------*/ #if defined(BSP_USING_EQEI0) && defined(EQEI0) -DEFINE_EQEI_IRQ_HANDLER(0) + DEFINE_EQEI_IRQ_HANDLER(0) #endif #if defined(BSP_USING_EQEI1) && defined(EQEI1) -DEFINE_EQEI_IRQ_HANDLER(1) + DEFINE_EQEI_IRQ_HANDLER(1) #endif static rt_uint32_t nu_eqei_type(struct rt_pulse_encoder_device *pulse_encoder) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c index bb44621508b..567fa5b4b3a 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.c @@ -35,17 +35,17 @@ /* Static Function Prototypes ------------------------------------------------*/ #if defined(RT_USING_FAL) -static int aprom_read(long offset, uint8_t *buf, size_t size); -static int aprom_write(long offset, const uint8_t *buf, size_t size); -static int aprom_erase(long offset, size_t size); + static int aprom_read(long offset, uint8_t *buf, size_t size); + static int aprom_write(long offset, const uint8_t *buf, size_t size); + static int aprom_erase(long offset, size_t size); -static int ldrom_read(long offset, uint8_t *buf, size_t size); -static int ldrom_write(long offset, const uint8_t *buf, size_t size); -static int ldrom_erase(long offset, size_t size); + static int ldrom_read(long offset, uint8_t *buf, size_t size); + static int ldrom_write(long offset, const uint8_t *buf, size_t size); + static int ldrom_erase(long offset, size_t size); -static int dataflash_read(long offset, uint8_t *buf, size_t size); -static int dataflash_write(long offset, const uint8_t *buf, size_t size); -static int dataflash_erase(long offset, size_t size); + static int dataflash_read(long offset, uint8_t *buf, size_t size); + static int dataflash_write(long offset, const uint8_t *buf, size_t size); + static int dataflash_erase(long offset, size_t size); #endif /* RT_USING_FAL */ static int nu_fmc_init(void); diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h index 0b16d76bb4d..6f4343b52c5 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_fmc.h @@ -9,7 +9,7 @@ #include "rtthread.h" #if defined(RT_USING_FAL) -#include "fal.h" + #include "fal.h" extern const struct fal_flash_dev g_falFMC_AP; extern const struct fal_flash_dev g_falFMC_LD; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c index 45dec56d915..2b2a7e5ccf9 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_gpio.c @@ -40,7 +40,7 @@ void GP##_port##_IRQHandler(void) \ } #if !defined(GPIO_PIN_DATA) -#define GPIO_PIN_DATA GPIO_PIN_DATA_S + #define GPIO_PIN_DATA GPIO_PIN_DATA_S #endif /* Types / Structures ---------------------------------------------------------*/ @@ -48,7 +48,7 @@ void GP##_port##_IRQHandler(void) \ /* Static Function Prototypes ------------------------------------------------*/ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static int nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -202,7 +202,7 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static int nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) return PIN_LOW; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c index a40c387a387..bed92f02a8b 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2c.c @@ -125,7 +125,7 @@ static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t nu_i2c, rt_uint8_t data) static rt_err_t nu_i2c_send_address(nu_i2c_bus_t nu_i2c, struct rt_i2c_msg *msg) - { +{ rt_uint16_t flags = msg->flags; rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; rt_uint8_t addr1, addr2; @@ -206,7 +206,7 @@ static rt_err_t nu_i2c_send_address(nu_i2c_bus_t nu_i2c, if ((I2C_GET_STATUS(nu_i2c->base) != ((flags & RT_I2C_RD) ? NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK)) && !ignore_nack) - { + { //LOG_E("sending address failed\n"); return -RT_EIO; } @@ -216,9 +216,9 @@ static rt_err_t nu_i2c_send_address(nu_i2c_bus_t nu_i2c, } static rt_ssize_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) - { + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ struct rt_i2c_msg *msg; nu_i2c_bus_t nu_i2c; rt_size_t i; @@ -269,7 +269,7 @@ static rt_ssize_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg)) && !ignore_nack) - { + { i = 0; //LOG_E("Send Address Fail"); break; @@ -327,7 +327,7 @@ static rt_ssize_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, if (I2C_GET_STATUS(nu_i2c->base) != NU_I2C_MASTER_STATUS_TRANSMIT_DATA_ACK && !ignore_nack ) /* Send aata and get Ack */ - { + { i = 0; break; } diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h index 26c4f01b7fc..709587c4520 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_i2s.h @@ -11,11 +11,11 @@ #include "drv_pdma.h" #if !defined(NU_I2S_DMA_FIFO_SIZE) -#define NU_I2S_DMA_FIFO_SIZE (RT_AUDIO_RECORD_PIPE_SIZE) + #define NU_I2S_DMA_FIFO_SIZE (RT_AUDIO_RECORD_PIPE_SIZE) #endif #if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER) - -#define NU_I2S_DMA_BUF_BLOCK_NUMBER (2) + + #define NU_I2S_DMA_BUF_BLOCK_NUMBER (2) #endif #if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 ) #error "Please give an aligned definition" diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c index 0110defef4c..fdb15ce3342 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_llsi.c @@ -24,9 +24,9 @@ #define MAKE_PDMA_ELLSI_TX(x) PDMA_ELLSI##x##_TX #if defined(BSP_USING_PDMA_LLSI_TX) -#define MAKE_LLSI_PDMA_TX_REQ(t) .pdma_perp_tx = t + #define MAKE_LLSI_PDMA_TX_REQ(t) .pdma_perp_tx = t #else -#define MAKE_LLSI_PDMA_TX_REQ(t) + #define MAKE_LLSI_PDMA_TX_REQ(t) #endif #define MAKE_LLSI_INSTANCE(x, t) \ { \ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h index b5e835774e3..70c3dedc3b3 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_log.h @@ -9,15 +9,15 @@ */ #ifndef LOG_TAG -#define DBG_TAG "drv" + #define DBG_TAG "drv" #else -#define DBG_TAG LOG_TAG + #define DBG_TAG LOG_TAG #endif /* LOG_TAG */ #ifdef DRV_DEBUG -#define DBG_LVL DBG_LOG + #define DBG_LVL DBG_LOG #else -#define DBG_LVL DBG_INFO + #define DBG_LVL DBG_INFO #endif /* DRV_DEBUG */ #include diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c index c8ee51a6e19..ccad27a7051 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.c @@ -22,7 +22,7 @@ #include "drv_log.h" #ifndef NU_PDMA_MEMFUN_ACTOR_MAX -#define NU_PDMA_MEMFUN_ACTOR_MAX (4) + #define NU_PDMA_MEMFUN_ACTOR_MAX (4) #endif #define NU_PDMA_SG_TBL_MAXSIZE (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T)) @@ -289,8 +289,6 @@ void nu_pdma_channel_terminate(int i32ModChnID) if (nu_pdma_check_is_nonallocated(i32ModChnID)) goto exit_pdma_channel_terminate; - LOG_I("[%s] %d", __func__, i32ModChnID); - /* Reset specified channel. */ nu_pdma_channel_reset(i32ModChnID); @@ -323,8 +321,8 @@ static rt_err_t nu_pdma_timeout_set(int i32ModChnID, int i32Timeout_us) uint32_t u32Divider = (i32Timeout_us / u32ToClk_Max) / (1 << 16); uint32_t u32TOutCnt = (i32Timeout_us / u32ToClk_Max) % (1 << 16); - LOG_I("CLK_GetHCLKFreq(): %d, u32ToClk_Max: %d, u32Divider: %d, u32TOutCnt:%d", - CLK_GetHCLKFreq(), u32ToClk_Max, u32Divider, u32TOutCnt); + //LOG_I("CLK_GetHCLKFreq(): %d, u32ToClk_Max: %d, u32Divider: %d, u32TOutCnt:%d", + // CLK_GetHCLKFreq(), u32ToClk_Max, u32Divider, u32TOutCnt); PDMA_DisableTimeout(pdma, 1 << u32ModChannId); PDMA_EnableInt(pdma, u32ModChannId, PDMA_INT_TIMEOUT); // Interrupt type @@ -616,7 +614,7 @@ static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu } rt_err_t nu_pdma_desc_setup(int i32ModChnID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent) - { +{ nu_pdma_periph_ctl_t *psPeriphCtl = NULL; PDMA_T *pdma = NULL; int isPdmaDescReg = 0; @@ -790,7 +788,7 @@ static rt_err_t nu_pdma_sgtbls_valid(int i32ModChnID, nu_pdma_desc_t head) { rt_kprintf("The distance is over %d between 0x%08x and 0x%08x. \n", NU_PDMA_SG_LIMITED_DISTANCE, pdma->SCATBA, node); rt_kprintf("Please use nu_pdma_sgtbl_allocate to allocate valid sg-table.\n"); - return RT_ERROR; + return -RT_ERROR; } node = (nu_pdma_desc_t)(node->NEXT + pdma->SCATBA); @@ -836,6 +834,7 @@ static void _nu_pdma_sgtbls_free(int i32ModChnID, nu_pdma_chn_t *psPdmaChann) if (psPdmaChann->m_ppsSgtbl) { nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + rt_free_align((void *)psPdmaChann->m_ppsSgtbl); psPdmaChann->m_ppsSgtbl = RT_NULL; psPdmaChann->m_u32WantedSGTblNum = 0; } @@ -855,19 +854,15 @@ static rt_err_t _nu_pdma_transfer_chain(int i32ModChnID, uint32_t u32DataWidth, psPeriphCtl = &psPdmaChann->m_spPeripCtl; - if (psPdmaChann->m_u32WantedSGTblNum != (u32TransferCnt / NU_PDMA_MAX_TXCNT + 1)) - { - if (psPdmaChann->m_u32WantedSGTblNum > 0) - { - nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); - _nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann); - } + uint32_t needed = (u32TransferCnt / NU_PDMA_MAX_TXCNT + 1); - psPdmaChann->m_u32WantedSGTblNum = u32TransferCnt / NU_PDMA_MAX_TXCNT + 1; + if (needed > psPdmaChann->m_u32WantedSGTblNum) + { + _nu_pdma_sgtbls_free(i32ModChnID, psPdmaChann); + psPdmaChann->m_u32WantedSGTblNum = needed; psPdmaChann->m_ppsSgtbl = (nu_pdma_desc_t *) -rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 32); - + rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 32); if (!psPdmaChann->m_ppsSgtbl) goto exit__nu_pdma_transfer_chain; @@ -876,7 +871,7 @@ rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 32); goto exit__nu_pdma_transfer_chain; } - for (i = 0; i < psPdmaChann->m_u32WantedSGTblNum; i++) + for (i = 0; i < needed; i++) { u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt; @@ -886,8 +881,8 @@ rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 32); (eMemCtl & 0x2ul) ? u32AddrSrc + u32Offset : u32AddrSrc, /* Src address is Inc or not. */ (eMemCtl & 0x1ul) ? u32AddrDst + u32Offset : u32AddrDst, /* Dst address is Inc or not. */ u32TxCnt, - ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? RT_NULL : psPdmaChann->m_ppsSgtbl[i + 1], - ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? 0 : 1); // Silent, w/o TD interrupt + ((i + 1) == needed) ? RT_NULL : psPdmaChann->m_ppsSgtbl[i + 1], + ((i + 1) == needed) ? 0 : 1); // Silent, w/o TD interrupt if (ret != RT_EOK) goto exit__nu_pdma_transfer_chain; @@ -1084,7 +1079,7 @@ static void nu_pdma_memfun_actor_init(void) else break; } - if (i) + if (i > 0) { nu_pdma_memfun_actor_maxnum = i; nu_pdma_memfun_actor_mask = ~(((1 << i) - 1)); @@ -1116,7 +1111,7 @@ static int nu_pdma_memfun_employ(void) /* Headhunter */ if (nu_pdma_memfun_actor_pool_sem && ((result = rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER)) == RT_EOK)) - { + { RT_ASSERT(result == RT_EOK); result = rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); @@ -1231,7 +1226,7 @@ void *nu_pdma_memcpy(void *dest, void *src, unsigned int count) if (((u32src % i) == (u32dest % i)) && ((u32src % i) == 0) && (RT_ALIGN_DOWN(u32Remaining, i) >= i)) - { + { uint32_t u32TXCnt = u32Remaining / i; if (u32TXCnt != nu_pdma_memfun((void *)u32dest, (void *)u32src, i * 8, u32TXCnt, eMemCtl_SrcInc_DstInc)) goto exit_nu_pdma_memcpy; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h index 19b5da2216a..5c8af25ac60 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_pdma.h @@ -11,7 +11,7 @@ #include "NuMicro.h" #ifndef NU_PDMA_SGTBL_POOL_SIZE -#define NU_PDMA_SGTBL_POOL_SIZE (16) + #define NU_PDMA_SGTBL_POOL_SIZE (16) #endif enum diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c index 062ba753f68..016efc943d8 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_qspi.c @@ -73,7 +73,7 @@ static struct nu_spi nu_qspi_arr [] = /* Functions Implementation --------------------------------------------------*/ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) - { +{ struct nu_spi *spi_bus; rt_uint32_t u32SPIMode; rt_uint32_t u32BusClock; @@ -107,7 +107,7 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, configuration->data_width == 16 || configuration->data_width == 24 || configuration->data_width == 32)) - { + { ret = RT_EINVAL; goto exit_nu_qspi_bus_configure; } @@ -389,7 +389,7 @@ rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4); qspi_device = (struct rt_qspi_device *) -rt_malloc(sizeof(struct rt_qspi_device)); + rt_malloc(sizeof(struct rt_qspi_device)); if (qspi_device == RT_NULL) { LOG_E("no memory, qspi bus attach device failed!\n"); diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c index 4b470ff6e3b..b82aee24e01 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_rtc.c @@ -48,7 +48,7 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args); static rt_err_t nu_rtc_is_date_valid(const time_t t); static rt_err_t nu_rtc_init(void); #if defined(RT_USING_ALARM) -static void nu_rtc_alarm_reset(void); + static void nu_rtc_alarm_reset(void); #endif /* Static Variables ----------------------------------------------------------*/ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c index aa248173f97..231ae0ebdc7 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_sdio.c @@ -19,9 +19,9 @@ #include "drv_log.h" #if defined(RT_USING_CACHE) -#define SDH_ALIGN_LEN 32 + #define SDH_ALIGN_LEN 32 #else -#define SDH_ALIGN_LEN 4 + #define SDH_ALIGN_LEN 4 #endif #define SDH_BUFF_SIZE 512 #define SDH_SetClock SDH_Set_clock @@ -78,7 +78,7 @@ static int SDH_GetBusStatus(SDH_T *sdh, uint32_t mask); /* Static Variables ----------------------------------------------------------*/ #if defined(BSP_USING_SDH0) -static uint32_t g_au32CacheBuf_SDH0[SDH_BUFF_SIZE / 4]; + static uint32_t g_au32CacheBuf_SDH0[SDH_BUFF_SIZE / 4]; #endif static struct nu_sdh nu_sdh_arr [] = @@ -119,7 +119,7 @@ static int SDH_GetBusStatus(SDH_T *sdh, uint32_t mask) { sdh->CTL |= SDH_CTL_CLK8OEN_Msk; while (sdh->CTL & SDH_CTL_CLK8OEN_Msk) -{ } + { } if (SDH_GET_INT_FLAG(sdh, SDH_INTSTS_DAT0STS_Msk)) break; @@ -646,11 +646,11 @@ static void nu_sdh_isr(nu_sdh_t NuSdh) } #if defined(BSP_USING_SDH0) -DEFINE_SDH_IRQ_HANDLER(0) + DEFINE_SDH_IRQ_HANDLER(0) #endif #if defined(BSP_USING_SDH1) -DEFINE_SDH_IRQ_HANDLER(1) + DEFINE_SDH_IRQ_HANDLER(1) #endif /** diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c index 60648cd4b60..41822b43e52 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.c @@ -116,7 +116,7 @@ void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int lengt void nu_spi_drain_rxfifo(SPI_T *spi_base); static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) - { +{ struct nu_spi *spi_bus; uint32_t u32SPIMode; uint32_t u32BusClock; @@ -152,7 +152,7 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, configuration->data_width == 16 || configuration->data_width == 24 || configuration->data_width == 32)) - { + { ret = RT_EINVAL; goto exit_nu_spi_bus_configure; } @@ -491,7 +491,7 @@ static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes */ static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) - { +{ SPI_T *spi_base = spi_bus->spi_base; // Write-only diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h index 615f74f7e06..16c29b22f84 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_spi.h @@ -12,12 +12,12 @@ #include "NuMicro.h" #include "nu_bitutil.h" #if defined(BSP_USING_SPI_PDMA) - -#include "drv_pdma.h" + + #include "drv_pdma.h" #endif #ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD - -#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) + + #define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) #endif struct nu_spi @@ -26,7 +26,7 @@ struct nu_spi char *name; SPI_T *spi_base; uint32_t rstidx; - uint32_t* dummy; + uint32_t *dummy; #if defined(BSP_USING_SPI_PDMA) int32_t pdma_perp_tx; int32_t pdma_chanid_tx; diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c index a0ebc34dcb2..d5a75af3fca 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_timer.c @@ -265,19 +265,19 @@ static int rt_hw_timer_init(void) INIT_BOARD_EXPORT(rt_hw_timer_init); #if defined(BSP_USING_TIMER0) -DEFINE_TIMER_IRQ_HANDLER(0) + DEFINE_TIMER_IRQ_HANDLER(0) #endif #if defined(BSP_USING_TIMER1) -DEFINE_TIMER_IRQ_HANDLER(1) + DEFINE_TIMER_IRQ_HANDLER(1) #endif #if defined(BSP_USING_TIMER2) -DEFINE_TIMER_IRQ_HANDLER(2) + DEFINE_TIMER_IRQ_HANDLER(2) #endif #if defined(BSP_USING_TIMER3) -DEFINE_TIMER_IRQ_HANDLER(3) + DEFINE_TIMER_IRQ_HANDLER(3) #endif #endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c index da61a899b9a..5bca8440658 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uart.c @@ -29,14 +29,14 @@ #define CONFIG_UART_USE_IDLE_TIMER #if defined(CONFIG_UART_USE_IDLE_TIMER) -#define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE) -#define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk) -#define CONFIG_UART_IDLE_TIMEOUT_VALUE (50) -#define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (0) + #define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE) + #define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk) + #define CONFIG_UART_IDLE_TIMEOUT_VALUE (50) + #define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (0) #else -#define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) -#define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk) -#define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (1000000 * 10 * (1 + psNuUart->dev.config.data_bits + (psNuUart->dev.config.stop_bits + 1)) / psNuUart->dev.config.baud_rate) + #define CONFIG_PDMA_USE_IT (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) + #define CONFIG_UART_USE_RXDMA_IT (UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk) + #define CONFIG_PDMA_IDLE_TIMEOUT_VALUE (1000000 * 10 * (1 + psNuUart->dev.config.data_bits + (psNuUart->dev.config.stop_bits + 1)) / psNuUart->dev.config.baud_rate) #endif #define CONFIG_UART_USE_TXDMA_IT (UART_INTEN_TXPDMAEN_Msk) #define MAKE_UART_NAME(x) #x @@ -220,7 +220,9 @@ static struct nu_uart nu_uart_arr [] = #endif ) #endif - {0} + { + 0 + } }; /* Functions Implementation --------------------------------------------------*/ diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c index dd9b105babb..a9d3041a262 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_ui2c.c @@ -97,7 +97,7 @@ static rt_err_t nu_ui2c_wait_ready_with_timeout(nu_ui2c_t psNuUi2c) UI2C_PROTSTS_ACKIF_Msk | UI2C_PROTSTS_NACKIF_Msk | UI2C_PROTSTS_STORIF_Msk)) == 0) - { + { if ((rt_tick_get() - start) > psNuUi2c->parent.timeout) { LOG_E("timeout! (%d - %d > %d) ProtSts=0x%08x", rt_tick_get(), start, psNuUi2c->parent.timeout, u32ProtSts); @@ -118,7 +118,7 @@ static rt_err_t nu_ui2c_send_data(nu_ui2c_t psNuUi2c, rt_uint8_t data) static rt_err_t nu_ui2c_send_address(nu_ui2c_t psNuUi2c, struct rt_i2c_msg *msg) - { +{ rt_uint16_t flags = msg->flags; rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; rt_uint8_t addr1, addr2; @@ -202,7 +202,7 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_t psNuUi2c, if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) - { + { LOG_E("sending addr fail\n"); return -RT_EIO; } @@ -215,7 +215,7 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_t psNuUi2c, static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) - { +{ struct rt_i2c_msg *msg; rt_size_t i = 0; rt_uint32_t cnt_data; @@ -269,7 +269,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, if ((RT_EOK != nu_ui2c_send_address(psNuUi2c, msg)) && !ignore_nack) - { + { i = 0; //LOG_E("Send Address Fail"); break; @@ -331,7 +331,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, if (((UI2C_GET_PROT_STATUS(psNuUi2c->base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack ) /* Send data and get Ack */ - { + { i = 0; break; } diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c index 792839b36f8..a4961eb2c56 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uspi.c @@ -22,7 +22,7 @@ #include "drv_log.h" #ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD -#define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) + #define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) #endif #if defined(BSP_USING_USPI_PDMA) @@ -121,7 +121,7 @@ static struct nu_uspi nu_uspi_arr [] = /* Functions Implementation --------------------------------------------------*/ static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) - { +{ struct nu_uspi *uspi_bus; uint32_t u32SPIMode; uint32_t u32BusClock; @@ -155,7 +155,7 @@ static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, } if (!(configuration->data_width == 8 || configuration->data_width == 16)) - { + { ret = RT_EINVAL; goto exit_nu_uspi_bus_configure; } diff --git a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c index 623e2f4b38f..8b45cec52ee 100644 --- a/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c +++ b/bsp/nuvoton/libraries/m3331/rtt_port/drv_uuart.c @@ -21,9 +21,9 @@ #if defined(RT_SERIAL_USING_DMA) #if defined(BSP_USING_UUART0_TX_DMA) -#define UUART0_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI0_TX, + #define UUART0_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI0_TX, #else -#define UUART0_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, + #define UUART0_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, #endif #if defined(BSP_USING_UUART0_RX_DMA) #define UUART0_DMA_RX_INIT .pdma_perp_rx = PDMA_USCI0_RX, \ @@ -33,9 +33,9 @@ #endif #if defined(BSP_USING_UUART1_TX_DMA) -#define UUART1_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI1_TX, + #define UUART1_DMA_TX_INIT .pdma_perp_tx = PDMA_USCI1_TX, #else -#define UUART1_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, + #define UUART1_DMA_TX_INIT .pdma_perp_tx = NU_PDMA_UNUSED, #endif #if defined(BSP_USING_UUART1_RX_DMA) #define UUART1_DMA_RX_INIT .pdma_perp_rx = PDMA_USCI1_RX, \ @@ -134,33 +134,33 @@ static struct nu_uuart nu_uuart_arr [] = #if defined(BSP_USING_UUART0) DEFINE_NU_UUART(0, USCI0_RST, USCI0_IRQn, #if defined(RT_SERIAL_USING_DMA) - UUART0_DMA_TX_INIT, - UUART0_DMA_RX_INIT + UUART0_DMA_TX_INIT, + UUART0_DMA_RX_INIT #else - , + , #endif - ), + ), #endif #if defined(BSP_USING_UUART1) DEFINE_NU_UUART(1, USCI1_RST, USCI1_IRQn, #if defined(RT_SERIAL_USING_DMA) - UUART1_DMA_TX_INIT, - UUART1_DMA_RX_INIT + UUART1_DMA_TX_INIT, + UUART1_DMA_RX_INIT #else - , + , #endif - ), + ), #endif }; /* uuart nu_uuart */ /* Functions Implementation --------------------------------------------------*/ #if defined(BSP_USING_UUART0) -DEFINE_UUART_IRQ_HANDLER(0) + DEFINE_UUART_IRQ_HANDLER(0) #endif #if defined(BSP_USING_UUART1) -DEFINE_UUART_IRQ_HANDLER(1) + DEFINE_UUART_IRQ_HANDLER(1) #endif /** diff --git a/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h index fa067348379..6a61c1b7841 100644 --- a/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h +++ b/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/nu_bitutil.h @@ -21,9 +21,8 @@ #endif #endif - #if !defined(__CLZ) - #define __CLZ __clz - #endif +#elif defined (__GNUC__) + #define __CLZ __builtin_clz #endif #include diff --git a/bsp/nuvoton/numaker-m3334ki/.config b/bsp/nuvoton/numaker-m3334ki/.config index 390681ad51f..5fea1a246f6 100644 --- a/bsp/nuvoton/numaker-m3334ki/.config +++ b/bsp/nuvoton/numaker-m3334ki/.config @@ -294,80 +294,31 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=2048 # CONFIG_RT_USING_SERIAL_BYPASS is not set -CONFIG_RT_USING_CAN=y -# CONFIG_RT_CAN_USING_HDR is not set -# CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_CANMSG_BOX_SZ=16 -CONFIG_RT_CANSND_BOX_NUM=1 -CONFIG_RT_CANSND_MSG_TIMEOUT=100 -CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 -# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set +# CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CLOCK_TIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set -CONFIG_RT_USING_PWM=y -CONFIG_RT_USING_PULSE_ENCODER=y -CONFIG_RT_USING_INPUT_CAPTURE=y -CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100 +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -CONFIG_RT_USING_SPI_ISR=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_SOFT_SPI is not set -CONFIG_RT_USING_QSPI=y -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -CONFIG_RT_USING_WDT=y -CONFIG_RT_USING_AUDIO=y -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 -CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 -CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set -CONFIG_RT_USING_HWCRYPTO=y -CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" -CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 -CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 -# CONFIG_RT_HWCRYPTO_USING_GCM is not set -# CONFIG_RT_HWCRYPTO_USING_AES is not set -# CONFIG_RT_HWCRYPTO_USING_DES is not set -# CONFIG_RT_HWCRYPTO_USING_3DES is not set -# CONFIG_RT_HWCRYPTO_USING_RC4 is not set -# CONFIG_RT_HWCRYPTO_USING_MD5 is not set -# CONFIG_RT_HWCRYPTO_USING_SHA1 is not set -# CONFIG_RT_HWCRYPTO_USING_SHA2 is not set -# CONFIG_RT_HWCRYPTO_USING_RNG is not set -CONFIG_RT_HWCRYPTO_USING_CRC=y -CONFIG_RT_HWCRYPTO_USING_CRC_07=y -CONFIG_RT_HWCRYPTO_USING_CRC_8005=y -CONFIG_RT_HWCRYPTO_USING_CRC_1021=y -CONFIG_RT_HWCRYPTO_USING_CRC_3D65=y -CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y -# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set +# CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set @@ -478,7 +429,11 @@ CONFIG_ULOG_BACKEND_USING_CONSOLE=y # CONFIG_ULOG_BACKEND_USING_FILE is not set # CONFIG_ULOG_USING_FILTER is not set # CONFIG_ULOG_USING_SYSLOG is not set -# CONFIG_RT_USING_UTEST is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_UTEST_USING_AUTO_RUN is not set +CONFIG_RT_UTEST_MAX_OPTIONS=64 # CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set @@ -499,7 +454,98 @@ CONFIG_ULOG_BACKEND_USING_CONSOLE=y # # RT-Thread Utestcases # -# CONFIG_RT_USING_UTESTCASES is not set +CONFIG_RT_USING_UTESTCASES=y + +# +# Kernel Core +# +# CONFIG_RT_UTEST_MEMHEAP is not set +# CONFIG_RT_UTEST_SMALL_MEM is not set +# CONFIG_RT_UTEST_OBJECT is not set +# CONFIG_RT_UTEST_IRQ is not set +# CONFIG_RT_UTEST_SEMAPHORE is not set +# CONFIG_RT_UTEST_EVENT is not set +# CONFIG_RT_UTEST_TIMER is not set +# CONFIG_RT_UTEST_MESSAGEQUEUE is not set +# CONFIG_RT_UTEST_SIGNAL is not set +# CONFIG_RT_UTEST_MUTEX is not set +# CONFIG_RT_UTEST_MAILBOX is not set +# CONFIG_RT_UTEST_THREAD is not set +# CONFIG_RT_UTEST_ATOMIC is not set +# CONFIG_RT_UTEST_HOOKLIST is not set +# CONFIG_RT_UTEST_MTSAFE_KPRINT is not set +# CONFIG_RT_UTEST_SCHEDULER is not set +# CONFIG_RT_UTEST_MEMPOOL is not set +# CONFIG_RT_UTEST_SYS_PERF is not set +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of Kernel Core + +# +# Kernel Components +# + +# +# Drivers +# +# CONFIG_RT_UTEST_DRIVERS_CORE is not set + +# +# IPC Test +# +# CONFIG_RT_UTEST_COMPLETION is not set +# CONFIG_RT_UTEST_WORKQUEUE is not set +# end of IPC Test + +# +# Serial Test +# +# end of Serial Test + +# +# SMP-Call Test +# +# end of SMP-Call Test +# end of Drivers + +# +# File System +# +# CONFIG_RT_UTEST_TC_USING_DFS_API is not set +# end of File System + +# +# CPP11 +# +# CONFIG_RT_UTEST_CPP11_THREAD is not set +# end of CPP11 + +# +# Network +# +# CONFIG_RT_UTEST_TC_USING_SAL is not set +# CONFIG_RT_UTEST_TC_USING_NETDEV is not set +# CONFIG_RT_UTEST_TC_USING_LWIP is not set +# end of Network + +# +# Utest Framework +# +CONFIG_RT_UTEST_SELF_PASS=y +# end of Utest Framework +# end of Kernel Components + +# +# Memory Management Subsytem Testcase +# +# CONFIG_RT_UTEST_MM_API is not set +# CONFIG_RT_UTEST_MM_LWP is not set +# end of Memory Management Subsytem Testcase + +# +# Tmpfs Testcase +# +# CONFIG_RT_UTEST_TMPFS_CP is not set +# end of Tmpfs Testcase # end of RT-Thread Utestcases # @@ -1580,106 +1626,41 @@ CONFIG_PKG_NUVOTON_SERIES_DRIVER_VER="latest" # CONFIG_SOC_FAMILY_NUMICRO=y CONFIG_SOC_SERIES_M3331=y -CONFIG_BSP_USING_BPWM=y -CONFIG_BSP_USING_BPWM_CAPTURE=y -CONFIG_BSP_USING_BPWM0=y -# CONFIG_BSP_USING_BPWM0_CAPTURE is not set -CONFIG_BSP_USING_BPWM1_CAPTURE=y -CONFIG_BSP_USING_BPWM2=y -# CONFIG_BSP_USING_BPWM2_CAPTURE is not set -CONFIG_BSP_USING_BPWM3=y -# CONFIG_BSP_USING_BPWM3_CAPTURE is not set -CONFIG_BSP_USING_BPWM4=y -# CONFIG_BSP_USING_BPWM4_CAPTURE is not set -CONFIG_BSP_USING_BPWM5=y -# CONFIG_BSP_USING_BPWM5_CAPTURE is not set -CONFIG_BSP_USING_CANFD=y -CONFIG_BSP_USING_CANFD0=y -CONFIG_BSP_USING_CANFD1=y -CONFIG_BSP_USING_CLK=y -CONFIG_BSP_USING_CRC=y -CONFIG_BSP_USING_CRC0=y -CONFIG_BSP_USING_CRYPTO=y -CONFIG_BSP_USING_CRYPTO0=y -CONFIG_BSP_USING_EADC=y -CONFIG_BSP_USING_EADC0=y +# CONFIG_BSP_USING_BPWM is not set +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_CLK is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_CRYPTO is not set +# CONFIG_BSP_USING_EADC is not set # CONFIG_BSP_USING_EBI is not set -CONFIG_BSP_USING_EPWM=y -CONFIG_BSP_USING_EPWM0=y -# CONFIG_BSP_USING_EPWM0_CAPTURE is not set -CONFIG_BSP_USING_EPWM1=y -# CONFIG_BSP_USING_EPWM1_CAPTURE is not set -CONFIG_BSP_USING_EQEI=y -CONFIG_BSP_USING_EQEI0=y -CONFIG_BSP_USING_EQEI1=y -CONFIG_BSP_USING_EQEI2=y -CONFIG_BSP_USING_EQEI3=y +# CONFIG_BSP_USING_EPWM is not set +# CONFIG_BSP_USING_EQEI is not set CONFIG_BSP_USING_FMC=y CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C0=y -CONFIG_BSP_USING_I2C1=y -CONFIG_BSP_USING_I2C2=y -CONFIG_BSP_USING_I2C3=y +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_LPADC is not set # CONFIG_BSP_USING_LPTMR is not set CONFIG_BSP_USING_PDMA=y CONFIG_BSP_USING_PDMA0=y CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16 CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 -CONFIG_BSP_USING_QSPI=y -CONFIG_BSP_USING_QSPI0=y -CONFIG_BSP_USING_QSPI0_PDMA=y -CONFIG_BSP_USING_RTC=y -CONFIG_BSP_USING_RTC_INTERNAL=y -CONFIG_BSP_USING_SC=y -CONFIG_BSP_USING_SC0=y -CONFIG_BSP_USING_SC1=y -CONFIG_BSP_USING_SC2=y -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI_PDMA=y -CONFIG_BSP_USING_SPII2S=y -CONFIG_BSP_USING_SPI0=y -# CONFIG_BSP_USING_SPII2S0 is not set -CONFIG_BSP_USING_SPI0_PDMA=y -CONFIG_BSP_USING_SPII2S1=y -CONFIG_BSP_USING_SPI2=y -# CONFIG_BSP_USING_SPII2S2 is not set -CONFIG_BSP_USING_SPI2_PDMA=y -CONFIG_BSP_USING_TMR=y -CONFIG_BSP_USING_TIMER=y -CONFIG_BSP_USING_TPWM=y -CONFIG_BSP_USING_TMR0=y -CONFIG_BSP_USING_TPWM0=y -CONFIG_BSP_USING_TMR1=y -CONFIG_BSP_USING_TIMER1=y -# CONFIG_BSP_USING_TPWM1 is not set -CONFIG_BSP_USING_TMR2=y -# CONFIG_BSP_USING_TIMER2 is not set -# CONFIG_BSP_USING_TPWM2 is not set -CONFIG_BSP_USING_TMR3=y -CONFIG_BSP_USING_TPWM3=y +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_TMR is not set CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y -CONFIG_BSP_USING_UART1=y -CONFIG_BSP_USING_UART2=y -CONFIG_BSP_USING_UART3=y -CONFIG_BSP_USING_UART4=y -CONFIG_BSP_USING_UART5=y -CONFIG_BSP_USING_USCI=y -CONFIG_BSP_USING_UUART=y -CONFIG_BSP_USING_USCI0=y -CONFIG_BSP_USING_USCI1=y -CONFIG_BSP_USING_UUART0=y -CONFIG_BSP_USING_UUART0_TX_DMA=y -CONFIG_BSP_USING_UUART0_RX_DMA=y -CONFIG_BSP_USING_UUART1=y -CONFIG_BSP_USING_UUART1_TX_DMA=y -CONFIG_BSP_USING_UUART1_RX_DMA=y -CONFIG_BSP_USING_HSUSBD=y -CONFIG_BSP_USING_HSUSBH=y -CONFIG_BSP_USING_HSOTG=y -CONFIG_BSP_USING_WDT=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_USCI is not set +# CONFIG_BSP_USING_HSUSBD is not set +# CONFIG_BSP_USING_HSUSBH is not set +# CONFIG_BSP_USING_HSOTG is not set +# CONFIG_BSP_USING_WDT is not set # end of On-chip Peripheral Drivers # @@ -1706,7 +1687,7 @@ CONFIG_BOARD_USING_NONE=y # Nuvoton Packages Config # CONFIG_NU_PKG_USING_UTILS=y -CONFIG_NU_PKG_USING_DEMO=y +# CONFIG_NU_PKG_USING_DEMO is not set # CONFIG_NU_PKG_USING_BMX055 is not set # CONFIG_NU_PKG_USING_MAX31875 is not set # CONFIG_NU_PKG_USING_NCT7717U is not set @@ -1721,3 +1702,6 @@ CONFIG_NU_PKG_USING_DEMO=y # CONFIG_NU_PKG_USING_SPINAND is not set # end of Nuvoton Packages Config # end of Hardware Drivers Config + +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-m3334ki/Nu_Link_Driver.ini b/bsp/nuvoton/numaker-m3334ki/Nu_Link_Driver.ini new file mode 100644 index 00000000000..e372291e9a4 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/Nu_Link_Driver.ini @@ -0,0 +1,1755 @@ +[Version] +Nu_LinkVersion=V6.24 +[Process] +ProcessID=0x00007070 +ProcessCreationTime_L=0x08fc89b9 +ProcessCreationTime_H=0x01dcd7ce +NuLinkID=0x7788ff78 +DisableFirmwareUpdate=0 +NuLinkIDs_Count=0x00000001 +NuLinkID0=0x7788ff78 +[ChipSelect] +;ChipName= +ChipName=M3331 +[NUC505] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC505_SPIFLASH.FLM +[NUC4xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC400_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x014fb180 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[NUC2xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC200_AP_128.FLM +[NUC1311] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC1311_AP_64.FLM +[NUC1263] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC1263_AP_64.FLM +[NUC126] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC126_AP_256.FLM +[NUC121] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC121_AP_32.FLM +[NUC1xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC100_AP_128.FLM +[NUC029] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NUC029_AP_16.FLM +[NM1820] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1820_AP_17_5.FLM +[NM1810] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1810_AP_29_5.FLM +[NM1500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1500_AP_128.FLM +[NM1330] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1330_AP_64.FLM +[NM1320] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1320_AP_32.FLM +[NM1240] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1240_AP_64.FLM +[NM1230] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1230_AP_64.FLM +[NM1200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1200_AP_8.FLM +[NM1120] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1120_AP_29_5.FLM +[N32F030] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N32F030_AP_64.FLM +[TF5100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=TF5100_AP_64.FLM +[NDA102] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NDA102_AP_29_5.FLM +[Nano103] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano103_AP_64.FLM +[Nano100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano100_AP_64.FLM +[NSC74] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NSC74_AP_512.FLM +[NSC] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NSC_AP_320.FLM +[N577] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=N577_AP_512.FLM +[N576] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N576_AP_145.FLM +[N575] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N575_AP_145.FLM +[N574] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N574_AP_512.FLM +[N572] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N572Fxxx.FLM +[N571] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N571E000.FLM +[N570] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N570_AP_64.FLM +[N569] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N569_AP_64.FLM +[N512] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N512_AP_64.FLM +[Mini57] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini57_AP_29_5.FLM +[Mini51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini51_AP_16.FLM +[M55M1] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +SPIM=0 +SPIMOption=0xAD000000 +OTFC_Ctrl=0x00000000 +OTFC0_Addr=0x00000000 +OTFC0_Size=0x00000000 +OTFC0_Key0=0x00000000 +OTFC0_Key1=0x00000000 +OTFC0_Key2=0x00000000 +OTFC0_Key3=0x00000000 +OTFC0_ScrambleKey=0x00000000 +OTFC0_Nonce0=0x00000000 +OTFC0_Nonce1=0x00000000 +OTFC0_Nonce2=0x00000000 +OTFC1_Addr=0x00000000 +OTFC1_Size=0x00000000 +OTFC1_Key0=0x00000000 +OTFC1_Key1=0x00000000 +OTFC1_Key2=0x00000000 +OTFC1_Key3=0x00000000 +OTFC1_ScrambleKey=0x00000000 +OTFC1_Nonce0=0x00000000 +OTFC1_Nonce1=0x00000000 +OTFC1_Nonce2=0x00000000 +OTFC2_Addr=0x00000000 +OTFC2_Size=0x00000000 +OTFC2_Key0=0x00000000 +OTFC2_Key1=0x00000000 +OTFC2_Key2=0x00000000 +OTFC2_Key3=0x00000000 +OTFC2_ScrambleKey=0x00000000 +OTFC2_Nonce0=0x00000000 +OTFC2_Nonce1=0x00000000 +OTFC2_Nonce2=0x00000000 +OTFC3_Addr=0x00000000 +OTFC3_Size=0x00000000 +OTFC3_Key0=0x00000000 +OTFC3_Key1=0x00000000 +OTFC3_Key2=0x00000000 +OTFC3_Key3=0x00000000 +OTFC3_ScrambleKey=0x00000000 +OTFC3_Nonce0=0x00000000 +OTFC3_Nonce1=0x00000000 +OTFC3_Nonce2=0x00000000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +CheckDPM=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M55M1_AP_2M.FLM +ProgramAlgorithm1=M55M1_SPIM.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M5531] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +SPIM=0 +SPIMOption=0xAD000000 +OTFC_Ctrl=0x00000000 +OTFC0_Addr=0x00000000 +OTFC0_Size=0x00000000 +OTFC0_Key0=0x00000000 +OTFC0_Key1=0x00000000 +OTFC0_Key2=0x00000000 +OTFC0_Key3=0x00000000 +OTFC0_ScrambleKey=0x00000000 +OTFC0_Nonce0=0x00000000 +OTFC0_Nonce1=0x00000000 +OTFC0_Nonce2=0x00000000 +OTFC1_Addr=0x00000000 +OTFC1_Size=0x00000000 +OTFC1_Key0=0x00000000 +OTFC1_Key1=0x00000000 +OTFC1_Key2=0x00000000 +OTFC1_Key3=0x00000000 +OTFC1_ScrambleKey=0x00000000 +OTFC1_Nonce0=0x00000000 +OTFC1_Nonce1=0x00000000 +OTFC1_Nonce2=0x00000000 +OTFC2_Addr=0x00000000 +OTFC2_Size=0x00000000 +OTFC2_Key0=0x00000000 +OTFC2_Key1=0x00000000 +OTFC2_Key2=0x00000000 +OTFC2_Key3=0x00000000 +OTFC2_ScrambleKey=0x00000000 +OTFC2_Nonce0=0x00000000 +OTFC2_Nonce1=0x00000000 +OTFC2_Nonce2=0x00000000 +OTFC3_Addr=0x00000000 +OTFC3_Size=0x00000000 +OTFC3_Key0=0x00000000 +OTFC3_Key1=0x00000000 +OTFC3_Key2=0x00000000 +OTFC3_Key3=0x00000000 +OTFC3_ScrambleKey=0x00000000 +OTFC3_Nonce0=0x00000000 +OTFC3_Nonce1=0x00000000 +OTFC3_Nonce2=0x00000000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +CheckDPM=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M5531_AP_2M.FLM +ProgramAlgorithm1=M5531_SPIM.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M481] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M481_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M480LD] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M480LD_AP_256.FLM +[M479] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M479_AP_256.FLM +[M471] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M471_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M460] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +SPIM=0 +SPIMOption=0xAD000000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm=M460_AP_1M.FLM +ProgramAlgorithm1=M460_SPIM_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M451] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M451_AP_256.FLM +[M433] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M433_AP_128.FLM +[M3351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M3351_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M3331] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M3331_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M2U51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1800 +ProgramAlgorithm=M2U51_AP_256.FLM +[M2L31] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm=M2L31_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M2354] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +CheckDPM=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2354_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M2351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2351_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M261] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M261_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M251] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M251_AP_192.FLM +[MR63] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=MR63_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M2A23] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M2A23_AP_256.FLM +[M2003] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M2003_AP_32.FLM +[M091] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +DisableTimeoutDetect=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M091_AP_64.FLM +[M071] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M071_AP_128.FLM +[M0564] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M0564_AP_256.FLM +[M0519] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0519_AP_128.FLM +[M0518] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0518_AP_64.FLM +[M05x] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0516_AP_64.FLM +[M0A86] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0A86_AP_64.FLM +[M0A21] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0A21_AP_32.FLM +[M031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M031_AP_128.FLM +[M030G] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +DisableTimeoutDetect=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M030G_AP_64.FLM +[NPCX] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NPCX_AP_512.FLM +[KM1M7C] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M7C_I.FLM +ProgramAlgorithm1=KM1M7C_D0.FLM +ProgramAlgorithm2=KM1M7C_D1.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[KM1M7A/B] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=5000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M7AFxxx_I.FLM +ProgramAlgorithm1=KM1M7AFxxx_D.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[KM1M4B] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=5000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M4B_I.FLM +ProgramAlgorithm1=KM1M4B_D.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[KM1M3E] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M3E1_APROM.FLM +ProgramAlgorithm1=KM1M3E1_DATA.FLM +ProgramAlgorithm2=KM1M3E1_APROM_NS.FLM +ProgramAlgorithm3=KM1M3E1_DATA_NS.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +EnableKeyfile_ns=0 +Keycode0_ns=0xFFFFFFFF +Keycode1_ns=0xFFFFFFFF +Keycode2_ns=0xFFFFFFFF +Keycode3_ns=0xFFFFFFFF +[KM1M2] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=KM1M2_AP_1M.FLM +[KM1M0G] +Connect=2 +Reset=HWRESET +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=5000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M0G_I.FLM +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[KM1M0D] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=5000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M0D_I.FLM +ProgramAlgorithm1=KM1M0D_D.FLM +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[I96000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=2 +Program=0 +Verify=0 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm= +[I94000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=I94000_AP_512.FLM +[I91500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I91500_AP_64.FLM +[ISD9300] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9300_AP_145.FLM +[I9200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I9200_AP_128.FLM +[ISD9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9100_AP_145.FLM +[ISD9000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9000_AP_64.FLM +[CM3031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=CM3031_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[CM2U51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1800 +ProgramAlgorithm=CM2U51_AP_256.FLM +[CM2052] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=CM2052_AP_128.FLM +[CM2003] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=CM2003_AP_32.FLM +[AU9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=AU9100_AP_145.FLM +[Autodetect] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= +[General] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 diff --git a/bsp/nuvoton/numaker-m3334ki/SConstruct b/bsp/nuvoton/numaker-m3334ki/SConstruct index f54828241c9..109dba2eecd 100644 --- a/bsp/nuvoton/numaker-m3334ki/SConstruct +++ b/bsp/nuvoton/numaker-m3334ki/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nuvoton-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) TARGET = 'rtthread.' + rtconfig.TARGET_EXT diff --git a/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c b/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c index b8816782c3f..f4edac04dd5 100644 --- a/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c +++ b/bsp/nuvoton/numaker-m3334ki/board/custom_loader.c @@ -17,7 +17,7 @@ #include "NuMicro.h" #ifndef __CUSTOM_LOADER_INFO_ATTRIBUTE -#define __CUSTOM_LOADER_INFO_ATTRIBUTE __attribute__((used, section("CLINFO"))) + #define __CUSTOM_LOADER_INFO_ATTRIBUTE __attribute__((used, section("CLINFO"))) #endif /* Use an unsigned integer number as version number. */ diff --git a/bsp/nuvoton/numaker-m3334ki/project.uvoptx b/bsp/nuvoton/numaker-m3334ki/project.uvoptx new file mode 100644 index 00000000000..f626dde5366 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/project.uvoptx @@ -0,0 +1,2116 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + rtthread-m3331 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil5\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 19 + + + + + + + + + + + Bin\Nu_Link.dll + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC4000 -FN3 -FF0M3331_AP_512 -FS00 -FL080000 -FF1M3331_LD_8 -FS1F100000 -FL12000 -FF2M3331_NS_512 -FS210000000 -FL280000 -FP0($$Device:M3334KIGAE$Flash\M3331_AP_512.FLM) -FP1($$Device:M3334KIGAE$Flash\M3331_LD_8.FLM) -FP2($$Device:M3334KIGAE$Flash\M3331_NS_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + applications\mnt.c + mnt.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + applications\pm_test.c + pm_test.c + 0 + 0 + + + + + board + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + board\NuPinConfig\nutool_pincfg.c + nutool_pincfg.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + board\NTFUN_board_dev.c + NTFUN_board_dev.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + board\NUTFT_board_dev.c + NUTFT_board_dev.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + board\custom_loader.c + custom_loader.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + board\nutool_modclkcfg.c + nutool_modclkcfg.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + cpuport.c + 0 + 0 + + + 3 + 14 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + syscall_rvds.S + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + trustzone.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 28 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\Device\Nuvoton\m3331\Source\startup_m3331.c + startup_m3331.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\Device\Nuvoton\m3331\Source\system_m3331.c + system_m3331.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_bpwm.c + drv_bpwm.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_bpwm_capture.c + drv_bpwm_capture.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_canfd.c + drv_canfd.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_clk.c + drv_clk.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_common.c + drv_common.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_crc.c + drv_crc.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_crypto.c + drv_crypto.c + 0 + 0 + + + 5 + 37 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_eadc.c + drv_eadc.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_ebi.c + drv_ebi.c + 0 + 0 + + + 5 + 39 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_ecap.c + drv_ecap.c + 0 + 0 + + + 5 + 40 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_epwm.c + drv_epwm.c + 0 + 0 + + + 5 + 41 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_epwm_capture.c + drv_epwm_capture.c + 0 + 0 + + + 5 + 42 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_eqei.c + drv_eqei.c + 0 + 0 + + + 5 + 43 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_fmc.c + drv_fmc.c + 0 + 0 + + + 5 + 44 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 5 + 45 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_i2c.c + drv_i2c.c + 0 + 0 + + + 5 + 46 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_i2s.c + drv_i2s.c + 0 + 0 + + + 5 + 47 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_llsi.c + drv_llsi.c + 0 + 0 + + + 5 + 48 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_pdma.c + drv_pdma.c + 0 + 0 + + + 5 + 49 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_qspi.c + drv_qspi.c + 0 + 0 + + + 5 + 50 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_rtc.c + drv_rtc.c + 0 + 0 + + + 5 + 51 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_sdio.c + drv_sdio.c + 0 + 0 + + + 5 + 52 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_softi2c.c + drv_softi2c.c + 0 + 0 + + + 5 + 53 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_spi.c + drv_spi.c + 0 + 0 + + + 5 + 54 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_spii2s.c + drv_spii2s.c + 0 + 0 + + + 5 + 55 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_timer.c + drv_timer.c + 0 + 0 + + + 5 + 56 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_tpwm.c + drv_tpwm.c + 0 + 0 + + + 5 + 57 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_uart.c + drv_uart.c + 0 + 0 + + + 5 + 58 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_ui2c.c + drv_ui2c.c + 0 + 0 + + + 5 + 59 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_uspi.c + drv_uspi.c + 0 + 0 + + + 5 + 60 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_uuart.c + drv_uuart.c + 0 + 0 + + + 5 + 61 + 1 + 0 + 0 + 0 + ..\libraries\m3331\rtt_port\drv_wdt.c + drv_wdt.c + 0 + 0 + + + + + Fal + 0 + 0 + 0 + 0 + + 6 + 62 + 1 + 0 + 0 + 0 + ..\..\..\components\fal\src\fal.c + fal.c + 0 + 0 + + + 6 + 63 + 1 + 0 + 0 + 0 + ..\..\..\components\fal\src\fal_flash.c + fal_flash.c + 0 + 0 + + + 6 + 64 + 1 + 0 + 0 + 0 + ..\..\..\components\fal\src\fal_partition.c + fal_partition.c + 0 + 0 + + + 6 + 65 + 1 + 0 + 0 + 0 + ..\..\..\components\fal\src\fal_rtt.c + fal_rtt.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c + devfs.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c + dfs_elm.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c + ff.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c + ffunicode.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs.c + dfs.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + dfs_file.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 8 + 74 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 9 + 79 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 9 + 80 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 9 + 81 + 1 + 0 + 0 + 0 + ..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 9 + 82 + 1 + 0 + 0 + 0 + ..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + 9 + 83 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 9 + 84 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 9 + 85 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 9 + 86 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 9 + 87 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 9 + 88 + 1 + 0 + 0 + 0 + ..\..\..\src\memheap.c + memheap.c + 0 + 0 + + + 9 + 89 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 9 + 90 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 9 + 91 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_comm.c + scheduler_comm.c + 0 + 0 + + + 9 + 92 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 9 + 93 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 9 + 94 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 9 + 95 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libc + 0 + 0 + 0 + 0 + + 10 + 96 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 10 + 97 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 10 + 98 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 10 + 99 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 10 + 100 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 10 + 101 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 10 + 102 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 10 + 103 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + 10 + 104 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 10 + 105 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 10 + 106 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 10 + 107 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 10 + 108 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 11 + 109 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_acmp.c + nu_acmp.c + 0 + 0 + + + 11 + 110 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_bpwm.c + nu_bpwm.c + 0 + 0 + + + 11 + 111 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_canfd.c + nu_canfd.c + 0 + 0 + + + 11 + 112 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_clk.c + nu_clk.c + 0 + 0 + + + 11 + 113 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_crc.c + nu_crc.c + 0 + 0 + + + 11 + 114 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_eadc.c + nu_eadc.c + 0 + 0 + + + 11 + 115 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ebi.c + nu_ebi.c + 0 + 0 + + + 11 + 116 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ecap.c + nu_ecap.c + 0 + 0 + + + 11 + 117 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ellsi.c + nu_ellsi.c + 0 + 0 + + + 11 + 118 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_epwm.c + nu_epwm.c + 0 + 0 + + + 11 + 119 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_eqei.c + nu_eqei.c + 0 + 0 + + + 11 + 120 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_fmc.c + nu_fmc.c + 0 + 0 + + + 11 + 121 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_gpio.c + nu_gpio.c + 0 + 0 + + + 11 + 122 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i2c.c + nu_i2c.c + 0 + 0 + + + 11 + 123 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i2s.c + nu_i2s.c + 0 + 0 + + + 11 + 124 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i3c.c + nu_i3c.c + 0 + 0 + + + 11 + 125 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_llsi.c + nu_llsi.c + 0 + 0 + + + 11 + 126 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_pdma.c + nu_pdma.c + 0 + 0 + + + 11 + 127 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_qspi.c + nu_qspi.c + 0 + 0 + + + 11 + 128 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_rtc.c + nu_rtc.c + 0 + 0 + + + 11 + 129 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_sdh.c + nu_sdh.c + 0 + 0 + + + 11 + 130 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_spi.c + nu_spi.c + 0 + 0 + + + 11 + 131 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_sys.c + nu_sys.c + 0 + 0 + + + 11 + 132 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_timer.c + nu_timer.c + 0 + 0 + + + 11 + 133 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_timer_pwm.c + nu_timer_pwm.c + 0 + 0 + + + 11 + 134 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_uart.c + nu_uart.c + 0 + 0 + + + 11 + 135 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_i2c.c + nu_usci_i2c.c + 0 + 0 + + + 11 + 136 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_spi.c + nu_usci_spi.c + 0 + 0 + + + 11 + 137 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_uart.c + nu_usci_uart.c + 0 + 0 + + + 11 + 138 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_wdt.c + nu_wdt.c + 0 + 0 + + + 11 + 139 + 1 + 0 + 0 + 0 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_wwdt.c + nu_wwdt.c + 0 + 0 + + + + + NuUTestCases + 0 + 0 + 0 + 0 + + 12 + 140 + 1 + 0 + 0 + 0 + test\canfd\utest_canfd.c + utest_canfd.c + 0 + 0 + + + 12 + 141 + 1 + 0 + 0 + 0 + test\clk\utest_clk.c + utest_clk.c + 0 + 0 + + + 12 + 142 + 1 + 0 + 0 + 0 + test\crc\utest_crypto.c + utest_crypto.c + 0 + 0 + + + 12 + 143 + 1 + 0 + 0 + 0 + test\hwtimer\utest_hwtimer.c + utest_hwtimer.c + 0 + 0 + + + 12 + 144 + 1 + 0 + 0 + 0 + test\pdma\utest_pdma.c + utest_pdma.c + 0 + 0 + + + 12 + 145 + 1 + 0 + 0 + 0 + test\rtc\utest_rtc.c + utest_rtc.c + 0 + 0 + + + 12 + 146 + 1 + 0 + 0 + 0 + test\template\utest_template.c + utest_template.c + 0 + 0 + + + 12 + 147 + 1 + 0 + 0 + 0 + test\uart\utest_uart.c + utest_uart.c + 0 + 0 + + + 12 + 148 + 1 + 0 + 0 + 0 + test\wdt\utest_wdt.c + utest_wdt.c + 0 + 0 + + + + + utc_UTest + 0 + 0 + 0 + 0 + + 13 + 149 + 1 + 0 + 0 + 0 + ..\..\..\components\utilities\utest\utest\TC_uassert.c + TC_uassert.c + 0 + 0 + + + + + UTest + 0 + 0 + 0 + 0 + + 14 + 150 + 1 + 0 + 0 + 0 + ..\..\..\components\utilities\utest\utest.c + utest.c + 0 + 0 + + + + + Utilities + 0 + 0 + 0 + 0 + + 15 + 151 + 1 + 0 + 0 + 0 + ..\..\..\components\utilities\ulog\ulog.c + ulog.c + 0 + 0 + + + 15 + 152 + 1 + 0 + 0 + 0 + ..\..\..\components\utilities\ulog\backend\console_be.c + console_be.c + 0 + 0 + + + + diff --git a/bsp/nuvoton/numaker-m3334ki/project.uvprojx b/bsp/nuvoton/numaker-m3334ki/project.uvprojx new file mode 100644 index 00000000000..a391a9de608 --- /dev/null +++ b/bsp/nuvoton/numaker-m3334ki/project.uvprojx @@ -0,0 +1,3116 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m3331 + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + M3334KIGAE + Nuvoton + Nuvoton.NuMicroM33_DFP.1.0.2 + https://github.com/OpenNuvoton/cmsis-packs/raw/master/Nuvoton_DFP/ + IRAM(0x20000000,0x60000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC4000 -FN3 -FF0M3331_AP_512 -FS00 -FL080000 -FF1M3331_LD_8 -FS1F100000 -FL12000 -FF2M3331_NS -FS210000000 -FL280000 -FP0($$Device:M3334KIGAE$Flash\M3331_AP_512.FLM) -FP1($$Device:M3334KIGAE$Flash\M3331_LD_8.FLM) -FP2($$Device:M3334KIGAE$Flash\M3331_NS.FLM)) + 0 + $$Device:M3334KIGAE$Device\M3331\Include\m3331.h + + + + + + + + + + $$Device:M3334KIGAE$SVD\Nuvoton\M3331.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf --bin ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.bin" + fromelf --text -c ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.txt" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 2 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 5 + 3 + 0 + 0 + 0 + 0 + 0 + + + __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS + + ..\..\..\components\net\utest;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\examples\utest\testcases\lwp;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\epoll;board\NuPinConfig;test\wdt;..\libraries\nu_packages\TPC;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\components\dfs\utest;..\..\..\components\drivers\include;packages\nuvoton-series-latest\CMSIS\Core\Include;test\rtc;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call\utest;..\..\..\components\drivers\core\utest;..\..\..\components\libc\posix\io\eventfd;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\libc\posix\io\poll;packages\nuvoton-series-latest\M3331\Device\Nuvoton\m3331\Include;test\template;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\utilities\utest;..\..\..\examples\utest\testcases\mm;test\hwtimer;..\..\..\examples\utest\testcases\tmpfs;..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\libraries\nu_packages\NuUtils\inc;test\uart;packages\nuvoton-series-latest\M3331\StdDriver\inc;board\NuClockConfig;test\canfd;..\..\..\components\drivers\ipc\utest;test\pdma;board;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;test\crc;..\..\..\components\drivers\serial\utest;..\libraries\m3331\rtt_port;..\..\..\src\utest\smp;..\..\..\components\utilities\ulog;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\phy;..\..\..\components\drivers\smp_call;.;test\clk;applications;..\..\..\components\libc\posix\ipc;..\..\..\src\utest;..\..\..\components\fal\inc + + + + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\linking_scripts\M3331.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + mnt.c + 1 + applications\mnt.c + + + pm_test.c + 1 + applications\pm_test.c + + + + + board + + + nutool_pincfg.c + 1 + board\NuPinConfig\nutool_pincfg.c + + + NTFUN_board_dev.c + 1 + board\NTFUN_board_dev.c + + + NUTFT_board_dev.c + 1 + board\NUTFT_board_dev.c + + + custom_loader.c + 1 + board\custom_loader.c + + + nutool_modclkcfg.c + 1 + board\nutool_modclkcfg.c + + + + + CPU + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + + + syscall_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + trustzone.c + 1 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_serial.c + 1 + ..\..\..\components\drivers\serial\dev_serial.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + startup_m3331.c + 1 + packages\nuvoton-series-latest\M3331\Device\Nuvoton\m3331\Source\startup_m3331.c + + + system_m3331.c + 1 + packages\nuvoton-series-latest\M3331\Device\Nuvoton\m3331\Source\system_m3331.c + + + drv_bpwm.c + 1 + ..\libraries\m3331\rtt_port\drv_bpwm.c + + + drv_bpwm_capture.c + 1 + ..\libraries\m3331\rtt_port\drv_bpwm_capture.c + + + drv_canfd.c + 1 + ..\libraries\m3331\rtt_port\drv_canfd.c + + + drv_clk.c + 1 + ..\libraries\m3331\rtt_port\drv_clk.c + + + drv_common.c + 1 + ..\libraries\m3331\rtt_port\drv_common.c + + + drv_crc.c + 1 + ..\libraries\m3331\rtt_port\drv_crc.c + + + drv_crypto.c + 1 + ..\libraries\m3331\rtt_port\drv_crypto.c + + + drv_eadc.c + 1 + ..\libraries\m3331\rtt_port\drv_eadc.c + + + drv_ebi.c + 1 + ..\libraries\m3331\rtt_port\drv_ebi.c + + + drv_ecap.c + 1 + ..\libraries\m3331\rtt_port\drv_ecap.c + + + drv_epwm.c + 1 + ..\libraries\m3331\rtt_port\drv_epwm.c + + + drv_epwm_capture.c + 1 + ..\libraries\m3331\rtt_port\drv_epwm_capture.c + + + drv_eqei.c + 1 + ..\libraries\m3331\rtt_port\drv_eqei.c + + + drv_fmc.c + 1 + ..\libraries\m3331\rtt_port\drv_fmc.c + + + drv_gpio.c + 1 + ..\libraries\m3331\rtt_port\drv_gpio.c + + + drv_i2c.c + 1 + ..\libraries\m3331\rtt_port\drv_i2c.c + + + drv_i2s.c + 1 + ..\libraries\m3331\rtt_port\drv_i2s.c + + + drv_llsi.c + 1 + ..\libraries\m3331\rtt_port\drv_llsi.c + + + drv_pdma.c + 1 + ..\libraries\m3331\rtt_port\drv_pdma.c + + + drv_qspi.c + 1 + ..\libraries\m3331\rtt_port\drv_qspi.c + + + drv_rtc.c + 1 + ..\libraries\m3331\rtt_port\drv_rtc.c + + + drv_sdio.c + 1 + ..\libraries\m3331\rtt_port\drv_sdio.c + + + drv_softi2c.c + 1 + ..\libraries\m3331\rtt_port\drv_softi2c.c + + + drv_spi.c + 1 + ..\libraries\m3331\rtt_port\drv_spi.c + + + drv_spii2s.c + 1 + ..\libraries\m3331\rtt_port\drv_spii2s.c + + + drv_timer.c + 1 + ..\libraries\m3331\rtt_port\drv_timer.c + + + drv_tpwm.c + 1 + ..\libraries\m3331\rtt_port\drv_tpwm.c + + + drv_uart.c + 1 + ..\libraries\m3331\rtt_port\drv_uart.c + + + drv_ui2c.c + 1 + ..\libraries\m3331\rtt_port\drv_ui2c.c + + + drv_uspi.c + 1 + ..\libraries\m3331\rtt_port\drv_uspi.c + + + drv_uuart.c + 1 + ..\libraries\m3331\rtt_port\drv_uuart.c + + + drv_wdt.c + 1 + ..\libraries\m3331\rtt_port\drv_wdt.c + + + + + Fal + + + fal.c + 1 + ..\..\..\components\fal\src\fal.c + + + fal_flash.c + 1 + ..\..\..\components\fal\src\fal_flash.c + + + fal_partition.c + 1 + ..\..\..\components\fal\src\fal_partition.c + + + fal_rtt.c + 1 + ..\..\..\components\fal\src\fal_rtt.c + + + + + Filesystem + + + devfs.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + dfs_elm.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + ff.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + ffunicode.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + dfs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + dfs_file.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + dfs_fs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + dfs_posix.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=c99 + + + + + + + + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + nu_acmp.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_acmp.c + + + nu_bpwm.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_bpwm.c + + + nu_canfd.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_canfd.c + + + nu_clk.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_clk.c + + + nu_crc.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_crc.c + + + nu_eadc.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_eadc.c + + + nu_ebi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ebi.c + + + nu_ecap.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ecap.c + + + nu_ellsi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_ellsi.c + + + nu_epwm.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_epwm.c + + + nu_eqei.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_eqei.c + + + nu_fmc.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_fmc.c + + + nu_gpio.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_gpio.c + + + nu_i2c.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i2c.c + + + nu_i2s.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i2s.c + + + nu_i3c.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_i3c.c + + + nu_llsi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_llsi.c + + + nu_pdma.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_pdma.c + + + nu_qspi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_qspi.c + + + nu_rtc.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_rtc.c + + + nu_sdh.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_sdh.c + + + nu_spi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_spi.c + + + nu_sys.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_sys.c + + + nu_timer.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_timer.c + + + nu_timer_pwm.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_timer_pwm.c + + + nu_uart.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_uart.c + + + nu_usci_i2c.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_i2c.c + + + nu_usci_spi.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_spi.c + + + nu_usci_uart.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_usci_uart.c + + + nu_wdt.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_wdt.c + + + nu_wwdt.c + 1 + packages\nuvoton-series-latest\M3331\StdDriver\src\nu_wwdt.c + + + + + NuUTestCases + + + utest_canfd.c + 1 + test\canfd\utest_canfd.c + + + utest_clk.c + 1 + test\clk\utest_clk.c + + + utest_crypto.c + 1 + test\crc\utest_crypto.c + + + utest_hwtimer.c + 1 + test\hwtimer\utest_hwtimer.c + + + utest_pdma.c + 1 + test\pdma\utest_pdma.c + + + utest_rtc.c + 1 + test\rtc\utest_rtc.c + + + utest_template.c + 1 + test\template\utest_template.c + + + utest_uart.c + 1 + test\uart\utest_uart.c + + + utest_wdt.c + 1 + test\wdt\utest_wdt.c + + + + + utc_UTest + + + TC_uassert.c + 1 + ..\..\..\components\utilities\utest\utest\TC_uassert.c + + + + + UTest + + + utest.c + 1 + ..\..\..\components\utilities\utest\utest.c + + + + + Utilities + + + ulog.c + 1 + ..\..\..\components\utilities\ulog\ulog.c + + + console_be.c + 1 + ..\..\..\components\utilities\ulog\backend\console_be.c + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/numaker-m3334ki/rtconfig.h b/bsp/nuvoton/numaker-m3334ki/rtconfig.h index 02c5e37b37b..f4b63dafb20 100644 --- a/bsp/nuvoton/numaker-m3334ki/rtconfig.h +++ b/bsp/nuvoton/numaker-m3334ki/rtconfig.h @@ -183,39 +183,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 2048 -#define RT_USING_CAN -#define RT_CANMSG_BOX_SZ 16 -#define RT_CANSND_BOX_NUM 1 -#define RT_CANSND_MSG_TIMEOUT 100 -#define RT_CAN_NB_TX_FIFO_SIZE 256 -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PULSE_ENCODER -#define RT_USING_INPUT_CAPTURE -#define RT_INPUT_CAPTURE_RB_SIZE 100 -#define RT_USING_PM -#define PM_TICKLESS_THRESHOLD_TIME 2 -#define RT_USING_RTC -#define RT_USING_SPI -#define RT_USING_SPI_ISR -#define RT_USING_QSPI -#define RT_USING_WDT -#define RT_USING_AUDIO -#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096 -#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2 -#define RT_AUDIO_RECORD_PIPE_SIZE 2048 -#define RT_USING_HWCRYPTO -#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto" -#define RT_HWCRYPTO_IV_MAX_SIZE 16 -#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256 -#define RT_HWCRYPTO_USING_CRC -#define RT_HWCRYPTO_USING_CRC_07 -#define RT_HWCRYPTO_USING_CRC_8005 -#define RT_HWCRYPTO_USING_CRC_1021 -#define RT_HWCRYPTO_USING_CRC_3D65 -#define RT_HWCRYPTO_USING_CRC_04C11DB7 #define RT_USING_PIN /* end of Device Drivers */ @@ -268,6 +235,10 @@ #define ULOG_OUTPUT_TAG /* end of log format */ #define ULOG_BACKEND_USING_CONSOLE +#define RT_USING_UTEST +#define UTEST_THR_STACK_SIZE 4096 +#define UTEST_THR_PRIORITY 20 +#define RT_UTEST_MAX_OPTIONS 64 /* end of Utilities */ /* Using USB legacy version */ @@ -277,6 +248,55 @@ /* RT-Thread Utestcases */ +#define RT_USING_UTESTCASES + +/* Kernel Core */ + +/* end of Kernel Core */ + +/* Kernel Components */ + +/* Drivers */ + + +/* IPC Test */ + +/* end of IPC Test */ + +/* Serial Test */ + +/* end of Serial Test */ + +/* SMP-Call Test */ + +/* end of SMP-Call Test */ +/* end of Drivers */ + +/* File System */ + +/* end of File System */ + +/* CPP11 */ + +/* end of CPP11 */ + +/* Network */ + +/* end of Network */ + +/* Utest Framework */ + +#define RT_UTEST_SELF_PASS +/* end of Utest Framework */ +/* end of Kernel Components */ + +/* Memory Management Subsytem Testcase */ + +/* end of Memory Management Subsytem Testcase */ + +/* Tmpfs Testcase */ + +/* end of Tmpfs Testcase */ /* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -498,91 +518,14 @@ #define SOC_FAMILY_NUMICRO #define SOC_SERIES_M3331 -#define BSP_USING_BPWM -#define BSP_USING_BPWM_CAPTURE -#define BSP_USING_BPWM0 -#define BSP_USING_BPWM1_CAPTURE -#define BSP_USING_BPWM2 -#define BSP_USING_BPWM3 -#define BSP_USING_BPWM4 -#define BSP_USING_BPWM5 -#define BSP_USING_CANFD -#define BSP_USING_CANFD0 -#define BSP_USING_CANFD1 -#define BSP_USING_CLK -#define BSP_USING_CRC -#define BSP_USING_CRC0 -#define BSP_USING_CRYPTO -#define BSP_USING_CRYPTO0 -#define BSP_USING_EADC -#define BSP_USING_EADC0 -#define BSP_USING_EPWM -#define BSP_USING_EPWM0 -#define BSP_USING_EPWM1 -#define BSP_USING_EQEI -#define BSP_USING_EQEI0 -#define BSP_USING_EQEI1 -#define BSP_USING_EQEI2 -#define BSP_USING_EQEI3 #define BSP_USING_FMC #define BSP_USING_GPIO -#define BSP_USING_I2C -#define BSP_USING_I2C0 -#define BSP_USING_I2C1 -#define BSP_USING_I2C2 -#define BSP_USING_I2C3 #define BSP_USING_PDMA #define BSP_USING_PDMA0 #define NU_PDMA_SGTBL_POOL_SIZE 16 #define NU_PDMA_MEMFUN_ACTOR_MAX 2 -#define BSP_USING_QSPI -#define BSP_USING_QSPI0 -#define BSP_USING_QSPI0_PDMA -#define BSP_USING_RTC -#define BSP_USING_RTC_INTERNAL -#define BSP_USING_SC -#define BSP_USING_SC0 -#define BSP_USING_SC1 -#define BSP_USING_SC2 -#define BSP_USING_SPI -#define BSP_USING_SPI_PDMA -#define BSP_USING_SPII2S -#define BSP_USING_SPI0 -#define BSP_USING_SPI0_PDMA -#define BSP_USING_SPII2S1 -#define BSP_USING_SPI2 -#define BSP_USING_SPI2_PDMA -#define BSP_USING_TMR -#define BSP_USING_TIMER -#define BSP_USING_TPWM -#define BSP_USING_TMR0 -#define BSP_USING_TPWM0 -#define BSP_USING_TMR1 -#define BSP_USING_TIMER1 -#define BSP_USING_TMR2 -#define BSP_USING_TMR3 -#define BSP_USING_TPWM3 #define BSP_USING_UART #define BSP_USING_UART0 -#define BSP_USING_UART1 -#define BSP_USING_UART2 -#define BSP_USING_UART3 -#define BSP_USING_UART4 -#define BSP_USING_UART5 -#define BSP_USING_USCI -#define BSP_USING_UUART -#define BSP_USING_USCI0 -#define BSP_USING_USCI1 -#define BSP_USING_UUART0 -#define BSP_USING_UUART0_TX_DMA -#define BSP_USING_UUART0_RX_DMA -#define BSP_USING_UUART1 -#define BSP_USING_UUART1_TX_DMA -#define BSP_USING_UUART1_RX_DMA -#define BSP_USING_HSUSBD -#define BSP_USING_HSUSBH -#define BSP_USING_HSOTG -#define BSP_USING_WDT /* end of On-chip Peripheral Drivers */ /* On-board Peripheral Drivers */ @@ -599,8 +542,9 @@ /* Nuvoton Packages Config */ #define NU_PKG_USING_UTILS -#define NU_PKG_USING_DEMO /* end of Nuvoton Packages Config */ /* end of Hardware Drivers Config */ +#define UTEST_CMD_PREFIX "bsp.nuvoton.utest." +#define BOARD_USE_UTEST #endif diff --git a/bsp/nuvoton/numaker-m467hj/rtconfig.h b/bsp/nuvoton/numaker-m467hj/rtconfig.h index b7317368f80..06ff141a208 100644 --- a/bsp/nuvoton/numaker-m467hj/rtconfig.h +++ b/bsp/nuvoton/numaker-m467hj/rtconfig.h @@ -694,7 +694,7 @@ /* Board extended module drivers */ -#define BOARD_USING_SENSON0_ID +#define BOARD_USING_SENSON0_ID /* end of Board extended module drivers */ /* Nuvoton Packages Config */